I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality?...

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I N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011

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Transcript of I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality?...

Page 1: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

I N

V E

N T

I V

E

EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality?

April 6, 2011

Page 2: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

2

Three Key Pillars of EDA360

© 2011 Cadence Design Systems, Inc. All Rights Reserved.

System Realization

SoC Realization

Silicon Realization

EDA360

Page 3: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

3

Three Key Pillars of EDA360

© 2011 Cadence Design Systems, Inc. All Rights Reserved.

EDA360

System Realization

SoC Realization

Silicon Realization

Page 4: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

4

Three Key Pillars of EDA360

© 2011 Cadence Design Systems, Inc. All Rights Reserved.

EDA360

System Realization

SoC Realization

Silicon Realization

Traditional EDA, including all the required technologies to design, verify, and implement silicon, packages, and boards

Page 5: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

5

Three Key Pillars of EDA360

© 2011 Cadence Design Systems, Inc. All Rights Reserved.

EDA360

System Realization

SoC Realization

Silicon Realization

Software content (IP), tools, and services that enable the delivery, integration, and support of high-quality IP required in complex SoCs

Traditional EDA, including all the required technologies to design, verify, and implement silicon, packages, and boards

Page 6: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

6

Three Key Pillars of EDA360

© 2011 Cadence Design Systems, Inc. All Rights Reserved.

EDA360

System Realization

SoC Realization

Silicon Realization

Software content (IP), tools, and services that enable hardware-aware system development and verification

Software content (IP), tools, and services that enable the delivery, integration, and support of high-quality IP required in complex SoCs

Traditional EDA, including all the required technologies to design, verify, and implement silicon, packages, and boards

Page 7: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

7

Silicon Realization – Customer Challenges

• Time to market– Disaggregated, global design chain

limits visibility and predictability forcomplex designs – causingschedule delays and respins

– Lack of true holistic and integratedsilicon-package-board flowscauses productivity gap

– Reuse

• Profitability– Design failure catastrophic– Functionality, performance, and power improvements

contribute to higher margins– Manufacturability

© 2011 Cadence Design Systems, Inc. All Rights Reserved.

Page 8: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

8

System Realization – Customer Challenges

• Software development trails hardware development, impacting time-to-market

• Hardware-software integration complexity impeding product shipments, quality

• Effective and predictable system and sub-system verification

© 2011 Cadence Design Systems, Inc. All Rights Reserved.

Page 9: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

9

System Realization – Market LandscapeDevelopment costs rising

© 2011 Cadence Design Systems, Inc. All Rights Reserved.

90nm 65nm 45nm 32nm 22nm$0

$20

$40

$60

$80

$100

$120

$140

$160

Mill

ions

Software

HW Implementationand Manufacturing

HW Design andVerification

Source: IBS 2009

Page 10: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

System Realization – Market LandscapeMarket window shrinking; growing penalties for delay

© 2011 Cadence Design Systems, Inc. All Rights Reserved.10

3 months

6 months

9 months

12 months

0% 2000% 4000% 6000%

IC Revenue Loss Due to Product Delay

Fast MarketMedium MarketSlow MarketP

rodu

ct D

elay

Source: IBS Percent Revenue Loss

Page 11: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

Application ApplicationApplication Application

Application Framework / GUI

Libraries

O/S

O/S RuntimesSystem

Sample Challenges at Each Realization Layer

SoC

Silicon

Test Programs

Mixed Signal Low Power Advanced Node

Giga-Gates/GHz DFMVerification

IP ConfigurationDrivers

PowerManagement…Scheduler

Hardware System Architecture

Page 12: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.12

Common Design Database

Page 13: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.13

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Page 14: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.14

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Page 15: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.15

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 16: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.16

Silicon Realization

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 17: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.17

Silicon Realization

Chip (Spec to GDSII)

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 18: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.18

Silicon Realization

Chip (Spec to GDSII)

Digital Flow (GigaGates/GHz)

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 19: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.19

Silicon Realization

Chip (Spec to GDSII)

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 20: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.20

Silicon Realization

Chip (Spec to GDSII)

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

RF Sub Flow

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 21: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.21

Silicon Realization

Chip (Spec to GDSII)

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

RF Sub Flow

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 22: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.22

Silicon Realization

Chip (Spec to GDSII)

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 23: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.23

Silicon Realization

Chip (Spec to GDSII) Package

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 24: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.24

Silicon Realization

Chip (Spec to GDSII) Package

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 25: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.25

Silicon Realization

Chip (Spec to GDSII) Package

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 26: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.26

Silicon Realization

Chip (Spec to GDSII) Package

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 27: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.27

Silicon Realization

Chip (Spec to GDSII) Package Board

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 28: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.28

Silicon Realization

Chip (Spec to GDSII) Package Board

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Layoutand

Routing

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 29: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.29

Silicon Realization

Chip (Spec to GDSII) Package Board

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Layoutand

Routing

AMSSimulation

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 30: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.30

Silicon Realization

Chip (Spec to GDSII) Package Board

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Layoutand

Routing

AMSSimulation

Signal andPower

Integrity

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 31: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.31

Silicon Realization

Chip (Spec to GDSII) Package Board

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Layoutand

Routing

AMSSimulation

FPGA andPCB

Codesign

Signal andPower

Integrity

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 32: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.32

Silicon Realization

Chip (Spec to GDSII) Package Board

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Layoutand

Routing

AMSSimulation

FPGA andPCB

Codesign

Signal andPower

Integrity

Silicon Realization

High-Quality IP

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 33: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.33

Silicon Realization

Chip (Spec to GDSII) Package Board

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Layoutand

Routing

AMSSimulation

FPGA andPCB

Codesign

Signal andPower

Integrity

Silicon Realization

High-Quality IP

Design IP

Synthesizable(Soft)

Process-Specific(Hard)

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 34: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.34

Silicon Realization

Chip (Spec to GDSII) Package Board

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Layoutand

Routing

AMSSimulation

FPGA andPCB

Codesign

Signal andPower

Integrity

Silicon Realization

High-Quality IP

Design IP

Verification IP

Synthesizable(Soft)

Process-Specific(Hard)

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 35: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.35

Silicon Realization

Chip (Spec to GDSII) Package Board

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Layoutand

Routing

AMSSimulation

FPGA andPCB

Codesign

Signal andPower

Integrity

Silicon Realization

High-Quality IP

Design IP

Verification IP

IP-CentricDesign Environment

Synthesizable(Soft)

Process-Specific(Hard)

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 36: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.36

Silicon Realization

Chip (Spec to GDSII) Package Board

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Layoutand

Routing

AMSSimulation

FPGA andPCB

Codesign

Signal andPower

Integrity

Silicon Realization

High-Quality IP

Design IP

Verification IP

IP-CentricDesign Environment

Synthesizable(Soft)

Process-Specific(Hard)

System Realization

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Page 37: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.37

Silicon Realization

Chip (Spec to GDSII) Package Board

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Layoutand

Routing

AMSSimulation

FPGA andPCB

Codesign

Signal andPower

Integrity

Silicon Realization

High-Quality IP

Design IP

Verification IP

IP-CentricDesign Environment

Synthesizable(Soft)

Process-Specific(Hard)

System Realization

Middleware OS Drivers

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Apps

Page 38: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.38

Silicon Realization

Chip (Spec to GDSII) Package Board

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Layoutand

Routing

AMSSimulation

FPGA andPCB

Codesign

Signal andPower

Integrity

Silicon Realization

High-Quality IP

Design IP

Verification IP

IP-CentricDesign Environment

Synthesizable(Soft)

Process-Specific(Hard)

System Realization

Hardware-Aware SoftwareDevelopment Environment

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Middleware OS DriversApps

Page 39: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.39

Silicon Realization

Chip (Spec to GDSII) Package Board

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Layoutand

Routing

AMSSimulation

FPGA andPCB

Codesign

Signal andPower

Integrity

Silicon Realization

High-Quality IP

Design IP

Verification IP

IP-CentricDesign Environment

Synthesizable(Soft)

Process-Specific(Hard)

System Realization

Hardware-Aware SoftwareDevelopment Environment

System-Level HardwareDesign Environment

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Middleware OS DriversApps

Page 40: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.40

Silicon Realization

Chip (Spec to GDSII) Package Board

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Layoutand

Routing

AMSSimulation

FPGA andPCB

Codesign

Signal andPower

Integrity

Silicon Realization

High-Quality IP

Design IP

Verification IP

IP-CentricDesign Environment

Synthesizable(Soft)

Process-Specific(Hard)

System Realization

Hardware-Aware SoftwareDevelopment Environment

System-Level HardwareDesign Environment

Virtual PrototypingEnvironment

System-Level SimulationSystem-Level Emulation

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Middleware OS DriversApps

Page 41: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 – The Technical Version

© 2011 Cadence Design Systems, Inc. All Rights Reserved.41

Silicon Realization

Chip (Spec to GDSII) Package Board

Digital Flow (GigaGates/GHz)

Mixed-Signal Flow

Custom/Analog Flow

Low-Power Flow

RF Sub Flow

SingleChip

MultiChip

2.5DAnd3D

Layoutand

Routing

AMSSimulation

FPGA andPCB

Codesign

Signal andPower

Integrity

Silicon Realization

High-Quality IP

Design IP

Verification IP

IP-CentricDesign Environment

Synthesizable(Soft)

Process-Specific(Hard)

System Realization

Hardware-Aware SoftwareDevelopment Environment

System-Level HardwareDesign Environment

Virtual PrototypingEnvironment

System-Level SimulationSystem-Level Emulation

System-Level Verification

Common Design Database

Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

Design Abstraction (models have multiple abstraction views for different tools)

Design Convergence (Get to the final design in an iterative but deterministic way)

Middleware OS DriversApps

Page 42: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

EDA360 Case Study: Agilent InfiniiVision Digital/Mixed-Signal Sampling Oscilloscope

© 2011 Cadence Design Systems, Inc. All Rights Reserved.42

Reproduced with Permission, Courtesy of Agilent Technologies, Inc.

Note: This case study is based on public, published data and nothing is implied about the EDA tools used to develop this product.

Page 43: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

Agilent InfiniiVision 2000/3000 DSO/MSO System Block Diagram

© 2011 Cadence Design Systems, Inc. All Rights Reserved.43

MeasurementBuffer(64K)

AcquisitionMemory Manager

DRAMADC Data

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Trigger

DisplayPlotter

DRAM

GUI Controller

Mask

WaveformSynthesis

A/D Converter

Measurement and Search

Acceleration*

User Interface Host

Processor

LCD PanelAnalog Signals

Digital Signals

Diagram as published in EE Times

* 23 automated measurements such as voltage, time, and frequency as well as four waveform math functions including FFT

Page 44: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

Agilent InfiniiVision 2000/3000 DSO/MSO System Intent

© 2011 Cadence Design Systems, Inc. All Rights Reserved.44

MeasurementBuffer(64K)

AcquisitionMemory Manager

DRAMADC Data

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Trigger

DisplayPlotter

DRAM

GUI Controller

Mask

WaveformSynthesis

A/D Converter

Measurement and Search

Acceleration

User Interface Host

Processor

LCD PanelAnalog Signals

Digital Signals

2 Gbytes/sec

4 Gbytes/sec

Diagram as published in EE Times

Page 45: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

Agilent InfiniiVision 2000/3000 DSO/MSO System Intent

© 2011 Cadence Design Systems, Inc. All Rights Reserved.45

MeasurementBuffer(64K)

AcquisitionMemory Manager

DRAMADC Data

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Trigger

DisplayPlotter

DRAM

GUI Controller

Mask

WaveformSynthesis

A/D Converter

Measurement and Search

Acceleration

User Interface Host

Processor

LCD PanelAnalog Signals

Digital Signals

2 Gbytes/sec

4 Gbytes/sec

>4 Gbytes/sec

Diagram as published in EE Times

Page 46: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

Agilent InfiniiVision 2000/3000 DSO/MSO System Intent

© 2011 Cadence Design Systems, Inc. All Rights Reserved.46

MeasurementBuffer(64K)

AcquisitionMemory Manager

DRAMADC Data

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Trigger

DisplayPlotter

DRAM

GUI Controller

Mask

WaveformSynthesis

A/D Converter

Measurement and Search

Acceleration

User Interface Host

Processor

LCD PanelAnalog Signals

Digital Signals

2 Gbytes/sec

4 Gbytes/sec

>4 Gbytes/sec

>>4 Gbytes/sec

Diagram as published in EE Times

Page 47: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

Agilent InfiniiVision 2000/3000 DSO/MSO System Partitioning

© 2011 Cadence Design Systems, Inc. All Rights Reserved.47

MeasurementBuffer(64K)

AcquisitionMemory Manager

DRAMADC Data

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Trigger

DisplayPlotter

DRAM

GUI Controller

Mask

WaveformSynthesis

A/D Converter

Measurement and Search

Acceleration

Processor running Win CE

LCD PanelAnalog Signals

Digital Signals

MegaZoom IV

SoC

Diagram as published in EE Times

Page 48: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

Agilent InfiniiVision 2000/3000 DSO/MSO System Partitioning

© 2011 Cadence Design Systems, Inc. All Rights Reserved.48

MeasurementBuffer(64K)

AcquisitionMemory Manager

DRAMADC Data

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Hardware SerialDecoders

(Simultaneous)

Trigger

DisplayPlotter

DRAM

GUI Controller

Mask

WaveformSynthesis

A/D Converter

Measurement and Search

Acceleration

Processor running Win CE

LCD PanelAnalog Signals

Digital Signals

MegaZoom IV

SoC

On-Chip DRAM allows High-Bandwidth

Connections

On-chip DRAM allows wide, high-bandwidth

connections

Diagram as published in EE Times

Page 49: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

Agilent MegaZoom IV SoC

© 2011 Cadence Design Systems, Inc. All Rights Reserved.49

Reproduced with Permission, Courtesy of Agilent Technologies, Inc.

Page 50: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

Agilent InfiniiVision 2000 X-Series DSO Circuit Board

© 2011 Cadence Design Systems, Inc. All Rights Reserved.50

Image courtesy of David Jones, www.eevblog.com

Page 51: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

Agilent InfiniiVision 2000 X-Series DSO Circuit Board

© 2011 Cadence Design Systems, Inc. All Rights Reserved.51

Image courtesy of David Jones, www.eevblog.com

Page 52: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

Detail: Board-Level Design Intent

© 2011 Cadence Design Systems, Inc. All Rights Reserved.52

Serpentines ensure that all analog inputs reach

the ADC simultaneously

Differential-pair serpentines ensure that all analog inputs reach

the ADC simultaneouslyImage courtesy of David Jones, www.eevblog.com

Page 53: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

Agilent InfiniiVision 2000 X-Series DSO Circuit Board

© 2011 Cadence Design Systems, Inc. All Rights Reserved.53

Quad 8-bit,1-Gsample/sec ADC

MegaZoom IVSOC

FPGA

ST Micro SPEAr600 MPU with two ARM9

processor cores

Image courtesy of David Jones, www.eevblog.com

Page 54: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

ST Microelectronics SPEAr600 Block Diagram

© 2011 Cadence Design Systems, Inc. All Rights Reserved.54

FPGA Interface

Page 55: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

Why use an ST Micro SPEAr600?

© 2011 Cadence Design Systems, Inc. All Rights Reserved.55

Less than $9 in production volumes!

Win CE Support

FPGA Interface

Page 56: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

56

Three Key Pillars of EDA360

© 2011 Cadence Design Systems, Inc. All Rights Reserved.

System Realization

SoC Realization

Silicon Realization

EDA360

Page 57: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

© 2011 Cadence Design Systems, Inc. All rights reserved.57

Questions and Answers

Page 58: I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

• v = (v 0 , v 1 , ..., v n-1 ) : code vector v (1) = (v n-1 , v 0 , v 1 , …, v n-2 )

• v = (v 0 , v 1 , ..., v n-1 ) : code vector v (1) = (v n-1 , v 0 , v 1 , …, v n-2 )

SCIENTIFIC ABSTRACT DANILOV, V. N. - DANILOV, V. YE. · title: scientific abstract danilov, v. n. - danilov, v. ye. subject: scientific abstract danilov, v. n. - danilov, v. ye. keywords

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EDA360 the Way Forward Vision

EDA360 the Way Forward Vision

Cadence OrCAD PCB Designer - FlowCAD · Cadence OrCAD PCB Designer Cadence is transforming the global electronics industry through a vision called EDA360. With an application-driven

Cadence OrCAD PCB Designer - FlowCAD · Cadence OrCAD PCB Designer Cadence is transforming the global electronics industry through a vision called EDA360. With an application-driven

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EDA360: The Way Forward for Electronic Design

EDA360: The Way Forward for Electronic Design

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The Way Forward for Electronic Design - IUMA - ULPGCnunez/IngTelySoc/CDNS EDA360 Vision Paper.… · they have continued to call upon their semiconductor partners for faster, better,

The Way Forward for Electronic Design - IUMA - ULPGCnunez/IngTelySoc/CDNS EDA360 Vision Paper.… · they have continued to call upon their semiconductor partners for faster, better,

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N-dimethylhydroxamidovanadium(V). Interactions with sulfhydryl … · 2007. 10. 26. · N,N-dimethylhydroxamidovanadium(V).Interactions with sulfhydryl-containing ligands: V(V) equilibria

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Vetores II. Combinação Linear Dados n vetores v 1, v 2,..., v n e n escalares a 1, a 2,..., a n o vetor v = a 1 v 1 + a 2 v 2 +... + a n v n, é a combinação.

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