Hysteresis modeling in graphene field effect tra · PDF file Hysteresis modeling in graphene...

Click here to load reader

  • date post

    21-Mar-2020
  • Category

    Documents

  • view

    0
  • download

    0

Embed Size (px)

Transcript of Hysteresis modeling in graphene field effect tra · PDF file Hysteresis modeling in graphene...

  • Hysteresis modeling in graphene field effect transistors

    M. Winters,1 E. €O. Sveinbj€ornsson,2 and N. Rorsman1 1Department of Microtechnology and Nanoscience, Chalmers University of Technology, 412-96 G€oteborg, Sweden 2Science Institute, University of Iceland, IS-107 Reykjavik, Iceland

    (Received 19 November 2014; accepted 7 February 2015; published online 19 February 2015)

    Graphene field effect transistors with an Al2O3 gate dielectric are fabricated on H-intercalated bilayer graphene grown on semi-insulating 4H-SiC by chemical vapour deposition. DC

    measurements of the gate voltage vg versus the drain current id reveal a severe hysteresis of clockwise orientation. A capacitive model is used to derive the relationship between the applied

    gate voltage and the Fermi energy. The electron transport equations are then used to calculate the

    drain current for a given applied gate voltage. The hysteresis in measured data is then modeled via

    a modified Preisach kernel. VC 2015 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4913209]

    I. INTRODUCTION

    Graphene has attracted a great deal of interest from

    diverse range of disciplines due to its unique band structure

    and electron transport properties. A wide range of graphene

    based technologies, including electrochemical sensors,1

    infrared detectors,2 and field effect transistors (FETs), have

    been presented. Particular interest has been directed towards

    the development of a graphene based technology for

    high frequency electronic devices. Though frequently

    observed,3–7 a theoretical treatment of field effect hysteresis

    in graphene FETs has not yet been presented in the context

    of experimental data.

    The field effect hysteresis is not unique to graphene.

    Gate hysteresis has been observed in a variety of semicon-

    ductor materials, such as AlGaAs/GaAs heterostructures,8,9

    AlGaN/GaN MOS heterostructures,10 and (4,6)H-SiC MOS

    structures.11,12 The hysteresis in MOS structures is usually

    attributed to charge trapping at the semiconductor/dielectric

    interface, ion drift within the insulator, or space charge

    effects related to dielectric polarization. Charge trapping

    generates a hysteresis of anti-clockwise orientation,9,13

    whereas polarization and space charge effects generate a

    hysteresis with clockwise orientation.14 Technology devel-

    opment often aims at the elimination of hysteretic phenom-

    ena for the purpose of reducing bias dependent instabilities.

    In addition to providing insight into the origin of the hystere-

    sis effect, an accurate model based on first principles

    provides a deeper understanding into the device physics and

    electron transport properties of MOS structures.

    Hysteresis is observed in graphene field effect transis-

    tors (GFETs) of many types, including exfoliated flakes,4,15

    transferred large area layers on SiO2 and SiO2/Si3N4, 16 and

    as-grown layers SiC grown by chemical vapour deposition (CVD)17 and sublimation. In this work, a drain hysteresis of

    similar character is clearly seen in H-intercalated CVD

    bilayer GFETs when measuring the drain current (id) as a function of gate voltage (vg). In the absence of hysteresis, the drain current density (J) may be calculated from the electron (n) and hole (p) densities by the following equation:

    J ¼ e½lnnð�f Þ þ lppð�f Þ�E: (1)

    The electron and hole densities are themselves a function of

    the Fermi energy (�f). During FET operation, �f is modulated by vg. In Eq. (1), e is the fundamental charge, ln,p are the electron and hole mobilities, and E is the electric field applied between source and drain.

    The objective of this work is to extend Eq. (1) to include

    a hysteretic effect and to apply quantitative hysteresis mod-

    els to GFET data. In Sec. II, the metal/oxide/semi-metal

    (MOSm) system is modeled as a capacitive divider, and a

    relation expressing the dependence of �f on vg is presented. The current saturation observed in graphene is modeled by

    considering Fermi level pinning interface effects. In Sec. III,

    the hysteresis is introduced by considering a hysteretic Fermi

    energy P½�f �. The operator P is a modified Preisach kernel which generates a hysteresis on �f. Given P½�f �, it is straight- forward to calculate the hysteretic current density via substi-

    tution of P½�f � for �f in Eq. (1). Details regarding device fabrication and material/device characterization are pre-

    sented in Sec. IV. Additional details regarding the computa-

    tional implementation of the Preisach kernel and hysteresis

    optimization are also presented. In Secs. V and VI, this

    model is applied to DC and low-frequency (LF) hysteresis

    measurements on the GFETs, and the resulting non-linear

    GFET models obtained from hysteresis optimization are

    shown. In Sec. VII, the physical origin of the hysteresis is

    discussed in the context of the experimental results.

    II. CAPACITANCE MODELING

    To generate P½�f �, it is necessary to find the relationship between the Fermi energy and gate voltage. A common

    approach is to model the MOSm structure as a capacitive

    divider (Figure 1).18 Here, Cox, Cq, and Cit represent the oxide, density of states (i.e., quantum), and interface charge

    capacitances per unit area, respectively.

    The following relation follows from voltage division:

    @v�f @vg ¼ Cox

    Cox þ Cit þ Cq : (2)

    0021-8979/2015/117(7)/074501/9/$30.00 VC 2015 AIP Publishing LLC117, 074501-1

    JOURNAL OF APPLIED PHYSICS 117, 074501 (2015)

    http://dx.doi.org/10.1063/1.4913209 http://dx.doi.org/10.1063/1.4913209 http://crossmark.crossref.org/dialog/?doi=10.1063/1.4913209&domain=pdf&date_stamp=2015-02-19

  • Here, v�f ¼ e�f represents the voltage at the graphene dielec- tric interface. Cq is obtained by differentiating the carrier density with respect to energy (Cq ¼ @vQ ¼ e@�ðenÞ)19,20

    e2@�n ¼ e2@� ð

    qð�Þf ð� : �f ; bÞd�

    � e2 ð

    qð�Þdð�� �f Þd�

    ¼ e2qð�f Þ: (3)

    In Eq. (3), the carrier density n(�f) is expressed as the product of the density of states in graphene q(�) and the Fermi Dirac distribution f(� : �f,b), where b ¼ ðkbTÞ�1. The integral is evaluated via the zero temperature approximation such that

    @�f ð� : �f ; bÞ � dð�� �f Þ. In AB-stacked bilayer graphene, the density of states is

    calculated from a tight binding Hamiltonian with one inter-

    layer coupling term (c?). The case of monolayer graphene is obtained by considering c?¼ 0. Taking the total density of states to be the sum of the low and high energy approxima-

    tions gives the following:21–23

    q �ð Þ ¼ gsgv 2p

    1

    �hvfð Þ2 j�f j þ

    c? 2

    � � : (4)

    Here, �h is the reduced Planck constant, gs,v are the spin and valley degeneracies, vf ¼ 108cm=s is the Fermi velocity in graphene, and c?� 0.4 eV is the interlayer coupling con- stant.21 In graphene, the ideal Cq exhibits a linear depend- ence on �f. It is useful to introduce a constant for the prefactor in Eq. (4)

    g ¼ gsgv 2p

    1

    �hvfð Þ2 : (5)

    The capacitance due to interface charge may be obtained

    similarly by Cit ¼ @vQit ¼ e2Ditð�f Þ. Substituting for Cq and Cit in Eq. (2) leads to the resulting differential equation

    @v @� ¼ 1

    e 1þ e

    2

    Cox q �ð Þ þ Dit �ð Þ½ �

    � � : (6)

    Substituting for q(�) and integrating over � 2 ½0; �f � and v 2 ½vD; vg� yields the following relation between the Fermi energy and the applied gate voltage:

    Dev ¼ �f þ e2g

    2Cox �2f þ �f c? � �

    þ e 2

    Cox

    ð�f 0

    Ditd�f : (7)

    Here, Dev ¼ eðvg � vDÞ, where vD is the Dirac voltage (i.e., the gate voltage where �f¼ 0). In Secs. II A and II B, two solutions to Eq. (7) are presented. In Sec. II A, the case of a

    constant Dit is examined, and in Sec. II B, the case of an empirically modeled Dit is considered. The empirically mod- eled case is selected to generate Fermi level pinning.

    A. Constant Dit

    In order to obtain a closed form solution to Eq. (7), it is

    useful to select a Dit(�f) to be a constant D 0 it. In this case, it is

    possible to obtain an analytic expression for Fermi energy as

    a function of gate voltage vg:

    Dev ¼ 1þ e2

    Cox

    gc? 2 þ D0it

    � " # �f þ

    e2g 2Cox

    � � �2f : (8)

    Solving for �f yields the following quadratic relation:

    �f ¼ 1

    2a 6

    ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 4aDevþ b2

    p � b

    h i ; (9)

    where the constants are given by the following:

    a ¼ e 2g

    2Cox

    b ¼ 1þ e 2

    Cox

    gc? 2 þ D0it

    � " # :

    (10)

    The effect of the quantum capacitance is to introduce a

    �f / ffiffiffiffiffiffiffiffi Dev p

    such that there is a weak saturating behavior in �f. The Dirac voltage introduces a shift into the function and

    can be estimated from experimental data. Reducing Cox and increasing D0it have the same effect of increasing b, which results in reduced gate control over �f.

    B. The Lorentz-d model

    Expe