HyperLynx DRC Basics Lab Instruction - Intel€¦ · HyperLynx DDR Wizard for Altera FPGA Design...

HyperLynx DDR Wizard for Altera FPGA Design Lab Instructions

11/10/2014 Nitin Bhagwath (Rev 1.0) © Mentor Graphics, 2014 of 27

HyperLynx DDR Wizard for Altera Arria 10 FPGA DDR4 Basic Lab Instructions

Revision1.0 (07/01/2015)

Lab Contents at a Glance Introduction .............................................................................................................................................................................................................................. 2

Overview – HyperLynx and Quartus. ....................................................................................................................................................................................... 2

Running HyperLynx ................................................................................................................................................................................................................. 2

Opening the Lab ................................................................................................................................................................................................................... 2

Board Setup.......................................................................................................................................................................................................................... 6

Running DDR Wizard ......................................................................................................................................................................................................... 11

Running Post-Process script.................................................................................................................................................................................................. 26

Conclusion ............................................................................................................................................................................................................................. 27

Summary ................................................................................................................................................................................................................................ 27

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Introduction Designing an FGPA on a board can be challenging. It involves several factors which need to be considered. While general PCB layout rules might be useful, they might be difficult to implement for the specific design under consideration due to various factors such as budget, time or other resource limitations. In such cases, simulating the board before release is an ideal way to mitigate risk. The HyperLynx DDR Wizard can help with such an effort when designing Altera FPGAs. This lab will detail a typical design example where the DDR3 subsystem is run through the HyperLynx simulation tool, and the results are fed into the Quartus design tool.

Overview – HyperLynx and Quartus. HyperLynx is a board level simulation tool which helps resolve the SI issues often present in PCB design. Within HyperLynx is a tool, the DDR Wizard, which is targeted to simulating the SI and timing requirements of DDR busses. Quartus is an FPGA design tool which helps in designing Altera FPGAs. In order to design the DDR controller subsystems within the FPGAs, certain information regarding the board is required. This lab outlines the obtaining of the information required by Quartus by using HyperLynx.

Running HyperLynx The following steps will outline how to run HyperLynx and the DDR Wizard in order to generate the required data for Quartus.

Opening the Lab 1-1. Open HyperLynx

1-2. Select File->Open Multi Board Project




1-3. Navigate to C:\Demos\Multiboard.

1-4. Open the file Aria10_DDR4.pjh

1-5. Click “No” when warned about the Manhattan Routing

1-6. Click “Ok” when warned about the board outline




1-7. The multi-board setup should open. Two board are visible – one is the main board with the controller, and the other is the Memory board with

the DRAMs.




Board Setup The following steps need to be done just once. Once verified, all subsequent runs will execute as expected. So, it is suggested that the first time the setup is run, the following setup steps are walked through. If any steps requires a change in the settings, it is suggested to make the change, and restart the program.

2-1. Click on “Setup->Stackup->Edit”

2-2. In this lab, the stackup has been setup to the appropriate values. In your actual design, you need to set this to the actual stackup of the PCB. You may vary the values given here to observe the effects. Click “OK” to get back to the board.




2-3. Click on the “Setup->Power Supplies”

2-4. Select the board “B01” under “Design File”, and make sure that the VTT rail is set to 0.6 volts. B01 is the DRAM board, and the VTT rail is the termination rail for the address signals. Click “OK” to get back to the board design.




2-5. Make sure that the area-fill return paths are seen as legitimate grounds. To do this, a. go to “Setup->Coupling Thresholds…”.




b. Select “Coupling Settings…”

c. Make sure that the “Include trace to area fill coupling” is selected with the shown values.




Running DDR Wizard 3-1. Start the DDR Wizard by clicking on “Simulate SI -> Run DDRx Batch Simulation”

3-2. Click “Next” on the introduction screen




3-3. In the “Initialization” page, select “DDR” as the interface, and “<Custom>” as the data rate. Manually enter in “2667” as the data rate. Leave the interface as “Unbuffered””. Click “Next”

3-4. In the “Controller” page, make sure that the “Board” file points to “B00 – Motherboard”. Scroll down to U28, click on the small square box next to it, and click on the arrow to the right to assign it as the controller. The Memory Controller will now change from “<none>” to “B00:U28”. Click Next




3-5. In the “DRAMs” page, there are several assignments to be made:

a. First change the number of Slots and the Ranks per Slots both to 1. b. Ensure that the Board is set to “B01 – DDR4 Daughtercard” c. Select U1, U2, U3, U4 and U5 by clicking on the small square next to U1, and while still holding the left mouse button, dragging down to

the small square next to U5 so that all five components are selected d. Then, select the rank these five DRAMs are to be assigned to by clicking on the small square next to Slot 1. e. Finally, click on the arrow key to assign the five DRAMs to the rank/slot




You might get an error saying that there might be a potential problem with this operation – select “Yes”

This should result in the five DRAMs being assigned to rank 1 of slot 1. Click “Next”.




3-6. In the “IBIS Models” page, click “Next”




3-7. In the “Nets to Simulate” page, make sure that the “Both Read and Write Cycles” is selected, and that the “Address Command and Control timing” is set to “1T timing”. Click “Next”.




3-8. In the “DRAM Signals” page, click on “Perform Automatic Net Mapping”. This will parse through the IBIS files to assign the nets to the appropriate groups. Once assigned, click on “Next”.




3-9. For the pages “Data Strobes”, “Data Nets”, “Clock Nets”, “Addr/Comm Nets” and “Control Nets”, make sure that the appropriate nets have been selected. In this lab, just click “Next” on each of the pages. In the “Disable Nets” page, select the nets that you want to simulate, and click “Next” If you are running it for the first time you might want to select them all.




3-10. In the “ODT Models” page, the buffer model settings for both the controller and the DRAMs are selected. There is only one option for this controller. However, for the DRAMs, there are several options. First, set the ODT settings for B01:U1 as shown in the diagram (34_2666 for models with ODT Disabled, and 34_ODT60_2666 for models with ODT Enabled). Then, click on the small square box next to B01:U1 to select the entire row. Finally, click on the “Apply These Settings to Similar DRAMs” to apply the settings for U1 to all the other DRAMs. Since U1, U2, U3 and U4 are the same type of DRAM, they will all be assigned to the same settings as U1 after clicking this button.

3-11.

Then, manually set similar ODT settings for U5 (34_2666 for model with ODT Disabled and 34_60_2666 for model with ODT Enabled)




Then, click “Next”

3-12. Click “Next” on the “ODT Behavior” page.

3-13. In the “IBIS Model Selectors” page, select List Item By as “Component”, and select the CLKIN and INPUT models to be “CLKIN_2666” and “INPUT_26”. Then click “Next”.




3-14. In the “Timing Models” page, change the timing numbers for the controller B00:U28 to ddr4_arria10_ctl.v, and all the DRAMs to ddr4_arria10_dram.v. To do this:

a. Click on “…browse” under the corresponding part’s “Model File” field

b. Select the file ddr4_arria10_ctl.v in the project directory for the FPGA, and ddr4_arria10_dram.v for the DRAMs. Click on “Verify All” to make sure that each timing file’s syntax is correct. Then click on “Next”.




3-15. For the pages “Write Leveling”, click “Next”

3-16. In the page “Vref Training”, make sure that the grouping is set to “Single Vref per lane”. This will create a common Vref for all bits in a given lane at the controller. Click “Next”.




3-17. For the “Stimulus and Crosstalk” page, click “Next”

3-18. In the Simulation Options, Unselect “Slow-weak”, Select the model corner as “Typical”, then click “Next”




3-19. Click on “Next” for the “Quality Checks” and “Report Options” pages. Click on “Run Batch Simulations…” in the “Simulate” page 3-20. After clicking Next in the Quality Checks tab you will see this 'Info’ box. Click OK

.

.




3-21. When prompted to save the setup, provide a File Name, such as “DDR4Setup.ddr” (or any name for your convenience)

3-22. If prompted, click “OK” to run

3-23. Once the simulation is complete the result folder will be created. This folder will be stored under C:\Demos\Multiboard. Name of the

folder will be DDR_Results_[time-stamp].




Running Post-Process script This script helps to analyze the results generated by the HyperLynx DDRx Batch Simulation Wizard when used to simulate external memory interfaces. The input to the tool is the result Excel files generated by the HyperLynx DDRx Batch Simulation, and the output of the tool is the calculated channel loss values needed in the Arria 10 External Memory Interface IP. More information about the tool can be found here: http://www.alterawiki.com/wiki/Calculating_Channel_Loss_from_DDRx_Batch_Wizard_Results

4-1 Browse to folder C:\Demos

4-2 Open Channel_Loss.xlsm

4-3 Click ‘Import Data’

4-4 Navigate into the C:\Demos\MultiBoard\DDR_Results<timestamp> directory. Click OK

4-5 Click Run Program. A pop will open asking you to input frequency. Enter interface frequency 1066 Mhz here

Input: Result files generated by DDRx

Batch Simulation

Channel Loss Calculation Tool

Output: Channel loss values to be

entered in Quartus




4-6 The tool will calculate and display the channel loss numbers to be entered in the Quartus II during EMIF IP generation process. Please note that what you see below is a result of a simulation on a limited set of pins. You may or may not see the same exact result for the pins that you have selected during simulation.

Descriptions Net name Absolute value (ns)

Address and command ISI/crosstalk MEM_ADDR_CMD0 0.118

Read DQS/DQS# ISI/crosstalk N/A Keep default value

Read DQ ISI/crosstalk MEM_DQA1 0.06

Write DQS/DQS# ISI/crosstalk N/A Keep default value

Write DQ ISI/crosstalk MEM_DQA1 0.057

Conclusion Summary By following the instructions on this document, the user will be able to adopt the benefits of the DDRx Wizard batch simulation to validate the QDR IV bus.


HyperLynx DRC Basics Lab Instruction - Intel€¦ · HyperLynx DDR Wizard for Altera FPGA Design...

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