Hybrid Plasmonic Waveguides and Devices:

Theory, Modeling and Experimental Demonstration

by

Xiao Sun

A thesis submitted in conformity with the requirements for the degree of Master of Applied Science

Graduate Department of Electrical and Computer Engineering University of Toronto

© Copyright by Xiao Sun, 2013

ii

Hybrid Plasmonic Waveguides and Devices: Theory, Modeling and Experimental Demonstration

Xiao Sun Master of Applied Science

Graduate Department of Electrical and Computer Engineering University of Toronto

2013

Abstract

This thesis prompt a theoretical analysis of the hybrid plasmonic waveguide (HPWG) and

a TE-pass polarizer based on HPWG has been designed, fabricated and characterized.

A combination of low propagation loss, high power density, and large confinement is

useful for many applications. The analysis results in this thesis show that the HPWG

offers a better compromise between loss and confinement as compared to pure plasmonic

waveguides.

Another interesting property of the HPWG is its polarization diversity. In the HPWG the

TE and the TM modes reside in different layers. We have designed a very compact

hybrid TE-pass polarizer using this property. The polarizer was fabricated and

characterized. The device shows low insertion loss for the TE mode with a high

extinction ratio at telecommunication wavelength range for a 30 µm long HPWG section.

Its performance compares favorably against previously reported silicon based integrated

optic TE-pass polarizers.

iii

Acknowledgements

First of all, I would like to thank my supervisors, Professor Mo. Mojahedi and Professor Stewart

Aitchison for giving me a great chance to work in such a creative group. Their guidance and

support throughout the course of the research have helped me achieve a successful completion of

my master degree.

I offer my special thanks to Muhammad Zulfiker Alam for his patient guidance and

encouragement during my research.

I would like to thank Henry Lee, Yimin Zhou, Edward Xu, Harlan Kuntz, and Aju Jugessur at the

Emerging Communications Technology Institute for their help in the device fabrications.

I would like to give my thanks to Sean Wager and Ksenia Dolgaleva for the help in the

device characterization.

I would like to thank all the professors in my thesis committee for giving me suggestions and all

my friends at the University of Toronto for their help in my research and school life.

Finally, I would like to thank my family for their support in my life.

iv

Table of Contents

Abstract ............................................................................................................................... ii 

Acknowledgements ............................................................................................................ iii 

List of Figures .................................................................................................................... vi 

List of Tables ...................................................................................................................... x 

List of Acronyms and Symbols.......................................................................................... xi 

Chapter 1 Introduction ........................................................................................................ 1 1.1 Background and Contributions ............................................................................. 1 1.2 Thesis Outline ....................................................................................................... 3 

Chapter 2 Literature Review ............................................................................................... 5 2.1 Surface Plasmon Polaritons .................................................................................. 5 2.2 Plasmonic Waveguides ....................................................................................... 13 2.3 Hybrid Plasmonic Waveguides Applications ..................................................... 16 

Chapter 3 Properties of Hybrid Plasmonic Waveguides and Confinement Comparison of Plasmonic Waveguides ..................................................................................................... 20 

3.1 Numerical Analysis Methods .............................................................................. 20 3.2 Properties of Hybrid Plamonic Waveguide ........................................................ 21 

3.2.1 Introduction to HPWG structure .............................................................. 21 3.2.2 Hybrid mode in one dimensional structure .............................................. 22 3.2.3 Mode transition as a function of dielectric thickness ............................... 25 

3.3 Comparison of Sub-wavelength Confinement and Loss of Plasmonic Waveguides ............................................................................................................... 27 

3.3.1 Analyzed waveguide structures ............................................................... 28 3.3.2 Method of comparision ............................................................................ 30 3.3.3 Confinement achievable in case of a dielectric waveguide ..................... 31 3.3.4 Properties of DLSPW .............................................................................. 32 3.3.5 Properties of plasmonic slot waveguide .................................................. 34 3.3.6 Properties of HPWG ................................................................................ 36 3.3.7 Comparison of various plasmonic waveguides........................................ 38 

3.4 Conclusion .......................................................................................................... 40 

Chapter 4 Design and Optimization of the Hybrid Plasmoinc Waveguide as a TE-pass Polarizer ............................................................................................................................ 41 

4.1 Background ......................................................................................................... 41 4.2 TE-pass Polarizer Design Overview ................................................................... 42 

4.2.1 Input/output waveguides .............................................................................. 43 4.2.2 Functional HPWG section ........................................................................... 44 

4.3 Device Optimization Process .............................................................................. 46 4.3.1 Chromium cap dimension ............................................................................ 47 

v

4.3.2 Silica spacer dimension ............................................................................... 48 4.4 Coupling Efficiency between Sections ............................................................... 50 4.5 Full Device Simulation ....................................................................................... 51 4.6 Conclusion .......................................................................................................... 54 

Chaper 5 Device Fabrication ............................................................................................ 55 5.1 Fabrication Process Overview ............................................................................ 55 5.3 Device Layout and Pattern Design with L-Edit .................................................. 57 5.4 Electron Beam Lithography and Dose Test ........................................................ 58 5.5 Gold Markers ...................................................................................................... 63 5.6 Silicon Nano Waveguide Etching ....................................................................... 66 5.7 Silica Deposition ................................................................................................. 68 5.8 Chromium Deposition and Lift-off ..................................................................... 70 5.9 Final Device ........................................................................................................ 72 5.10 Conclusion ........................................................................................................ 74 

Chapter 6 Optical Characterization ................................................................................... 75 6.1 Experimental Setup and Measurement Method ........................................................ 75 6.2 Optical Characterization Results ......................................................................... 77 6.3 Conclusion .......................................................................................................... 81 

Chaper 7 Conclusion and Future works ............................................................................ 82 7.1 Summary of the Contributions ............................................................................ 82 7.2 Future Works ...................................................................................................... 83 

Appendix A Optimizion of Silicon Width for Confinement of HPWG ........................... 84 

References ......................................................................................................................... 85 

List of Publications ........................................................................................................... 88 

vi

List of Figures

Fig.2.1. (a) Single metal-dielectric interface and field profile of SP mode. (b) Schematic illustration of the electric field decay in both dielectric and metal layers. ................................................................................................................. 6 

Fig.2.2. Dispersion relation of SPP at the interface between a Drude metal with negligible damping and a dielectric material. ................................................... 11 

Fig.2.3. Prism coupling to SPP in the (a) Otto and (b) Kretschmann configuration. 12 Fig.2.4. Phase-matching of light to SPP using a grating. ......................................... 12 Fig.2.5. Structure of different types of plasmonic waveguide. (a) LRSPP waveguide.

(b) DLSPW. (c) plasmonic slot waveguide. (d) Metal wedge waveguide. (e) V-groove channel waveguide. (f) HPWG. ............................................................ 14 

Fig.2.6. Optical devices based on the HPWG. (a) Plasmonic laser. (b) Electro-optical modulator. (c) Light concentrator. (d) Ring resonance biosensor. ................... 18 

Fig.3.1. Schematic of the hybrid waveguide. ............................................................ 22 Fig.3.2. Formation of the hybrid plasmonic mode. (a) The hybrid plasmonic

waveguide combines the structure of dielectric waveguide and plasmonic waveguide. (b) TM mode of three waveguides. (c) TE mode of three waveguides ........................................................................................................ 24 

Fig.3.3. Field intensity of the TM and TE mode for the HPWG with silicon slab thickness 220 nm, spacer thickness 100 nm. .................................................... 24 

Fig.3.4. HPWG structure and field profiles. (a) One-dimensional HPWG structure. (b) Electric filed intensity profile for varying silicon thickness (d). Spacer thickness is fixed at 100 nm. ............................................................................. 26 

Fig.3.5. Power confinement and loss for the HPWG. (a) Power confinement for different dielectric layer thickness. (b) Propagation loss for different dielectric layer thickness. .................................................................................................. 27 

Fig.3.6. Analyzed waveguide structures. (a) Dielectric loaded surface plasmon waveguide. (b) Plasmonic slot waveguide. (c) Hybrid plasmonic waveguide. (d) Silicon waveguide. ............................................................................................ 30 

Fig.3.7. (a) Structure of the silicon waveguide. (b) Guided power distribution in the silicon waveguide. ............................................................................................. 31 

Fig.3.8. (a) Confinement factor and (b) power density of the silicon dielectric waveguide ......................................................................................................... 32 

Fig.3.9. (a) Structure of the DLSPW structure. (b) Guided power distribution in the DLSPW. ............................................................................................................ 32 

Fig.3.10. Confinement factor and power density associated with loss for the DLSPW. (a) Confinement factor. (b) Power density. (c) Propagation loss. (d) Power density vs. propagation loss ................................................................... 33 

Fig.3.11. (a) Structure of the plasmonic slot waveguide. (b) Guided power distribution in the plasmonic slot waveguide. ................................................... 34 

Fig.3.12. Confinement factor and power density associated with loss for the plasmonic slot waveguide. (a) Confinement factor. (b) Power density. (c) Propagation loss. (d) Power density vs. propagation loss ................................. 35 

vii

Fig.3.13. (a) Structure of the HPWG. (b) Guided power distribution in the HPWG............................................................................................................................ 36 

Fig.3.14. Confinement factor and Power Density associated with Loss for the HPWG with w= 200 nm. (a) Confinement factor. (b) Power density. (c) Propagation loss. (d) Power density vs. propagation loss ................................. 37 

Fig.3.15. Normalized power density vs. propagation loss for three types of plasmonic waveguides. ..................................................................................... 38 

Fig.3.16. Confinement factor vs. propagation loss for three types of plasmonic waveguides. ....................................................................................................... 39 

Fig.4.1. (a) Three dimensional schematic of the HPWG TE-pass polarizer with input

and output silicon waveguides. (b) Cross section of the HPWG. (c) Cross section of the input/output silicon waveguide. The final dimensions are H = 220 nm, T = 3 μm, w = 500 nm, w′ = 250 nm, h = 200 nm, t =100 nm. ............... 42 

Fig.4.2. Electric field intensity profiles at 1.55 μm for the (a) TE and (b) TM modes of the input/output waveguides for H = 220 nm, T = 3 μm, w = 500 nm, h = 200 nm. The definition of the variables is shown in (c). ......................................... 44 

Fig.4.3. Electric field intensity profiles of the (a)TE and (b) TM modes of the HPWG section for H = 220 nm, T = 3 μm, w = 500 nm, w′ = 250 nm, h = 200 nm, t =100 nm. Wavelength of operation is 1.55μm. The definition of the variables is shown in (c). .................................................................................. 45 

Fig.4.4. Propagation loss with different chromium cap width (w′) for H = 220 nm, T = 3 μm, w = 500 nm, h = 200 nm, t =100 nm. Wavelength of operation is 1.55μm. For the definition of the variables, see Fig. 4.1. (a) TE mode. (b) TM mode .................................................................................................................. 47 

Fig.4.5. Propagation loss with different chromium cap thickness (t) for H = 220 nm, T = 3 μm, w = 500 nm, w′ = 250 nm, h = 200 nm. (a) TE mode. (b) TM mode. ................................................................................................................. 48 

Fig.4.6. Propagation loss for the (a) TE mode and (b) TM mode. (c) HPWG length for 30 dB extinction ratio. (d) Propagation loss of the TE mode for length calculated in (c). The plots are with different spacer thickness (h) with other dimensions fixed of H = 220 nm, T = 3 μm, w = 500 nm, w′ = 250 nm, and t = 100 nm. .......................................................................................................... 49 

Fig.4.7. Insertion loss of a 30 μm long TE-pass polarizer predicted by FDTD simulation. Device dimensions are as mentioned in the caption of Fig. 1. (a) Variation of insertion loss for the TM mode. (b) Variation of insertion loss for the TE mode with silicon width (w). ................................................................. 52 

Fig.4.8. Power in the chromium layer and adjacent regions for the (a) TE mode and (b) TM mode with variation of silicon width (w). ............................................ 53 

Fig.4.9. Insertion loss of a 30 μm long TE-pass polarizer predicted by FDTD simulation. Device dimensions are as mentioned in the caption of Fig. 1. (a) Variation of insertion loss for the TM mode. (b) Variation of insertion loss for the TE mode with spacer thickness (h). ............................................................ 54 

viii

Fig.5.1. Fabrication process flow of the HPWG TE-pass polarizer. (a) SOI substrate. (b) Resist spin-coating and EBL for gold markers. (c) Gold deposition. (d) Gold lift-off. (e) Resist spin-coating and EBL for silicon nano waveguide (markers are not shown in this and following steps because they are far from waveguides). (f) RIE etching and resist removal. (g) Silica deposition by PECVD. (h) Resist spin-coating and EBL. (f) Chromium deposition and lift-off............................................................................................................................ 56 

Fig.5.2. Design and Layout pattern of the polarizer. (a) Designed device. (b) Layout for one polarizer. ............................................................................................... 57 

Fig.5.3. L-Edit Layout pattern of the polarizer. (a) Overview of the pattern; (b) close view of the polarizers in one block. .................................................................. 58 

Fig.5.4. Low dose results in resist residues even for large areas. (Resist thickness is 340 nm, and fracture resolution is 10 nm) ........................................................ 60 

Fig.5.5. Dose test for the ridge drawn in L-edit as 700 nm wide. (Resist thickness is 340 nm, and fracture resolution is 10 nm) ........................................................ 60 

Fig.5.6. Dose test for trench drawn in L-edit as 100 nm wide. (Resist thickness is 340 nm, and fracture resolution is 10 nm) ........................................................ 61 

Fig.5.7. dose test for the ridge drawn in L-edit as 700 nm wide. (Resist thickness is 340 nm, and fracture resolution is 25 nm) ........................................................ 62 

Fig.5.8. dose test for the ridge drawn in L-edit as 700 nm wide. (Resist thickness is 500 nm, and fracture resolution is 10 nm) ........................................................ 63 

Fig.5.9. Fabrication steps for alignment makers. (a) SOI wafer. (b) Spin coat ZEP resist. (c) Define maker shape and dimensions by E-beam writing. (d) Chromium deposition by thermal evaporation. (e) Gold deposition by thermal evaporation. (f) Lift-off process. (g) Top view of SOI wafer with gold markers............................................................................................................................ 64 

Fig.5.10 (a) Gold marker covered by ZEP. (b-c) Gold marker after ebeam writing and development. (d) Gold marker covered by silica ....................................... 66 

Fig.5.11. Fabrication steps for silicon waveguides. (a) Spin coat ZEP resist. (b) Define silicon waveguide pattern by E-beam writing. (c) RIE etch the uncovered silicon. (d) Resist removal. (e) Top view of silicon waveguides with markers. ............................................................................................................. 67 

Fig.5.12. Silicon nano waveguides etched by RIE has slanted sidewalls. ................ 68 Fig.5.13. SEM picture of the 205 nm silica layer deposited over the whole sample by

PECVD. (a) Silicon waveguide under silica cladding. (b) Close view of the surface of the deposited silica. .......................................................................... 70 

Fig.5.14. Fabrication steps for hybrid section metal lift-off. (a) Spin coat ZEP resist. (b) Define metal pattern by E-beam writing. (c) Deposit chromium by thermal evaporation. (d) Lift-off ZEP resist. (e) Top view of the final device. ............. 71 

Fig.5.15. SEM picture of the rough surface of deposited chromium ........................ 71 Fig.5.16. Fabricated device with silicon reference nano waveguides and TE

polarizers of different HPWG lengths. ............................................................. 72 Fig.5.17. SEM images of (a) the cross section of the input/output/reference silicon

nano waveguides, (b) the cross section of HPWG section, (c) top view of the HPWG section, and (d) a closer top view of the HPWG section. .................... 73 

ix

Fig.5.18. A sample with around 70 nm misalignment. SEM images of (a) the cross section of the HPWG section and (b) top view of the HPWG section. ............ 74 

Fig.6.1. Experiment setup to measure the power transmission through waveguides.

........................................................................................................................ 76 Fig.6.2. Camera images of mode output profile for TE and TM mode at 1.55 μm

from the reference silicon waveguide and from the polarizer with a 30 μm HPWG section. ................................................................................................. 78 

Fig.6.3. Insertion losses of the TE and TM modes for a 30 μm long HPWG TE-pass polarizer. ........................................................................................................... 79 

Fig.6.4. Extinction ratios for a 30 μm long HPWG TE-pass polarizer. .................... 80  Fig.A.1. Confinement factor and Power Density for HPWG with w. (a)

Confinement factor. (b) Power density. ............................................................ 84 

x

List of Tables

Table 4.1 Effective indices and coupling efficiency for the TE and TM modes at 1.55 μm ........................................................................................................ 51

Table 5.1: RIE etching recipe for silicon waveguides .............................................. 67 Table 5.2: PECVD silica deposition recipe at 300 C ................................................ 69 

xi

List of Acronyms and Symbols

CMOS Complementary metal–oxide–semiconductor

DLSPW dielectric loaded surface plasmon waveguide(s)

DRIE Deep Reactive Ion Etching

ECTI Emerging Communication Technology Institute

EBL Electron Beam Lithography

FDTD Finite-Difference Time-Domain

FP Fabry-Perot

HPWG Hybrid Plasmonic Waveguide(s)

PBS polarizing beam splitter / polarizing beam cube

PECVD Plasma-enhanced chemical vapor deposition

RF Radio Frequency

RIE Reactive Ion Etching

SOI Silicon-on-Insulator

SPP Surface Plasmon Polaritons

TE Transverse Electric

TM Transverse Magnetic

E Electric Field

H Magnetic Field

β Effective Propagation Constant

ε Dielectric Permittivity

εr Relative Dielectric Permittivity

λ Wavelength

λspp Surface Plasmon Polariton Wavelength

k Wave vector/Momentum/Phase constant

ωp Bulk Plasmon Frequency

ωspp Characteristic Surface Plasmon Frequency

1

Chapter 1 Introduction

1.1 Background and Contributions

Waveguides have been designed for many different applications and are important

components in integrated optical circuits. To increase the integration density, compact

circuits are preferred. One approach to achieve this is to use high refractive index contrast

waveguides, for example, silicon waveguides with silica or air cladding. Silicon

waveguides can guide light in a more confined manner than can be achieved using low

index contrast waveguides. Silicon waveguides are compatible with CMOS

(Complementary metal–oxide–semiconductor) technology; thus they offer the possibility

for integrating electronics and photonics in the same material platform and have attracted

much interest [1]. Since silicon is transparent in the near-infrared range, silicon

waveguides have very low loss and are widely used in telecommunication. However, the

mode size achievable with a silicon waveguide is still limited by the diffraction. Another

emerging technology is plasmonics, i.e., the application of surface plasmons polaritons

(SPP). Surface plasmon polaritons (SPP) are electromagnetic waves propagating along

metal-dielectric surface in the optical spectrum (visible or infrared light) [2-4]. SPP have

a shorter wavelength and the waveguides based on SPP (plasmonic waveguides) can

break the diffraction limit. They offer the possibility of increased integration density for

optical circuits. At the same time, metal has a complex refractive index and as a result

plasmonic waveguides suffer from significant propagation loss.

2

It is important to compare different plasmonic waveguides and identify the best

waveguide design for various applications to fully realize the potential of plasmonics. A

combination of low propagation loss, high power density, and large confinement will be

useful for many applications of plasmonic waveguides including nonlinear optics [5] and

biosensing [6, 7]. Many kinds of plasmonic waveguides have been proposed for

nanophotonic applications [8-15]. In this thesis we compare some of the popular

plasmonic waveguides including the dielectric loaded surface plasmon waveguide

(DLSPW) [8], the plasmonic slot waveguide [9], and the hybrid plasmonic waveguide

(HPWG) [10-14] with a view to identifying their relative advantages and limitations.

The HPWG consists of a metal layer separated from a high index material by a low index

spacer. The HPWG combines both dielectric and plasmonic guiding schemes and forms a

hybrid guiding scheme. The hybrid mode in the HPWG is concentrated in the low index

region and offers a better compromise between loss and confinement as compared to a

purely plasmonic mode [11]. When silicon is chosen as the high index material and silica

as the low index material, the fabrication of the HPWG is compatible with silicon-on-

insulator (SOI) technology. The HPWG offers the possibility of successful integration of

silicon photonics and plasmonics on the same platform. In addition, the HPWG supports

both the transverse electric (TE) and the transverse magnetic (TM) modes in two

different layers and offers the possibility of developing devices which can manipulate the

two polarizations independently.

3

Based on the property of polarization diversity of the HPWG, a TE-pass polarizer has

been designed. Besides the theoretical work, we have experimentally demonstrated the

application of the HPWG by implementing a TE-pass polarizer for SOI platform. The

device structure is carefully designed to achieve a short length and optimized for ease of

fabrication. The device has been characterized and its performance compares favorably

against previously reported silicon based integrated optic TE-pass polarizers.

1.2 Thesis Outline

The rest of the thesis is organized as follows:

The background information on plasmonic waveguides is described in chapter 2. In this

chapter we present a brief review of the fundamental theory of plasmonics. Both the

dispersion and spatial profile are discussed for the simple single-interface metal-dielectric

structure. Furthermore, we give a brief introduction to some of the popular plasmonics

waveguides. Finally, we discuss the some of the applications based on the HPWG.

In chapter 3, we investigate the structure and underlying theory of the HPWG and its

mode characteristics. In order to understand the properties and suitable applications of

various plasmonic waveguides, the confinement and propagation loss of some popular

plasmonic waveguides have also been compared in this chapter.

4

The theory of operation of the TE-pass polarizer based on the HPWG and optimization

for dimensions are presented in chapter 4. The relation of the dimensions and

performance has been carefully analyzed. The designed polarizer is compact and has a

high extinction ratio. The fabrication simplicity and smooth coupling from input/output

waveguides are also considered.

The polarizer is fabricated in the cleanroom of ECTI (Emerging Communication

Technology Institute) Open Research Facility. Its fabrication is fully compatible with the

SOI technology. The fabrication process is described in chapter 5.

The results of the device characterization are described in chapter 6. The power output of

the TE-pass polarizer waveguide has been compared to that of the reference waveguide to

measure the device insertion loss. The experimental results match well with simulations.

The summary of our work and consideration for future work are described in chapter 7.

5

Chapter 2 Literature Review

In this chapter we present a brief review of the fundamental theory of plasmonics.

Starting with the simple, single-interface metal-dielectric structure, we describe the basics

of surface plasmon including the dispersion, spatial profile, and commonly used optical

excitation schemes. Furthermore, we give a brief introduction to some of the popular

plasmonics waveguides including the long-range surface plasmonic waveguide (LRSPP),

the plasmonic dielectric loaded waveguide (DLSPW), the plasmonic slot waveguide, and

the hybrid plasmonic waveguide (HPWG). Finally, we discuss the some of the

applications based on the structure of the HPWG.

2.1 Surface Plasmon Polaritons

Surface plasmon polaritons (SPP) are electromagnetic excitations propagating along the

metal-dielectric interface, with its evanescent field decayed in the perpendicular direction

[4]. The simplest structure that can support a SPP is a single flat interface between a

dielectric non-absorbing material and a metal, as illustrated in Fig.2.1 (a). The electric

field decay in both half spaces as illustrated in Fig.2.1 (b).

We begin our analysis by examining the physical properties of SPP. For simplicity, we

assume there is no spatial variation in the in-plane y direction. The permittivity varies

only on the z direction and the plane z=0 is the interface of the two materials. Waves

propagate in the x direction along the interface.

6

Fig.2.1. (a) Single metal-dielectric interface and field profile of SPP mode. (b) Schematic illustration of the

electric field decay in both dielectric and metal layers.

We assume the variation of the dielectric permittivity of material on both sides of the

interface is negligible, and the time harmonic wave can be written as ( , ) ( ) i tE r t E r e ω−= .

The propagating wave can be described as ( , ) ( ) i xE x z E z e β= , where kxβ = is the

propagation constant of the traveling wave.

By expanding the two Maxwell source-free curl equations, for time dependent field, we

get the following set of equations

0yz

x

EE i Hy z

ωμ∂∂

− =∂ ∂

(2.1a)

0x z

yE E i Hz x

ωμ∂ ∂− =

∂ ∂ (2.1b)

0y x

z

E E i Hx y

ωμ∂ ∂

− =∂ ∂

(2.1c)

0yz

r x

HH i Ey z

ωε ε∂∂

− = −∂ ∂

(2.1d)

0x z

r yH H i Ez x

ωε ε∂ ∂− = −

∂ ∂ (2.1e)

0y x

r z

H H i Ex y

ωε ε∂ ∂

− = −∂ ∂

(2.1f)

Because we assume the propagation is along the x direction ( ix

β∂=

∂) and the structure is

x

z

|Ez|

z

xMetal

Dielectric

(a) (b)

7

homogenous in the y direction ( 0y

∂=

∂), the equations (2.1a-f) can be simplified. For the

transverse magnetic (TM) mode, only field components Ex, Ez and Hy are not zero. The

electric field can be expressed as the function of the magnetic field in such a case.

0

1 yx

r

HE i

zωε ε∂

= −∂

(2.2)

0z y

r

E Hβωε ε

= − (2.3)

For the surface mode propagate along the x direction and with field decay in the z

direction, we can write the magnetic field profile as zk zi xyH Ae eβ ±= . For a surface mode,

the real part of kz is positive. The electromagnetic field of a surface mode for the upper

space (z>0) can be written as

11( 0) zk zi x

yH z Ae eβ −> = (2.4)

11 1

0

1( 0) zk zi xx z

r

E z iA k e eβ

ωε ε−> = (2.5)

11

0

( 0) zk zi xz

r

E z A e eββωε ε

−> = − (2.6)

The electromagnetic field of a surface mode for the lower space (z<0) can be written as

22( 0) zk zi x

yH z A e eβ< = (2.7)

22 2

0

1( 0) zk zi xx z

r

E z iA k e eβ

ωε ε< = − (2.8)

22

0

( 0) zk zi xz

r

E z A e eββωε ε

< = − (2.9)

According to the boundary condition, the continuity of Hy at the interface (z=0) requires

A1=A2, while the continuity of Ex at the interface requires

8

1 1

2 2

r z

r z

kk

εε

= − (2.10)

Thus one condition for the SPP is that the permittivity of the two materials must have

opposite signs. This is the case when one material is dielectric and the second material is

metal.

The wave number has the following relations

2 2 21 0 1r zk kε β= − + (2.11)

2 2 22 0 2r zk kε β= − + (2.12)

From equations (2.10-2.12), we can get the expression for the propagation constant along

the x direction with the permittivity of the two materials as

21

210 εε

εεβ+

= k (2.13)

A similar derivation can be carried out for the case of transverse electric (TE) mode. For

the TE mode, only field components Hx, Hz and Ey are nonzero. The magnetic fields can

be expressed as the function of the electric field.

0

1 yx

EH i

zωμ∂

=∂

(2.14)

0z yH Eβ

ωμ= (2.15)

Now we briefly analyze the possibility of the TE surface mode. For the TE surface wave,

the electromagnetic field for the upper space (z>0) can be written as

11( 0) zk zi x

yE z Ae eβ −> = (2.16)

11 1

0

1( 0) zk zi xx zH z iA k e eβ

ωμ−> = − (2.17)

9

11

0

( 0) zk zi xzH z A e eββ

ωμ−> = (2.18)

The electromagnetic field for the lower half space (z<0) can be written as

22( 0) zk zi x

yE z A e eβ< = (2.19)

22 2

0

1( 0) zk zi xx zH z iA k e eβ

ωμ< = (2.20)

22

0

( 0) zk zi xzH z A e eββ

ωμ< = (2.21)

According to the boundary condition, the continuity of Ey and Hx at the interface (z=0)

requires

1 2 0k k+ = (2.22)

From this expression there is a contradiction with the surface mode requirement Re[k1] >

0 and Re[k2] > 0; thus no surface mode exist for the TE mode. We can conclude that only

the TM mode is supported.

Next we can examine the dispersion relation of SPP. According to the Drude model for

the free-electron gas, the permittivity of the metal is expressed as

2

2 21 p

iω

εω γω

= −+

(2.23)

where ωp is the plasma frequency of the metal and ω is the angular frequency of light. γ =

1/τ is the damping factor. τ is the relaxation time of the free electron gas, which is

typically on the order of 10-14 s at room temperature. In the optical regime, including the

visible and infrared range, ω < ωp, metals retain their metallic character [4]. For large

frequencies close to ωp, damping is negligible; thus the permittivity of metal can be

10

expressed as

2

2

2 1ωω

ε p−= (2.24)

According to equation 2.13 and 2.24, we can get the dispersion relation of surface wave

as

2

1 2

20

1 2

(1 )

1

p

pk

ωεβ ω

ωε

ω

−=

+ −

(2.25)

Based on this dispersion relation, we can normalize the frequency ω to the plasma

frequency ωp and the normalized SPP propagation wave number β/k0. The dispersion

relation is plotted in Fig. 2.2. In the lower frequency range, the SPP wave number is close

to the light line. Accordingly, the surface wave extends deep into the dielectric material.

For large frequencies, the wave number becomes extremely large and tends to infinity as

the resonance frequency is approached. This indicates the propagation speed slows down.

At the same time, the mode is bounded close to the metal-dielectric surface as the

frequency approach the resonance frequency. The characteristic surface plasmon

resonace frequency ωspp is given by

11p

spp

ωω

ε=

+ (2.26)

From the dispersion relations in Fig 2.2, we notice the surface plasmon mode always has

a larger wave number than the light line (ω = cβ), which means the SPP mode has a

greater momentum than a free photon of the same frequency, especially when the

11

frequency approaches the surface plasmon resonance frequency. Therefore the SPP

cannot be excited by directly shining light on the metal surface. As a result a phase-

matching mechanism is required. Prism coupling and grating coupling are the common

methods to increase the momentum of the incident waves. SPP waves can also be excited

using electrical techniques [4], though we will not consider this further in this thesis.

Fig.2.2. Dispersion relation of SPP at the interface between a Drude metal with negligible damping and a

dielectric material.

A prism made of a dielectric with a larger permittivity than air can be used to increase the

momentum of light. When a light beam is reflected at the interface between prism and air,

the evanescent waves created have an in-plane momentum sinx rk k ε θ= , where θ is the

incident angle form the prism to air and is set to be above the critical angle. This in-plane

momentum is larger than the momentum in air and can excite SPP at the air-metal

interface. Two commonly used prism excitation structures are those proposed by A. Otto

[16] and E. Kretschmann [17]. In the Otto configuration shown in Fig.2.3 (a) the prism is

separated from the metal surface by a thin air gap. Total internal reflection excites the

SPP via tunneling to the air-metal interface. This configuration is preferable for studies of

surface quality where direct contact with the metal surface is undesirable. In the

Kretschmann configuration shown in Fig.2.3 (b), a thin metal film is directly deposited

ω/ωp

β/k0

ω=cβ

1

11 ε+

12

on the prism surface. The total internal reflection takes place at the metal-prism interface

and the evanescent waves tunnel through the metal film and excite the SPP at the metal-

air interface. This is an easier mechanism for practical use.

(a)

(b)

Fig.2.3. Prism coupling to SPP in the (a) Otto and (b) Kretschmann configuration.

The mismatch in the momentum between the incident light and the SPP mode can also be

compensated by using a grating coupler. The metal surface can be patterned with periodic

structure [18], as shown in Fig. 2.4. If the light is incident at an angle θ, the evanescent

waves will have wave vectors

2sink n πβ θ= ±Λ

(2.27)

here Λ is the grating period and n can be any integer number. By choosing the grating

period properly, the grating can be used to excite the SPP.

Fig.2.4. Phase-matching of light to SPP using a grating.

Prism

Metal

airSPP

Prism

air

MetalSPP

MetalSPPΛ

Light

Substrate

13

2.2 Plasmonic Waveguides

The surface plasmonic wave propagating along the metal-dielectric surface has a smaller

phase velocity, shorter wavelength, higher momentum, and higher impedance compared

to waves propagating in the dielectric material [3]. The reduction in the wavelength is

essential for realizing nano-scale integrated circuit, and SPP-based waveguides have

attracted much attention during the past decades. Unlike dielectric materials, metals have

a complex permittivity. The imaginary part of the permittivity induces power loss as the

wave propagats along the waveguide. In the optical frequency regime (visible and

infrared), noble metals like gold and silver have a relatively small imaginary part of

permittivity and are typically used in the structure of plasmonic waveguides. The

permittivity of a metal can be expressed as ″+′= 222 εεε i , and the corresponding

expression for the propagation constant is

' ''iβ β β= + (2.20)

The propagation distance of the SPP before the power has decayed to 1/e of its original

value can be obtained by

12 ''

Lβ

= (2.21)

Though plasmonic waveguides have a large propagation loss, the promise of sub-

diffraction mode confinement, along with various applications like biosensing where the

presence of a metal can be an advantage, have attracted much attention and have

stimulated the increasing interest in plasmonic waveguides.

14

Figures 2.5 (a)-(e) show some popular types of plasmonic waveguides, including the

long-range SPP (LRSPP) waveguide, the dielectric loaded surface plasmon waveguide

(DLSPW), the plasmonic slot waveguide, the hybrid plasmonic waveguides (HPWG), the

metal wedge waveguide, and the V-groove channel waveguide.

Fig.2.5. Structure of different types of plasmonic waveguide. (a) LRSPP waveguide. (b) DLSPW. (c)

plasmonic slot waveguide. (d) Metal wedge waveguide. (e) V-groove channel waveguide. (f) HPWG.

One way to reduce the propagation loss of the SPP is to adopt the structure of a thin metal

film between identical dielectric materials at both sides [19-21], as shown in Fig. 2.5 (a).

In the symmetric metal slab with lossless cladding structure, the two single interface SPP

modes couple and form supermodes, one of which is the symmetric mode. The loss of the

symmetric mode decreases as the thickness of the metal film becomes thinner. At the

same time, the confinement of the mode reduces. The mode size is commonly very large

and can be comparable to those in an optical fiber [20-21]. The mode is called the long-

range SPP (LRSPP) mode. LRSPP waveguide based devices can be implemented where

the mode confinement is not critical but the longer propagation is required.

SiO2

Ag

SiO2

Ag

SiO2Si

Ag

SiO2

Ag

SiO2

Ag

(a) (b) (c)

SiO2Si

Ag (f)(d) (e)

15

When a higher degree of confinement is required, some other types of plasmonic

waveguides with higher propagation loss need to be used. As we discussed in section 2.1,

one of the most attractive properties of the single interface plasmonic waveguide is that

its mode size becomes vanishingly small as the resonance frequency is approached.

However, in this thesis we focus on applications of SPP in the telecommunications band

around 1.55 µm. In this lower frequency range, the group velocity of the mode is close to

the speed of light and the evanescent field extends further into the dielectric from the

single metal-dielectric interface. Besides the simple single metal-dielectric interface

structure, many other structures based on SPP have been shown to offer good

confinement in the optical regime [8-11], even though these waveguides do not operate

near the surface plasmon frequency.

The DLSPW consists of a high index material on metal, with low index material as the

cladding [8], as shown in Fig. 2.5 (b). For a single interface SPP guiding, vertical

confinement is achieved by the surface mode and the lateral confinement is achieved by

shrinking the lateral dimension of silicon. In DLSPW, lateral confinement is achieved by

the index contrast of high index core and lower index cladding. This approach is similar

to conventional dielectric waveguides. The high index contrast therefore is important for

DLSPW, and a silicon core and a silica cladding are used in this structure [8].

The plasmonic slot waveguide consists of a slot in a metallic film deposited on a

substrate. The slot could be filled with air or other dielectric material, as shown in Fig.

16

2.5 (c). The dimension of the slot can be much smaller than the wavelength [9], and the

fundamental mode is highly confined in the slot.

Plasmonic waveguides can also have different shapes like wedge waveguide as shown in

Fig. 2.5 (d) and V-groove channel waveguide and as shown in Fig. 2.5 (e). Their

principle of operation is similar to the slot waveguide and can achieve a high degree of

mode confinement [3].

The HPWG has been proposed as a way of optimizing the degree of confinement while

minimizing the amount of optical loss [10-11]. The HPWG consists of a high index

dielectric material separated from a metal layer with a low index dielectric material, as

shown in Fig.2.5 (f). Such type of waveguides combines both dielectric and plasmonic

guiding schemes and the TM mode is mostly confined in the low index material region.

The HPWG also supports the conventional TE mode in the high index layer. The

moderate loss and polarization diversity make the HPWG attractive and many

applications have been suggested [6, 22-26].

2.3 Hybrid Plasmonic Waveguides Applications

The HPWG offers sub-wavelength confinement in the low index region, offers a better

compromise between confinement and loss compared to pure plasmonic waveguides, and

is compatible with SOI technology. In addition, the propagation of the TE and TM modes

can be independently controlled which opens up the possibility of implementing compact

17

devices for manipulating polarization. These promising features have motivated recent

advanced research in the HPWG for various applications. Many different kinds of HPWG

have been proposed [10-14] and various applications have been suggested. Here we give

a brief introduction to some applications including lasers [22], electro-optic modulators

[23], optical concentrator [24], and sensors [25].

The plasmonic laser consists of a high-gain material (CdS) as the high index material,

low index MgF2 cladding and silver, as shown in Fig.2.6 (a) [22]. In this experiment, the

high index CdS is a nanowire and the cross section has a round shape. The mode is

confined in the gap region between the nanowire and metal surface. This plasmonic laser

offers the possibility of extreme interaction between light and matter.

A HPWG has been designed as an electro-optic modulator based on its multi layer

structure as shown in Fig. 2.6 (b) [23]. n-type doped silicon is chosen for the high index

material to reduce its resistivity and improve the modulation speed. The silicon and silver

form a capacitor with a low index, polymer spacer layer. The polymer has a strong χ(2)

electro-optic nonlinear effect. An external voltage is applied to the capacitor and the

refractive index of the pole polymer changes accordingly. The polymer film is thin and

the electric field is concentrated in the polymer, making such a structure sensitive to the

change of external applied voltage.

Figure 2.6 (c) shows an ultra-compact hybrid dielectric-plamonic, electromagnetic energy

nano-concentrator using mode beating [24]. The basic structure is a small gold triangle on

18

top of a dielectric waveguide. Silicon nitride is used as the high index material and silica

is used as the buffer layer. The length of the taper is about 1 μm and tip radium is 15 nm.

The concentration factor achieved is greater than 10.

A compact sensor based on a HPWG on a SOI substrate is shown in Fig. 2.6 (d) [25]. The

ring resonator is composed of a gold-gap-silicon structure and has only 1 μm radius. The

optical energy is greatly enhanced in the gap, thus enhances its overlap with the cladding

sensing medium. The sensitivity is very high compared to dielectric resonator sensors.

(a)

(b)

(c)

(d)

Fig.2.6. Optical devices based on the HPWG. (a) Plasmonic laser. (b) Electro-optical modulator. (c) Light

concentrator. (d) Ring resonance biosensor. (Figures are taken from [22-25])

Our group has contributed much in the progress of research on HPWG. In addition to

proposing the idea of the HPWG [10], many HPWG based applications has been

proposed by our group including TE-pass polarizer [27], TM-pass polarizer [28], high

sensitive biosensor which supports both the TE and TM modes [6], a polarization

19

independent hybrid plasmonic coupler [29] and other devices. In this thesis, we have

designed and experimentally demonstrated a HPWG based TE-pass polarizer.

20

Chapter 3 Properties of Hybrid Plasmonic Waveguides and Confinement Comparison of Plasmonic Waveguides

In this chapter, we carefully analyzed the properties of the hybrid plasmonic waveguide

(HPWG), including the mode formation, mode transition, power confinement, and

propagation loss. We have also analyzed the plasmonic slot waveguide and the dielectric

loaded surface plasmon waveguide (DLSPW) in terms of confinement and loss and tried

to identify their relative advantages and limitations compared to the HPWG.

3.1 Numerical Analysis Methods

To use the plasmonic waveguides for practical applications, we need to clearly

understand their propagation characteristics. The waveguides analyzed in this thesis have

a complicated geometry. Solving the propagation problem using analytical method for

these waveguides is therefore difficult. Numerical methods have been used to analyze the

waveguides. In this chapter, two-dimensional finite difference method is used to mesh the

structure and analyze the cross section of the different types of plasmonic waveguides. In

the next chapter, we will propose the design of a TE-pass polarizer. Besides using the

two-dimensional finite difference method, we analyze the wave propagating through the

full device using the three-dimensional Finite-difference time-domain (FDTD) method.

The simulations were carried out by the commercial software Lumerical Mode Solutions

and Lumerical FDTD Solutions.

21

To ensure a high accuracy while avoiding excessive demand of computational resources,

we used a conformal meshing scheme. A non-uniform mesh with a 5 nm mesh size at the

metal-dielectric interface and relatively larger mesh elsewhere in the computational

volume were used. We focus on the propagation behavior of the modes at the range of

telecommunication wavelength around 1.55 µm.

Noble metals like gold and silver at optical frequency regime has relatively low loss, so

are commonly used in plasmonic waveguides. At the wavelength of 1.55 µm, the real part

of the permittivity for both gold and silver is large and negative while the imaginary part

is small. In this chapter, we use silver as the noble metal in our simulations. In this thesis,

the permittivities of noble metals (silver and gold) are taken from Johnson and Christy

[30], and the permittivities of other materials including silicon, silica and chromium are

taken from palik [31].

3.2 Properties of Hybrid Plamonic Waveguide

3.2.1 Introduction to HPWG structure

The HPWG combines the characters of both a dielectric waveguide and a plasmonic

waveguide and have attracted much interest due to its potential for practical applications.

As shown in Fig. 3.1, the HPWG consists of a metal plane separated from a high index medium

by a low index spacer [10-11]. Silicon is chosen as the high index medium and silica is

chosen as the low index spacer, so that the structure is fully compatible with silicon-on-

insulator (SOI) technology and is suitable for optical applications in the near infrared

22

range. Besides, the waveguide is compact, shows polarization diversity, and can provide a

better compromise between loss and confinement than pure plasmonic waveguides. We

will address these properties in later sections.

Fig.3.1. Schematic of the hybrid waveguide.

3.2.2 Hybrid mode in one dimensional structure

In order to fully understand the characteristics of the HPWG, we first study the one-

dimensional HPWG structure, shown in Fig. 3.2 (a). It consists of a silicon slab layer, a

silica spacer layer and a silver layer. The HPWG structure can be treated as combination

of a dielectric waveguide (a silicon slab in a silica cladding) and a plasmonic waveguide

(a waveguide with a silver-silica interface).

The electric field intensity profiles for the TM and TE modes of the silicon waveguide,

single interface plasmonic waveguide, and HPWG are shown in Figs. 3.2 (b) and (c). As

an example, we choose a silicon slab with a thickness of 220 nm, and a silica spacer with

a thickness of 100 nm. The silver layer is much thicker than the skin depth, so it is treated

as semi-infinite. As we mentioned earlier, the HPWG supports both the TM mode and the

TE mode. The hybrid mode is the TM mode and it is formed via the coupling of the

plasmonic mode and the dielectric mode. As illustrated in Fig. 3.2 (b), the TM mode of

Si

SiO2

Spacer

Metal

23

the conventional dielectric waveguide is guided along the high index silicon layer and the

TM mode of the plasmonic waveguide is guided along the interface of silver and extends

into the silica layer. For the HPWG, when a dielectric waveguide is brought close to a

dielectric-metal interface but separated by a thin layer of low index material, the

dielectric mode and the SPP mode will couple and form a hybrid mode. A significant

fraction of the electric field of the TM mode is confined in the low index spacer layer

between the high index and the metal layer, i.e., silica layer between silicon and silver in

this example. Fig. 3.2 (c) shows the TE mode of the three waveguides. The TE mode of

the conventional dielectric waveguide is also guided along the high index silicon layer.

Because the plasmonic waveguide does not support the TE mode, the TE mode in the

HPWG is similar to a conventional dielectric waveguide mode and confined in the high

index medium. Since the TE and TM modes in a HPWG are concentrated in two different

layers, their properties can be controlled in different manners by changing the waveguide

dimensions and material properties. This can be used to design polarization sensitive

components such as the TE-pass polarizer which be discussed in Chapter 4.

In order to show the mode distribution more clearly, the electric field intensity profiles

for both the TM and TE modes of structure described above are plotted in Fig. 3.3. This

plot clearly shows the different mode distribution of the TM mode (hybrid mode) and the

TE mode (conventional mode). The TM mode resides more in the lower index spacer

layer while the TE mode resides in the high index silicon layer.

24

Fig.3.2. Formation of the hybrid plasmonic mode. (a) The hybrid plasmonic waveguide combines the

structure of dielectric waveguide and plasmonic waveguide. (b) TM mode of three waveguides. (c) TE

mode of three waveguides

-0.4

-0.2

0.0

0.2

0.4

0.0 0.2 0.4 0.6 0.8 1.0

TM TE

Normalized field intensity

Slab

dim

ensi

on (μ

m)

Fig.3.3. Field intensity of the TM and TE mode for the HPWG with silicon slab thickness 220 nm, spacer

thickness 100 nm.

+ =SiSiO2

SiO2

SiO2

Ag Ag

SiSiO2

TM mode

SiO2

SiO2

SiSiO2

AgSiO2

Ag

Si

SiO2

Dielectric mode

1.0

0.00.20.40.60.8

Plasmonicmode

Hybrid mode

(a) Waveguide structure

(b) TM mode intensity profile

TE mode

SiO2

SiO2

SiSiO2

Ag

Si

SiO2

N/A

(c) TE mode intensity profile

25

3.2.3 Mode transition as a function of dielectric thickness

Since the hybrid mode is the result of coupling between the plasmonic mode and the

dielectric mode, it shows the both the feature of plasmonic and dielctric modes. By

changing the dimensions of each layer, the hybrid mode could be more plasmoinc like or

dielectric like. The metal has a high absorption and the penetration depth in the metal is

very small, so the mode mostly resides in the dielectric. On the other hand, dielectric

materials confine the mode with the scheme of index contrast, so the thickness of the

dielectric layers can change the field distribution. In this section, the effects of varying

silicon thickness are examined for a fixed spacer thickness.

For simplicity, we analyzed the one-dimensional HPWG structure with the materials and

dimension shown in Fig. 3.4 (a). The silicon slab thickness is d and the silica spacer

thickness is g. Figure 3.4 (b) shows the electric field intensity for d = 0, 100, 400 nm for

g = 100 nm. When d = 0, the structure corresponds to a plasmonic waveguide. As d

increases, the electric field becomes more confined to the region with the low dielectric

constant. For a moderate d (d = 100 nm), the power is highly confined in the spacer. For a

large d (d = 400 nm), the mode resides more in silicon slab and becomes a dielectric like

waveguide.

Figure 3.4 (b) clearly shows that the nature of the mode changes with varying silicon

thickness. The mode changes from a plasmonic mode to a hybrid mode and then to a

mode like in the dielectric waveguide with the increase of d. In the application of HPWG

26

waveguide, the mode distribution will affect the performance. We will evaluate the mode

distribution of HPWG of different dimensions.

(a)

-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.60.0

0.2

0.4

0.6

0.8

1.0 d = 0 nm d = 100 nm d = 400 nm

Nor

mal

ized

Ele

ctric

File

d In

tens

ity

x (μm) (b)

Fig.3.4. HPWG structure and field profiles. (a) One-dimensional HPWG structure. (b) Electric filed

intensity profile for varying silicon thickness (d). Spacer thickness is fixed at 100 nm.

The coupling of the plasmonic mode with the dielectric mode results in a hybrid mode

which resides mainly in the spacer layer. The percentage of power in the spacer layer can

be used as a criterion to evaluate the HPGW. For the power propagating in the waveguide

along the z direction, the confinement factor (Γ) is defined as the fraction of power

confined in the spacer layer and can be expressed as:

( , )

( , )

zi

z

S x y dxdy

S x y dxdyΓ ∞ ∞

−∞ −∞

< >=

< >

∫∫∫ ∫

(3.1)

Here, Sz is the time-averaged pointing vector along the z-direction.

Figure 3.5 (a) shows the power confinement factor (Γ) in the spacer layer (with thickness

of g) for the one dimensional structure for different values of g and d. When d = 0, there

is no silicon layer and the waveguide is a pure plasmonic waveguide and the power reside

in the 100 nm layer adjacent to the silver (where the spacer would be if a silicon layer

g d

xo

Si SiO

2

Ag

27

exists) is relatively low. The presence of the silicon layer pushes more power into the

spacer layer as d increases and goes to a maximum value. However, as silicon becomes

thicker and thicker, more power can be confined in the silicon layer and less power is in

the spacer. We can clearly see, there is a silicon thickness range for which the mode in

the HPWG is more concentrated in the low index spacer. The associated propagation loss

of the proposed HPWG has also been studied. As shown in Fig. 3.5 (b), the propagation

loss increases with the increasing of d and then decreases. Figures 3.5 (a) and (b) have a

similar trend, which shows the more power is squeezed into the spacer, the higher the

propagation loss. Comparing Fig. 3.5 (a) and (b), we find high Γ is associated with high

loss. There is a tradeoff between mode confinement and propagation loss of HPWG.

0 50 100 150 200 250 3000

10

20

30

40

50

60

70 g = 10 nm g = 20 nm g = 50 nm g = 100 nm

Pow

er C

onfin

emen

t Fac

tor (

%)

d (nm) (a)

0 50 100 150 200 250 3000.00

0.05

0.10

0.15

0.20

Prop

agat

ion

Loss

(dB

/μm

)

d (nm)

g = 10 nm g = 20 nm g = 50 nm g = 100 nm

(b)

Fig.3.5. Power confinement and loss for the HPWG. (a) Power confinement for different dielectric layer

thickness. (b) Propagation loss for different dielectric layer thickness.

3.3 Comparison of Sub-wavelength Confinement and Loss of Plasmonic Waveguides

In addition to the HPWG introduced in previous section, many different types of

plasmonic waveguides have been proposed [3]. With the ability to confine light to a

28

subwavelength scale, plasmonic waveguides can be used for nano scale integrated

circuits. Unlike dielectric waveguides for which the propagation loss can be negligible,

the presence of metal as part of the guiding structure makes plasmonic guides highly

lossy. In general, any plasmonic guide exhibits a tradeoff between propagation loss and

mode confinement – the smaller the mode size, the higher the propagation loss.

Plasmonic waveguides of different design have different characteristics and the variation

between loss and confinement is also different among them. Criteria for evaluating these

types of plamonic waveguides should be based on the particular application. A

combination of low propagation loss, high power density, and large confinement will be

useful for many applications of plasmonic waveguides including nonlinear optics [5] and

biosensing [6-7]. In order to evaluate the confinement level for different types of

plamonic waveguides, we have proposed the criterion of the normalized average power

density per unit area (D). The propagation loss and D have been studied and compared.

Since the SPP mode is TM in nature, we only analyze the TM mode in this section.

3.3.1 Analyzed waveguide structures

In real applications, the waveguides have both lateral and vertical confinement. The

waveguides compared in this section have two-dimensional cross sections. Though there

are many types of plasmonic waveguides, it is impractical to compare all of them. In this

chapter some typical types have been analyzed. It is possible to apply our approach to

other plasmonic structures. Some of the most popular plasmonic guides proposed for

nanophotonic applications are the dielectric loaded surface plasmon waveguide (DLSPW)

[8], the plasmonic slot waveguide [9], and the hybrid plasmonic waveguide (HPWG) [10,

29

11]. The geometries of these guides are shown in Fig. 3.6 (a-c). In order to achieve a low

propagation loss, silver is used for the metal part of the plasmonic waveguides in this

chapter. We intend to compare the relative performance of these guides and also compare

their performance with the silicon nanowire waveguide shown in Fig. 3.6 (d).

Unlike a typical dielectric waveguide whose guided mode has a circular or elliptical

shape, the shapes of the modes supported by plasmonic guides are usually more

complicated. As a result, evaluation of mode confinement for plasmonic guides is a

challenging task. This issue has been discussed in [32, 33] and it was asserted that the

definition of mode area should depend on the specific application. A common way of

expressing a waveguide’s ability to confine light is to calculate its mode size, and various

definitions of mode size have been used by the plasmonics research community.

Although the mode size can be a good indication of a guide’s ability to confine light, it is

not sufficient in many cases. Many applications of plamsonics like nonlinear optics [5]

and biosensing [6] aim at utilizing the high power density of plasmonic guides. For such

applications, in addition to having a small mode size, it is also important to confine the

power in a specific area of the wave guiding region. For example, a typical application of

the DLSPW could require power to be confined in the high index core marked by the

dotted line in Fig. 3.6 (a). An application of the slot waveguide on the other hand will

most likely require the power to be concentrated in the slot region indicated by the dotted

line in Fig. 3.6 (b). Typical applications of the HPWG may require high power

concentration in the region between the silicon and metal indicated by the dotted line in

Fig. 3.6 (c). It is unlikely one would intend to use the HPWG for confining light in the

30

high index medium which can be achieved in much simpler manner as shown in Figs. 3.6

(a) and 3.6 (d).

Fig.3.6. Analyzed waveguide structures. (a) Dielectric loaded surface plasmon waveguide. (b) Plasmonic

slot waveguide. (c) Hybrid plasmonic waveguide. (d) Silicon waveguide.

3.3.2 Method of comparision

This work is aimed at comparing different types of plasmonic guides. Instead of defining

mode size as in [32] or figure of merit as in [33], we use the following two criteria: the

power confinement (Γ ) in the area of interest and the power density (D) in the area of

interest. The power confinement factor Γ in region i [area of interest marked by the dotted

lines in Figs. 3.6 (a) to 1(d)] is defined according to equation (3.1). However, the

confinement factor alone is not enough to evaluate the usefulness of a waveguide. In

addition to having a large Γ it may also be important to have high power density in the

area of interest. To evaluate this we define the average power density per unit area (D) in

the following manner

total

i

PD

AΓ ⋅

= (3.2)

Here, Ai is the area enclosed by the dotted lines in Figs. 3.6 (a)-(d) and Ptotal is the total

guided power, which is normalized to 1 mw in the present case. In the following we

dw SiO2

Si

Ag

(a)

dg

SiO2

Ag

(b)

dw

gSiO2

Ag

Si

(c)

ddSi

SiO2

(d)

31

investigate which of the plasmonic guides can provide large values of Γ and D for the

same propagation loss.

3.3.3 Confinement achievable in case of a dielectric waveguide

Before the study of plasmonic waveguides, the confinement ability of a dielectric

waveguide should be evaluated first to set a reference. The imaginary part of the

permittivity of silicon is negligible at 1.55 μm and silicon has a high index contrast with

silica; thus silicon waveguide could be a good reference to evaluate the confinement

ability of a dielectric waveguide with the proposed criteria.

We analyze a silicon dielectric waveguide with a core of square cross section with side

length d in silica cladding, as shown in Fig.3.7 (a). The guided power is mostly confined

in the silicon core, as shown in Fig.3.7 (b).

(a)

(b)

Fig.3.7. (a) Structure of the silicon waveguide. (b) Guided power distribution in the silicon waveguide.

The power confinement factor (Γ) in the square core is shown in Fig. 3.8 (a). As the

dimension of silicon core increases, more power resides in the core. At the same time, the

average power density in the core initially increases, reaches a maximum value, then

decreases as the silicon core becomes larger, as shown in Fig. 3.8 (b). Though a silicon

ddSi

SiO2

32

dielectric waveguide can confine up to 80% of the power in the high index region, the

cross section of the silicon waveguide is large. In such a case, the power density is low.

The highest value of D is about 7.8 mw/μm2 which is achieved for d = 300 nm and the

corresponding Г is 70%.

250 300 35030

40

50

60

70

80

90

Γ (%

)

d (nm)(a)

250 300 3505

6

7

8

D (m

w/μ

m2 )

d (nm)(b)

Fig.3.8. (a) Confinement factor and (b) power density of the silicon dielectric waveguide

3.3.4 Properties of DLSPW

The DLSPW consists of a high index material on metal, with low index material as

cladding. As shown in Fig. 3.9 (a), the silicon core sits on top of the silver with silica

cladding. The power resides in the high index core and close to silver surface, as shown

in Fig.3.9 (b).

(a)

(b)

Fig.3.9. (a) Structure of the DLSPW structure. (b) Guided power distribution in the DLSPW.

dw SiO2

Si

Ag

33

The power confinement factor (Г) is shown in Fig. 3.10 (a). The width (w) is fixed at

discrete values in the range of 150 - 300 nm and the height of the silicon layer (d) is

varied from 150 nm to 300 nm. The power density (D) is shown in Fig. 3.10 (b). The

corresponding D for the DLSPW is 24 mw/μm2 at the maximum. With the help of metal,

more power is confined in a smaller region, i.e. in a w = 200 nm by d = 150 nm with

about 80% power confined. For equal value of Γ, the DLSPW is more compact, and the

average power density in the core is higher than a silicon dielectric waveguide.

100 150 200 250 3000

20

40

60

80

100

w = 150 nm w = 200 nm w = 250 nm w = 300 nm

Γ (%

)

d (nm)(a)

100 150 200 250 30010

15

20

25

D (m

w/μ

m2 )

w = 150 nm w = 200 nm w = 250 nm w = 300 nm

d (nm)(b)

100 150 200 250 3000.10

0.15

0.20

0.25

0.30

0.35

0.40 w = 150 nm w = 200 nm w = 250 nm w = 300 nm

Prop

agat

ion

Loss

(dB

/μm

)

d (nm)(c)

0.15 0.20 0.25 0.30 0.355

10

15

20

25

w = 150 nm w = 200 nm w = 250 nm w = 300 nm

D (m

w/μ

m2 )

Propagation Loss (dB/μm)

d (150-300 nm)

(d)

Fig.3.10. Confinement factor and power density associated with loss for the DLSPW. (a) Confinement

factor. (b) Power density. (c) Propagation loss. (d) Power density vs. propagation loss

34

Though in terms of power confinement, the DLSPW is better than a silicon waveguide,

this better confinement is achieved at the cost of a higher propagation loss. The

associated loss for DLSPW is plotted in Fig. 3.10 (c) for different silicon widths and

heights. The relation between propagation loss and power density is plotted in Fig. 3.10

(d) for silicon heights (d) in the range of 150 - 300 nm, as shown by the arrow. As shown

in Fig. 3.10 (a) and (b), when the dimension goes below w = 150 nm , d = 150 nm, Г and

D dramatically goes down because most of the power leaks out to the cladding.

3.3.5 Properties of plasmonic slot waveguide

The plasmonic slot waveguide consists of two metal walls and a dielectric gap. Since the

field cannot penetrate into the metal, the mode is highly confined in the gap between two

metal walls. In reality, the metal wall cannot be infinitely high, so some power will leak

out of the gap into the surrounding dielectric. The structure of a typical plasmonic slot

waveguide is shown in Fig. 3.11 (a). We have analyzed the plasmonic slot waveguide

with different silver heights d of 50 nm, 100 nm and 150 nm. The slot width (g) is varied

from 30 to 100 nm. The power is highly confined in the slot as shown in Fig. 3.11 (b).

(a)

(b)

Fig.3.11. (a) Structure of the plasmonic slot waveguide. (b) Guided power distribution in the plasmonic slot

waveguide.

dg

SiO2

Ag

35

As shown is Fig.3.12 (a), the confinement factor increases with thicker metal layers. For

the same gap g = 50 nm, the confinement factor (Г) reaches 60% with d = 150 nm, while

the confinement factor is 30% for d = 50 nm. Considering the fact that the area of the

regions is different, we compare power density (D) in the gap. From Fig.3.12 (b), D is

higher for d = 50 than d = 100 or d = 150 nm, because light has been squeezed into a

smaller region. This guide can provide very high D which can be approximately 200 mw

/μm2. Fig. 3.12 (c) shows the associated power loss. Fig. 3.12 (d) shows the relation of D

with associated loss for different metal height. With fixed metal height, the higher D, the

higher the propagation loss. As g decreases, D in the plasmonic slot and its associated

propagation loss can continuously increase.

30 60 90 120 15010

20

30

40

50

60

70 d = 50 nm d = 100 nm d = 150 nm

Γ (%

)

g (nm)(a)

30 60 90 120 1500

50

100

150

200

250

d = 50 nm d = 100 nm d = 150 nm

D (m

w/μ

m2 )

g (nm)(b)

30 60 90 120 1500.10

0.15

0.20

0.25

0.30

0.35

d = 50 nm d = 100 nm d = 150 nm

Prop

agat

ion

Loss

(dB

/μm

)

g (nm)(c)

0.10 0.15 0.20 0.25 0.30 0.350

50

100

150

200

250 (30-150nm) d = 50 nm d = 100 nm d = 150 nm

g

D (m

w/μ

m2 )

Propagation Loss (dB/μm)(d)

Fig.3.12. Confinement factor and power density associated with loss for the plasmonic slot waveguide. (a)

Confinement factor. (b) Power density. (c) Propagation loss. (d) Power density vs. propagation loss

36

3.3.6 Properties of HPWG

The structure of the HPWG is shown in Fig. 3.13 (a). For the HPWG, the TM mode is

coupled between the surface plasmonic mode and dielectric mode resulting a high power

density in the gap (g), as shown in Fig. 3.13 (b). The properties of the resulting

waveguide mode are affected not only by the dimension of the gap itself, but also by the

thickness and width of the silicon. For consistency we fixed w = 200 nm, and change the

value of silicon thickness d for different gap (we plot the confinement relation with w in

the Appendix A, w = 200 nm is optimized to achieve a good confinement).

(a)

(b)

Fig.3.13. (a) Structure of the HPWG. (b) Guided power distribution in the HPWG.

When d is small, most of the guided power will leak out to the upper cladding layer, thus

less power resides in the gap (g), as shown in Fig. 3.14 (a). With the increase of d, power

is more confined in the gap, and reaches the highest value when d = 150 nm to 200 nm.

Further increase of d causes the electric field to reside into silicon and the HPWG then

works like a dielectric waveguide, which results in the decrease of confinement factor (Г)

in the gap. Increasing g from 10 nm to 50 nm also increases the confinement factor (Г)

because light spreads over a larger area; however, the HPWG with a very large gap

looses the confinement ability and Г goes down again after it reaches maximum value

dw

g

SiO2

Ag

Si

37

(the Г of g = 100 nm is smaller than the Г of g = 50 nm). Though the HPWG with a small

g (for example, g = 10 nm) does not have high Г, it has the highest power density (D) and

highest propagation loss, as shown in Fig. 3.14 (b) and (c). If d is fixed, changing g

results in different propagation loss. The relation of power density vs. propagation loss

for hybrid mode (d = 150 nm to d = 250 nm) is shown in Fig. 3.14 (d)

100 150 200 250 300 3505

10

15

20

25

30 g = 10 nm g = 20 nm g = 50 nm g = 100 nm

Γ (%

)

d (nm)(a)

100 150 200 250 300 3500

20

40

60

80

100

120

D (m

w/μ

m2 )

g = 10 nm g = 20 nm g = 50 nm g = 100 nm

d (nm)(b)

100 150 200 250 300 3500.00

0.05

0.10

0.15 g = 10 nm g = 20 nm g = 50 nm g = 100 nm

Prop

agat

ion

Loss

(dB

/μm

)

d (nm)(c)

0.04 0.08 0.12 0.160

30

60

90

120

d = 150 nm d = 200 nm d = 250 nm

D (m

w/μ

m2 )

Propagation Loss (dB/μm)

(10-100nm)g

(d) Fig.3.14. Confinement factor and Power Density associated with Loss for the HPWG with w= 200 nm. (a)

Confinement factor. (b) Power density. (c) Propagation loss. (d) Power density vs. propagation loss

38

3.3.7 Comparison of various plasmonic waveguides

We have analyzed the confinement properties of three types of plasmonic waveguides.

The properties of each waveguides are determined by the dimensions. However, the

results show the confinement range that a waveguide can achieve. For conciseness we

report one case for each waveguide.

0.0 0.1 0.2 0.30

50

100

150

200

w= 200 nm

w=d= 200 nm

d(150-300 nm)

g(10-100 nm)

Slot DLSPW HPWG

D (m

w/μ

m2 )

Propagation Loss (dB/μm)

g(30-150 nm)d=100 nm

DLSPW

Plasmonit Slot

HPWG

Fig.3.15. Normalized power density vs. propagation loss for three types of plasmonic waveguides.

Figure 3.15 shows the power density (D) achievable for the plasmonic waveguides. The

arrows in Figs. 3.15 and 3.16 indicate increasing dimensions (d or g). For the DLSPW the

width (w) is fixed at 200 nm and the height of the silicon layer (d) is varied from 150 nm

to 300 nm. The corresponding D for the DLSPW varies from 13 mw/μm2 to 24 mw/μm2.

For the slot waveguide, the metal thickness (d) is fixed at 100 nm and the slot width (g) is

varied from 30 to 150 nm. This guide can provide the highest power density which can be

approximately 200 mw/μm2. For the HPWG, both the width (w) and silicon thickness (d)

dw SiO2

Si

Ag

(a)

dg

SiO2

Ag

(b)

dw

gSiO2

Ag

Si

(c)

39

have been fixed at 200 nm and the gap (g) is varied from 10 to 100 nm. The power density

achievable for the HPWG is higher than the DLSPW but lower compared to the slot

waveguide. However, for a given power density the propagation loss of the HPWG is

much lower compared to the other types of plasmonic guides.

0.0 0.1 0.2 0.30

20

40

60

80

100

w=d= 200nm

d= 100nm

w= 200nmd(150-300nm)

g(10-100nm)

g(30-150nm)

Γ (%

)

Propagation Loss (dB/μm)

Slot DLSPW HPWG

DLSPW

Plasmonit Slot

HPWG

Fig.3.16. Confinement factor vs. propagation loss for three types of plasmonic waveguides.

Figure 3.16 shows the confinement factor (Г) achievable for the plasmonic waveguides.

The dimensions chosen are same as those in Fig. 3.15. The value of Г is largest for the

DLSPW (85%) and comparable to that achievable from silicon nanowire waveguide. The

confinement is relatively low for the HPWG compared to the other guides but its

propagation loss is also much lower.

dw SiO2

Si

Ag

(a)

dg

SiO2

Ag

(b)

dw

gSiO2

Ag

Si

(c)

40

From the analysis above we observe that the performance of the DLSPW is very similar to

the silicon waveguide, but it suffers from a very high propagation loss. Therefore,

DLSPW may not be a best choice for applications where high power density is required,

nonlinear optics for example. The slot waveguide can achieve very high power density

and good confinement but the propagation loss is also very high. HPWG is a compromise

in the sense that it has significantly lower loss but still can provide high power density and

moderate confinement. The choice between HPWG and slot waveguides should depend on

the relative importance of power density and power confinement for a specific application.

3.4 Conclusion In this chapter, we have analyzed the properties of the HPWG and compared the

confinement and propagation loss of the HPWG with the plasmonic slot waveguide and

the DLSPW. The HPWG combines both dielectric and plasmonic guiding schemes, and it

provides good confinement with moderate propagation loss. The HPWG supports both the

TE and TM modes. In the next chapter, we will present the design of a TE-pass polarizer

that utilizing the polarization diversity of the HPWG for its operation.

41

Chapter 4 Design and Optimization of the Hybrid Plasmoinc Waveguide as a TE-pass Polarizer

Various applications can be realized based on the HPWG with the property of its polarization

diversity as mentioned in the previous chapter. Our objective is to experimentally demonstrate the

polarization diversity property of HPWG. In this chapter, we design a compact TE-pass polarizer

based on the HPWG. The designed polarizer has a high extinction ratio and low insertion loss.

We have not only considered the compactness and performance of the poloarizer itself, but also

considered the fabrication simplicity and smooth coupling from input/output waveguides.

4.1 Background

Control of the polarization state of light is essential for many integrated optical applications [34].

This is especially true for high index contrast waveguides such as those implemented on the SOI

platform. The high index of silicon makes SOI waveguides highly polarization dependent. Thus,

TE and TM modes behave differently and the absence of polarization control may disrupt the

proper operation of the integrated chip. One common approach to solve this problem is to use a

polarizer to extinguish the unwanted polarization state. A number of different types of SOI

compatible TE-pass polarizer have been proposed in the past including metal clad waveguides

[35, 36], shallowly etched waveguides [37], gap plasmon waveguides [38], and silicon nanowire

polarization splitter [39]. These devices are either very sensitive to fabrication imperfection, or

very long. Some have significant insertion loss for the TE mode, or low extinction ratio. In order

to implement complex optical circuits with many integrated components and to increase the

42

integration density, an experimental demonstration of a compact, broadband, and SOI compatible

TE-pass polarizer with better solution for polarization control would be useful.

4.2 TE-pass Polarizer Design Overview

A compact, broadband TE-pass polarizer can be implemented based on the structure of the

HPWG [27]. Such a structure can provide high extinction ratio and low insertion loss for the TE

mode. In addition to the theoretical considerations, we have also considered the

fabrication simplicity and the smooth propagation of the TE mode in the whole device.

Figure 4.1 (a) shows a schematic of the TE-pass polarizer. It consists of a HPWG section (Fig.

1(b)) between two silicon waveguides (Fig. 1(c)).

Fig.4.1. (a) Three dimensional schematic of the HPWG TE-pass polarizer with input and output silicon

waveguides. (b) Cross section of the HPWG. (c) Cross section of the input/output silicon waveguide. The

final dimensions are H = 220 nm, T = 3 μm, w = 500 nm, w′ = 250 nm, h = 200 nm, t =100 nm.

Though the desired TE mode in HPWG is similar to a conventional TE mode and has a

much lower propagation loss, it is still affected by the existence of metal and the

propagation length in the HPWG is short compared to in a conventional dielectric

waveguide. Since the proposed HPWG is compatible with SOI technology, in our

approach the silicon waveguide is used for the input/output sections and the HPWG section

(b)

wHT

w'

ht

(a) (c)

HT

w hSiliconSilicaChromium

43

is used to extinguish the TM mode. The designed device can achieve a high extinction ratio with

a very short HPWG section. Moreover, partial etching of the silicon layer has been

eliminated to reduce the roughness on the silicon top surface and to improve the coupling

efficiency between different sections. In particular, a smooth transition between different

sections for the desired TE mode is achieved as discussed later.

4.2.1 Input/output waveguides

We chose to implement the TE-pass polarizer on a SOI substrate consisting of a 220 nm

thick silicon device layer on a 3 μm buried oxide layer. The low loss input and output silicon

waveguides are used to guide light over large distances into and out of the HPWG section. A

single mode input/output silicon waveguide can be designed with the 220 nm silicon

device layer and at the same time a single mode hybrid waveguide can be implemented

with such a dimension; thus it simplifies the fabrication process and improves the

coupling efficiency between sections. To be consistent with the dimension of the SOI

wafer, the thickness of the input/output silicon waveguides is 220 nm. The width of the

input/output waveguides is 500 nm, so that light is guided in single mode. To be

consistent with the HPWG section fabrication, which will be described in chapter 5, the

input/output waveguides is covered by a 200 nm silica cladding. The two fundamental

modes have been calculated using Lumerical Mode Solutions. Figures 4.2 (a) and (b)

illustrate the electric field intensity profiles of the two fundamental modes for the input

/output waveguides. Here the field intensity is defined as the square of the field magnitude. The

cross section of the input /output waveguide shown in Fig. 4.1 is shown in Fig. 4.2 (c) again

for reference.

44

Fig.4.2. Electric field intensity profiles at 1.55 μm for the (a) TE and (b) TM modes of the input/output

waveguides for H = 220 nm, T = 3 μm, w = 500 nm, h = 200 nm. The definition of the variables is shown in

(c).

Later in our characterization setup, the light from a single mode fiber will be coupled into

the waveguide via free space lens. The mode size from the fiber is much larger than the

mode size in the silicon nano waveguide. Although adiabatic taper has been used to couple

the TE mode from a wider waveguide to a nanowire [40], this approach is not chosen here. The

reason has been discussed in [41, 42]. The TM fundermental mode in the adiabatic taper

will convert to high order TE modes and scatter during propagation. Because both the TE

and the TM mode are characterized in our experiment, the light is directly coupled into

the silicon nano waveguide and there is no taper structure for the input/output

waveguides.

4.2.2 Functional HPWG section

The functional HPWG section consists of a silicon high index core covered by a layer of

silica, which is the same as the input/output waveguides. An extra chromium cap is

deposited on the silica layer to absorb the TM mode.

0.2

0.4

0.6

0.8

1.0

0.2

0.4

0.6

-0.2

0.0

0.0

-0.2 0.2-0.4 0.4

0.0

x (μm)

y (μ

m)

(a)0.2

0.4

0.6

0.8

1.0

0.2

0.4

0.6

-0.2

0.0

0.0

-0.2 0.2-0.4 0.4

0.0

x (μm)

y (μ

m)

(b) (c)

HT

w h

45

The electric field intensity profiles for TE and TM modes for the HPWG, obtained by using

commercial finite difference code Lumerical MODE Solutions, are shown in Fig. 4.3 (a) and (b)

respectively. The cross section of the HPWG section in Fig. 4.1 is shown in Fig. 4.3 (c) again

for reference. The optimization process will be described in next section. The electric field

distributions are different for the two modes. The electric field of the TE mode in a HPWG is

concentrated in the high index region i.e., silicon core which is far from the metal layer. The

electric field of the TM mode on the other hand is a hybrid mode and the electric field is

concentrated in the silica between the metal and silicon. Since the TM mode is adjacent to the

metal, the propagation loss for the TM mode in the HPWG is always larger than that for the TE

mode. If the metal is highly lossy, the TM mode will be attenuated quickly while the TE

mode can be well guided with a lower loss. Based on this principle a TE-pass polarizer can be

implemented using HPWG by properly choosing the device dimensions and materials.

Fig.4.3. Electric field intensity profiles of the (a)TE and (b) TM modes of the HPWG section for H = 220

nm, T = 3 μm, w = 500 nm, w′ = 250 nm, h = 200 nm, t =100 nm. Wavelength of operation is 1.55μm. The

definition of the variables is shown in (c).

0.2

0.4

0.6

0.8

1.0

0.2

0.4

0.6

-0.2

0.0

0.0

-0.2 0.2-0.4 0.40.0

x (μm)

y (μ

m)

(a)0.1

0.2

0.3

0.4

0.5

0.00.0-0.2 0.2-0.4 0.4

x (μm)

0.2

0.4

0.6

-0.2

0.0

y (μ

m)

(b) (c)

wHT

w'

ht

46

4.3 Device Optimization Process

The losses of TM and TE modes are highly dependent on the dimensions of the various

layers. As mentioned before, by properly adjusting the dimensions, it is possible to make

the propagation loss of the TM mode much higher than that of the TE mode. A good

polarizer should have low insertion loss for the desired mode and the high loss for the

unwanted mode. At the same time, we consider the fabrication simplicity and feasibility.

That is, the device should have a high extinction ratio, the design should not be difficult

to implement, and the performance should not be very sensitive to small variations of

dimensions. To achieve these goals and at the same time keep the device size small, we

have done a detailed parametric study.

We will fabricate the polarizer on a SOI wafer with 3 μm thick silica box layer and 220

nm thick silicon device layer. The width of the silicon waveguide is chosen to be 500 nm

to ensure the single-mode guiding requirements. The dimensions for the silicon nano

waveguide, which are illustrated in Fig. 4.1, are H = 220 nm, T = 3 μm, w = 500 nm.

The dimensions of the silicon layer in the HPWG are kept exactly same as the

input/output waveguide to simplify the fabrication process and guarantee a smooth

coupling between sections. We have analyzed the performance of the HPWG by varying

the dimensions w′, h and t. Here we reported the simulation results at 1.55 μm obtained

by using Lumerical Mode Solutions.

47

4.3.1 Chromium cap dimension

Figures 4.4 (a) and (b) show the propagation loss of the TE mode and the TM mode with

different widths of metal (w′) while all other dimensions were kept constant. The

propagation loss of the TE mode decreases as the w′ decreases. The propagation loss of

the TM mode first increases then decreases as the w′ decreases and the loss is high for w′

= 100 - 500 nm. The loss does not change much for the TM mode in this range. Although

the width of the chromium cap (w′) can be designed to be the same as the width of the

silicon core (w), in practice this will increase the fabrication difficulties due to possible

misalignment between the various layers. If the chromium cap falls down from the upper

layer to the side wall, the device operation will be seriously affected. Structure with a

narrower w′ structure can tolerate more misalignment; however, a shallow trench is more

difficult for metal lift-off. We finally choose w′ = 250 nm for our device because for this

dimension the device is easy to fabricate and shows good performance. Also for such a

dimension the propagation loss for the TM mode is high and for the TE mode is low.

100 200 300 400 5000.00

0.02

0.04

0.06

0.08

0.10

0.12

w' (nm)

Prop

agat

ion

Loss

of H

PWG

(dB

/μm

)

TE

(a)

100 200 300 400 5001.10

1.12

1.14

1.16

1.18

Prop

agat

ion

Loss

of H

PWG

(dB

/μm

)

w' (nm)

TM

(b)

Fig.4.4. Propagation loss with different chromium cap width (w′) for H = 220 nm, T = 3 μm, w = 500 nm,

h = 200 nm, t =100 nm. Wavelength of operation is 1.55μm. For the definition of the variables, see Fig. 4.1.

(a) TE mode. (b) TM mode

48

Figures 4.5 (a) and (b) show the propagation loss of the TE mode and the TM mode with

different metal thickness t with other dimensions same as in Fig. 4.1. The propagation

loss for both modes at first increases with increment of t but then decreases as t increases

further. At the beginning when t is very small the chromium is not thick enough to absorb

the electric field. For intermediate value of t, the propagation loss goes to maximum

because the absorption takes place at both interfaces and corners of the chromium cap.

Further increase in t results in less absorption from the top interface of the chromium cap

and the propagation loss tends to be a constant for a large t. Though the extinction ratio is

maxium when t is around 30 nm, we do not choose such a dimension because the

performance in such a range is quite sensitive to device dimension and any deviation

from design value strongly affects the device operation. We choose t >= 100 nm to make

the device less sensitive to fabrication imperfections.

0 50 100 150 2000.04

0.05

0.06

0.07

0.08 (a)

Prop

agat

ion

Loss

of H

PWG

(dB

/μm

)

t (nm)

TE

0 50 100 150 2001.0

1.2

1.4

1.6

1.8

2.0 (b)

t (nm)Prop

agat

ion

Loss

of H

PWG

(dB

/μm

)

TM

Fig.4.5. Propagation loss with different chromium cap thickness (t) for H = 220 nm, T = 3 μm, w = 500 nm,

w′ = 250 nm, h = 200 nm. (a) TE mode. (b) TM mode.

4.3.2 Silica spacer dimension

Figures 4.6 (a) and (b) show the propagation loss of the TE mode and the TM mode with

different spacer thickness (h). The propagation loss of both modes decreases as h

49

increases because both modes are less concentrated at the interface of the chromium cap.

Accordingly, the required HPWG length (L) for a certain extinction ratio varies. In order

to illustrate this more clearly, the length of the HPWG required (L) to achieve 30 dB

extinction ratio is calculated and plotted in Fig. 4.6 (c). The loss for the TE mode at the

same length (L) is plotted in Fig. 4.6 (d). As h increases, L becomes larger with less loss

for the TE mode, while a smaller h results a smaller L but a higher loss for the TE mode.

We choose h = 200 nm for our final design for the polarizer.

150 200 2500.00

0.05

0.10

0.15

0.20

h (nm)

Prop

agat

ion

Loss

of H

PWG

(dB

/μm

)

TE

(a)

150 200 2500.5

1.0

1.5

2.0 (b)

Prop

agat

ion

Loss

of H

PWG

(dB

/μm

)

h (nm)

TM

150 200 25010

15

20

25

30

35

40

45

h (nm)

HPW

G le

ngth

for 3

0 dB

Ex

(μm

) (c)

150 200 2500

1

2

3

4

h (nm)

Prop

agat

ion

Loss

for T

E m

ode

(dB

)

(d)

Fig.4.6. Propagation loss for the (a) TE mode and (b) TM mode. (c) HPWG length for 30 dB extinction

ratio. (d) Propagation loss of the TE mode for length calculated in (c). The plots are with different spacer

thickness (h) with other dimensions fixed of H = 220 nm, T = 3 μm, w = 500 nm, w′ = 250 nm, and t = 100

nm.

50

The final dimensions for the full device illustrated in Fig. 4.1 are H = 220 nm, T = 3 μm,

w = 500 nm, w′ = 250 nm, h = 200 nm, t = 100 nm. For this set of dimensions we expect

an extinction ratio of 30 dB and insertion loss of 2 dB for the TE mode for a 30 μm long

HPWG section. These dimensions ensure: single mode guiding, high coupling efficiency

between different sections, and high extinction ratio. Also the design is tolerant to

possible variations of the device dimensions.

4.4 Coupling Efficiency between Sections

In the design of our device, we made an effort to minimize the coupling losses between

the silicon input/output waveguides and the HPWG section. When light couples from one

waveguide to another, coupling losses can be caused by two general mechanisms: (a)

difference in the field profiles and, (b) mismatch of effective mode indices. Here, we will

discuss the two effects separately. Because the dimensions of the HPWG are exactly the

same as the input/output waveguides (except for a metal cap), the coupling losses

between different sections are low. For the TE mode we have ensured that the mode

shape, position, and refractive index match well between sections, thus the reflection and

scattering losses between different sections have been suppressed. From the electric field

profiles of the TE mode in silicon waveguides and HPWG in Fig. 4.2 (a) and Fig. 4.3 (a),

we notice the field distribution is almost the same. The calculated effective indices and

coupling efficiency at 1.55 μm wavelength are listed in Table 4.1. The effective indices

in these sections of the TE mode are very close. The coupling efficiency of the TE mode

between sections is more than 99%, which ensures a smooth transition for the TE mode.

51

On the other hand, for the TM mode – because of the influence of the chromium – there

is some shape and effective index mismatch, as we see from Fig. 4.2 (b) and Fig. 4.3 (b).

In the case of silicon nano waveguides, 48% of the total guided power is confined in the

silicon core and the rest resides in the cladding layer and the substrate. For the HPWG

section, 42% of the guided power is in the silicon core. This proves the mode shape and

location are different in the two sections. As a result, the effective mode indices of the

TM mode supported by the silicon nano waveguides and the HPWG are not the same but

also close (1.74 and 1.82, respectively). The coupling efficiency between the sections is

approximately 88% at each interface, and some power is reflected and scattered. Though

the coupling of the TM mode is not as efficient as the TE mode, it is still good.

Table 4.1 Effective indices and coupling efficiency for the TE and TM modes at 1.55 μm

Mode neff of input/output waveguides

neff of HPWG section

Coupling efficiency at each interface

TE mode 2.443 2.440 > 99% TM mode 1.735 1.821 88%

4.5 Full Device Simulation

The loss values presented in the previous section are obtained from Lumerical Mode

Solution. These values include only absorption and radiation losses for ideal waveguides.

In the following, parameters like wavelength dependency, insertion loss and extinction

ratio for the whole polarizer are analyzed using 3 dimensional FDTD solutions.

Figure 4.7 (black line) shows the device insertion losses (including coupling and

propagation losses) obtained from the full wave FDTD simulation for a 30 μm long

52

HPWG TE-pass polarizer inserted between two silicon nano waveguides. It shows a high

extinction ratio (of at least 20 dB) and a low insertion loss for the TE mode over a

bandwidth of 150 nm.

During fabrication precise control of the width of the silicon nano waveguide is not an

easy task because of the undercut which takes place during the etching process. We have

investigated the performance of the polarizer for w = 500 nm ± 50 nm and have plotted

the results in Figs. 4.7 (a) and (b). The ripples present in the TM mode insertion loss

spectrum are because of the reflection and the scattering due to the mode mismatch

between different sections.

1.50 1.55 1.60 1.6520

25

30

35

40

45 w = 450 nm w = 500 nm w = 550 nm

Wavelength (μm)Inse

rtion

Los

s for

TM

mod

e (d

B) (a)

1.50 1.55 1.60 1.651

2

3

4

5

Wavelength (μm)Inse

rtion

Los

s for

TE

mod

e (d

B)

w = 450 nm w = 500 nm w = 550 nm

(b)

Fig.4.7. Insertion loss of a 30 μm long TE-pass polarizer predicted by FDTD simulation. Device

dimensions are as mentioned in the caption of Fig. 1. (a) Variation of insertion loss for the TM mode. (b)

Variation of insertion loss for the TE mode with silicon width (w).

From Figs. 4.7 (a) and (b), we notice smaller value of silicon width (w) results in higher

losses while larger w results in lower losses for both modes. The reason is explained in

the following. A significant part of the device insertion loss is due to the presence of the

metal in the HPWG section and the intensity of the optical field in the vicinity of metal.

53

Figures 4.8 (a) and (b) show the optical power in the chromium layer and regions up to

10 nm from the chromium-dielectric interface. These figures imply that the optical power

– within the chromium layer and regions up to 10 nm away – increases as the width of the

silicon width (w) decreases. Consequently, the losses due to the metal also increase as the

silicon width (w) decreases.

450 500 5500.060

0.065

0.070

0.075

0.080

TE

Pow

er p

erce

ntag

e fo

r the

TE

mod

e (%

)

w (nm)

(a)

450 500 5501.6

1.7

1.8

1.9

2.0

2.1 (b)

TM

w (nm)Pow

er p

erce

ntag

e fo

r the

TM

mod

e (%

)

Fig.4.8. Power in the chromium layer and adjacent regions for the (a) TE mode and (b) TM mode with

variation of silicon width (w).

Now we analyze the effect of variation of the spacer thickness (h) on device performance.

The thickness control of the silica deposition with PECVD is more precise, therefore we

have investigated the performance of the device for h = 200 nm ± 5 nm and plotted the

results in Fig. 4.9 (a) and (b). Thinner h results in higher loss and thicker h results in

lower loss for both modes. The ripples present in the TM mode insertion loss spectrum

are due to the reflections between different sections. These results indicate that the

proposed device can provide a large insertion loss for the TM mode while maintaining a

low insertion loss for the TE mode over a range of dimensions.

54

1.50 1.55 1.60 1.6520

25

30

35 h = 195 nm h = 200 nm h = 205 nm

Wavelength (μm)Inse

rtion

Los

s for

TM

mod

e (d

B)

1.50 1.55 1.60 1.651

2

3

4

Inse

rtion

Los

s for

TE

mod

e (d

B)

Wavelength (μm)

h = 195 nm h = 200 nm h = 205 nm

Fig.4.9. Insertion loss of a 30 μm long TE-pass polarizer predicted by FDTD simulation. Device

dimensions are as mentioned in the caption of Fig. 1. (a) Variation of insertion loss for the TM mode. (b)

Variation of insertion loss for the TE mode with spacer thickness (h).

4.6 Conclusion In this chapter we have presented a detailed design of the TE-pass polarizer. We have

investigated the effects of different parameters on the device performance and chosen the

optimized dimensions. The final designed device is compact, broadband, has high

extinction ratio, and has a low loss for the TE mode. In the following chapter we will

present the details of fabrication process used for implementing the device.

55

Chaper 5 Device Fabrication

We present the fabrication process required for the implementation of the HPWG based

TE-pass polarizer in this chapter. Fabrication of the proposed device includes a number

of steps including electron beam lithography (EBL), reactive ion etching (RIE), dielectric

deposition using plasma enhanced chemical vapor deposition (PECVD), and metal

deposition using thermal evaporator followed by lift-off process. Those process steps are

described in this chapter.

5.1 Fabrication Process Overview

The proposed polarizer is a multilayer structure, and precise alignment between these

layers is necessary for proper operation of the device. Electron beam lithography (EBL)

meets this requirement and is chosen as the lithography method. EBL is a direct-write

method and does not need a prefabricated mask. The positive electron beam resist ZEP

520A is chosen for the process. It provides a high resolution, high sensitivity and is

durable during the etching process which will be used to define silicon waveguides.

The fabrication process steps are summarized in Fig. 5.1. The fabrication began with a

SOI wafer (Fig. 5.1 (a)). Using a combination of EBL, metal deposition and lift-off, gold

markers were fabricated (Figs. 5.1 (b)-(d)). In the next step, the positive electron beam

resist ZEP 520A was spin-coated on the substrate and patterned using electron beam

lithography (Fig. 5.1 (e)). This was followed by reactive ion etching (RIE) to define the

56

silicon nano waveguides (Fig. 5.1 (f)). A 200 nm thick silica layer was then deposited

over the sample using plasma enhanced chemical vapor deposition (PECVD) (Fig. 5.1

(g)). Electron beam lithography was used again to define the HPWG section (Fig. 5.1 (h)).

The sample was then covered with chromium using a thermal evaporation process

followed by a lift-off process to complete the fabrication (Fig. 5.1 (i)). All these process

steps are SOI compatible and were carried out in ECTI nanofabrication cleanroom at the

University of Toronto. The details of these fabrication process steps are described in the

in the following sections.

Fig.5.1. Fabrication process flow of the HPWG TE-pass polarizer. (a) SOI substrate. (b) Resist spin-coating

and EBL for gold markers. (c) Gold deposition. (d) Gold lift-off. (e) Resist spin-coating and EBL for

silicon nano waveguide (markers are not shown in this and following steps because they are far from

waveguides). (f) RIE etching and resist removal. (g) Silica deposition by PECVD. (h) Resist spin-coating

and EBL. (f) Chromium deposition and lift-off.

(a)

Silicon

Silica

Gold

ZEP 520A

(b) (c)

(d) (e)

(g)

(f)

(i)(h)

Chromium

57

5.3 Device Layout and Pattern Design with L-Edit

The device layout and dimensions of a HPWG TE-pass polarizer and the input/output

silicon waveguides were described in chapter 4. Though the length of the HPWG section

(L) was optimized at 30 μm in chapter 4, considering the possible deviations, we

fabricated polarizers with HPWG sections of lengths 20μm, 30μm and 40μm.

The device patterns were created with Tanner EDA Software Tools–L-Edit Layout. The

designed device is shown in Fig. 5.2 (a). The layout of the device is shown in Fig. 5.2 (b).

The area with patterns (shown in color) will be exposed; the blank area will remain

unexposed. Because positive resist is used, resist on the exposed area will be dissolved in

the developer.

(a) top view of the TE-pass polarizer

(b) EBL layout for the TE-pass polarizer

Fig.5.2. Design and Layout pattern of the polarizer. (a) Designed device. (b) Layout for one polarizer.

The L-Edit Layout of the device is shown in Fig. 5.3. Several layers were defined for

different fabrication steps or for different pattern fracture resolutions. Layer 1 was used to

w'w

L

w'w

L

58

define maker array (blue in Fig. 5.3 (a)). Layer 2 (red in Fig. 5.3) and layer 3 (green in

Fig. 5.3) were used to define the straight silicon nano waveguides. The exposed area was

to be etched and the unexposed area was defined as waveguides. In order to decrease the

EBL writing time, the background was defined in layer 2 (red) and fractured with a lower

resolution (25 nm). In order to guarantee the high resolution of the nano waveguides, the

exposure area near the waveguides was defined in layer 3 (green) and fractured with high

resolution (10 nm). The center-to-center distance of the waveguides is 14 μm to ensure no

coupling between waveguides. Layer 4 (purple in Fig. 5.3) was used to define the

exposure area for chromium lift-off and thus defined the length of the HPWG section.

(a) (b)

Fig.5.3. L-Edit Layout pattern of the polarizer. (a) Overview of the pattern; (b) close view of the polarizers

in one block.

5.4 Electron Beam Lithography and Dose Test

Different layers of the patterns were written and aligned with Vistec EBPG 5000+. The

positive resist ZEP 520A was used for all lithography processes. The resist was spin-

coated on the whole sample and a part was removed after exposure and development. The

59

unexposed part remained on the substrate. ZEP 520A has a good resolution thus is good

for defining nano scale patterns. Compared to another popular positive resist PMMA,

ZEP 520A is more sensitive in EBL and more durable during the etching process. The

EBL tool in ECTI works at 100 kV HT voltage with variable currents. In order to get a

clear pattern, an optimized electron beam dose (amount of electrons per area, unit: μC/cm2)

needs to be used. To achieve this optimized dose, a number of test patterns were written

with different doses, developed and inspected under a scanning electron microscope

(SEM). For the proposed device, we used ZEP 520A spin-coated at 6000 rpm for both the

etching and chromium lift-off process, and ZEP 520A resist spin-coated at 2000 rpm was

used for the gold lift-off process.

We ran dose tests for three conditions in EBL. These conditions are:

1. ZEP520A resist spin-coated at 6000 rpm with pattern fracture resolution of 10 nm.

2. ZEP520A resist spin-coated at 6000 rpm with pattern fracture resolution of 25 nm.

3. ZEP520A resist spin-coated at 2000 rpm with pattern fracture resolution of 10 nm.

The ZEP520A resist spin-coated at 6000 rpm results in a 340 nm thick uniform film. A

thinner resist layer is typically used for a small dimension because of the aspect ratio. For

the resist just beside the region of silicon waveguides and inside the region of the

chromium caps, we used a 10 nm resolution with a 5 nA electron beam current for

electron beam writing. For the dose equal to or lower than 220 μC/cm2, resist particles

scatter on the substrate surface after development, as shown in Fig.5.4. The SEM pictures

in Fig. 5.5 (ridge) and Fig. 5.6 (trench) show a clear pattern begins with dose equal or

60

greater than 240μC/cm2. We chose the dose of 240 μC/cm2, which produces a well

defined pattern for the etching process. Having a clean surface is critical for metal

deposition and lift-off; thus a higher dose equal to or greater than 280 μC/cm2 is used for

the pattern.

(a) 200 μC/cm2 (b) 220 μC/cm2

Fig.5.4. Low dose results in resist residues even for large areas. (Resist thickness is 340 nm, and fracture

resolution is 10 nm)

(a) 200 μC/cm2 (b) 220 μC/cm2 (c) 240 μC/cm2

(d) 260 μC/cm2 (e) 280 μC/cm2 (f) 300 μC/cm2

Fig.5.5. Dose test for the ridge drawn in L-edit as 700 nm wide. (Resist thickness is 340 nm, and fracture

resolution is 10 nm)

61

(a) 200 μC/cm2 (b) 220 μC/cm2 (c) 240 μC/cm2

(d) 260 μC/cm2 (e) 280 μC/cm2 (f) 300 μC/cm2

Fig.5.6. Dose test for trench drawn in L-edit as 100 nm wide. (Resist thickness is 340 nm, and fracture

resolution is 10 nm)

For the background area writing (shown as red in Fig. 5.3), we used a 25 nm resolution

with a 30 nA electron beam current. This lower fracture resolution and higher beam

current increase the direct writing speed. As shown in Fig. 5.7, a clear pattern begins with

a dose equal or greater than 240μC/cm2. We chose the dose of 240 μC/cm2 to write

patterns for etching of large area.

62

(a) 200 μC/cm2

(b) 220 μC/cm2 (c) 240 μC/cm2

(d) 260 μC/cm2 (e) 280 μC/cm2 (f) 300 μC/cm2

Fig.5.7. dose test for the ridge drawn in L-edit as 700 nm wide. (Resist thickness is 340 nm, and fracture

resolution is 25 nm)

The ZEP520A resist spin-coated at 2000 rpm results in a 500 nm uniform film. The lift-

off time for gold is much longer than for chromium and a thicker resist layer can make

the lift-off process easier. The gold markers have a large dimension (20 μm by 20μm);

thus the aspect ratio for markers is low. We used a 10 nm resolution with 5 nA electron

beam current. The SEM pictures in Fig. 5.8 show a clear pattern begins with dose equal

or greater than 240 μC/cm2. However, for gold deposition and lift-off, a clean substrate

without speckles over a large area is required. A dose equal or greater than 300 μC/cm2

was used.

63

(a) 220 μC/cm2

(b) 240 μC/cm2 (c) 300 μC/cm2

Fig.5.8. dose test for the ridge drawn in L-edit as 700 nm wide. (Resist thickness is 500 nm, and fracture

resolution is 10 nm)

5.5 Gold Markers

The purpose of the gold markers is to define the coordinate system during the EBL

process which helps in achieving good alignment of different layers. Gold has a high

atomic weight and shows a high contrast to silicon under electron beam illumination, thus

it is a suitable material for alignment markers. An array of gold markers was deposited on

the SOI sample. Each maker is a 20 by 20 µm gold square. The height of the marker is

about 50 nm to achieve sufficient contrast to the substrate under electron beam

illumination.

For our sample, the maker pattern was defined by the EBL. Thermal evaporation was

used for the deposition of the gold layer. Because gold does not have a good adhesion to

the silicon surface, a 5 nm thick chromium layer was used as the adhesion layer. The

detailed deposition steps are illustrated in Fig. 5.9. The SOI substrate (Fig. 5.9 (a)) was

first spin-coated by ZEP 520A with 2000 rpm for 1 min (Fig. 5.9 (b)). Then the pattern

for the marker definition was written using EBL and developed in ZED-N50 (the

64

developer for ZEP 520A), as shown in Fig. 5.9 (c). A 5 nm thick layer of chromium used

as the adhesion layer was deposited by thermal evaporation (Fig. 5.9 (d). Then a 50 nm

thick gold layer was deposited by thermal evaporation in the same run (Fig. 5.9 (e)). The

metals were evaporated at the rate under 1 Å/s to ensure a uniform deposition and to

reduce the grain size. After the metal films were deposited, the samples were immersed in

ZDMAC to remove the resist. In order to thoroughly clean the resist after deposition

without damaging the marker, the sample was put in ZDMAC for 2 days in room

temperature. Then the beaker was manually agitated and put in an ultrasound bath until

the gold layer peeled off and only the markers were left (Fig. 5.9 (f)). Top view of the

marker array is shown in Fig. 5.9 (g).

Fig.5.9. Fabrication steps for alignment makers. (a) SOI wafer. (b) Spin coat ZEP resist. (c) Define maker

shape and dimensions by E-beam writing. (d) Chromium deposition by thermal evaporation. (e) Gold

deposition by thermal evaporation. (f) Lift-off process. (g) Top view of SOI wafer with gold markers.

Now we describe how the markers work during the alignment job. The substrate is

manually loaded on the EBL sample holder with a coarse alignment under a microscope.

The sample can be slightly rotated and the marker-to-marker distance may be slightly

different. These errors are corrected by the EBL tool. In a general alignment job, four

(a) (c)

(e) (f)

(d)(b)

Silicon Silica

Chromium

ZEP 520AGold(g)

65

markers are used. The coordinate system during the EBL is decided by these four

markers. The EBL tool–Vistec EBPG 5000+ automatically explores the location of the

four markers and calculates their centers. The electron beam searches for the marker

edges and calculates their center positions. Figure 5.10 (a) shows the microscope picture

of a gold marker covered by ZEP 520A. The gold square is clear and intact. Fig. 5.10 (b)

shows the picture of a gold marker after exposure during the alignment job and

development. The dots at the edges and on the marker are the result of the electron beam

scanning. For the first marker, the electron beam has a larger scanning area and exposes

more area around the marker, as shown in Fig. 5.10 (c). The quality of the exposed

markers will degrade in the later steps like etching. However the unexposed gold markers

are protected by the resist. Using a different set of makers is recommended for good

alignment. Fig. 5.10 (d) shows the unexposed gold markers after RIE etching and silica

deposition. They are clear, and can be used for future alignment.

Two possible issues affecting the precision of the alignment job can be seen here.

Different sets of markers in the array are not identical especially there are some

roughness at the edges. This may result in possible differences in defining the coordinate

systems and contribute slightly to misalignment in later steps. In the thermal evaporator,

the two metal sources (chromium and gold) are put in two different crucibles and these

crucibles are fixed at different positions in the chamber, so there is an angle difference of

the two metal sources to the sample. This difference causes imperfect marker edges

which may slightly contribute to the misalignment.

66

(a) (b)

(c) (d)

Fig.5.10 (a) Gold marker covered by ZEP. (b-c) Gold marker after ebeam writing and development. (d)

Gold marker covered by silica

5.6 Silicon Nano Waveguide Etching

The Phantom etcher is used for RIE etching of the silicon waveguides. The Phantom

etcher can supply SF6, CHF3, CF4, O2 and inert gases. Using a high RIE RF power during

RIE etching generates more heat which will make the ZEP 520A resist very hard and

insoluble in resist remover. To dissipate the heat, thermal oil can be coated on the back

side of the sample, but possible residue of the oil after cleaning can contaminate the

sample. A moderate RIE RF power (80 Watt) is chosen in our fabrication. A standard

clean recipe is run first, and then the recipe optimized for etching by us is used to etch the

silicon waveguide. The recipe optimized recipe is listed in Table 5.1.

67

Table 5.1: RIE etching recipe for silicon waveguides

Etching chamber condition Parameter RIE RF power 80 Watt

Chamber pressure 80 mTor

Gases flow in the chamber 25 sccm SF6 and 12 sccm O2

Backside cooling gas flow 10 sccm He

Total etching time 65 seconds

The steps in the silicon etching process are illustrated in Fig. 5.11. The substrate was

spin-coated by ZEP 520A at 6000 rpm for 1 min (Fig. 5.11 (a)). The EBL was used to

define the silicon nano waveguides as shown in Fig. 5.11 (b). RIE was used to etch the

nano silicon waveguides as shown in Fig. 5.11 (c). After etching, we put the sample in

ZDMAC for 10 minutes and heated it to 50 °C. Later the beaker was put in an ultrasound

bath for about 1 minute. The heating and ultrasound was used to thoroughly remove the

resist since a very clean surface was required for later steps, as shown Fig. 5.11 (d).

Figure 5.11 (e) shows the top vieWs of the silicon waveguides with markers.

Fig.5.11. Fabrication steps for silicon waveguides. (a) Spin coat ZEP resist. (b) Define silicon waveguide

pattern by E-beam writing. (c) RIE etch the uncovered silicon. (d) Resist removal. (e) Top view of silicon

waveguides with markers.

(b)(a)

Silicon Silica

ZEP 520A

Gold

(c)

(d) (e)

68

The typical etching profile under SEM is shown in Fig. 5.12. The etched waveguides has

slanted sidewalls which are different from design. We have several recipes but were not

able to achieve a vertical wall for the silicon nano waveguides. Fortunately, this shape

change does not significantly affect the porlarizer performance. This will be discussed in

more detail in chapter 6.

Fig.5.12. Silicon nano waveguides etched by RIE has slanted sidewalls.

5.7 Silica Deposition

A 200 nm thick silica layer was deposited by PECVD. In this step, the silica layer

covered the whole sample, including the input/output waveguides.

The deposition system PlasmaLab System 100 PECVD (Oxford Instruments) supplies

silane (SiH4) and nitrous oxide (N2O) for silica deposition. They interact in the chamber

to form silica. The plasma process reaction is [43]

4 2 2 3 23 6 3 4 4SiH N O SiO NH N+ → + + (5.1)

69

According to [43], silanol (Si-OH) incorporation happens at substrate temperatures of

250-290 C and N-H bond formation occurs at substrate temperatures of 350-390 C. To

ensure the purity of silica, the deposition temperature is chosen at 300 C.

Before silica deposition, we opened the chamber and cleaned it with vacuum and IPA.

The physical cleaning process was carried out at a temperature of less than 50 °C. Later

after the deposition temperature and low pressure are reached, we run a plasma clean

recipe on the empty chamber at 300 C.

The PECVD deposition recipe is taken from the user database from ECTI and the steps

are summarized in Table 5.2.

Table 5.2: PECVD silica deposition recipe at 300 C

Steps Chamber condition Time 1 Pump down 2 minutes

2 Preheat Pressure: 1500 mTorr

Gas flow: N2 1000 sccm

3 minutes

3 Plasma clean RF power: 100 watts

Gas flow: N2 1000 sccm

Gas flow: N2 1000 sccm

1 minute

4 Silica deposition RF power: 45 Watt,

Pressure: 400 mTorr,

Gas flow: 30 sccm 5% SiH4/N2, 700 sccm N2O.

26 minutes

5 Pump down 1 minute

The deposition rate for this recipe is about 8 nm/min. After deposition the samples were

checked under SEM. The silica thickness measured under SEM is 205 nm as shown in

Fig. 5.13 (a). The sample has a low surface roughness as shown in Fig. 5.13 (b).

70

(a) (b)

Fig.5.13. SEM picture of the 205 nm silica layer deposited over the whole sample by PECVD. (a) Silicon

waveguide under silica cladding. (b) Close view of the surface of the deposited silica.

5.8 Chromium Deposition and Lift-off

To define the HPWG section, a chromium layer was deposited using thermal evaporation

and the lift-off process was performed. ZEP 520A was spin-coated on the top of the silica

layer as shown in Fig. 5.14 (a). The EBL was used to define a 250 nm wide region as

shown in Fig. 5.14 (b). Thermal evaporation was used to deposit a layer of chromium as

shown in Fig. 5.14 (c). A chromium cap sit on the top of the silica ridge after the lift-off

process as shown in Fig. 5.14 (d). In this step, different lengths (20 μm, 30 μm and 40 μm)

of HPWG sections for the polarizers were defined as shown in Fig. 5.14 (e).

71

Fig.5.14. Fabrication steps for hybrid section metal lift-off. (a) Spin coat ZEP resist. (b) Define metal

pattern by E-beam writing. (c) Deposit chromium by thermal evaporation. (d) Lift-off ZEP resist. (e) Top

view of the final device.

The deposition quality was checked under the SEM and Fig. 5.15 shows the surface of

the chromium cap. The top surface is very rough. Fortunately, a smooth chromium top is

not required in our design.

Fig.5.15. SEM picture of the rough surface of deposited chromium

(a) (b) (c)

(d) (e)

Silicon Silica

Chromium

ZEP 520AGold

72

5.9 Final Device

An optical microscope image of the final device is shown in Fig. 5.16. A number of TE-

pass polarizers of various lengths (20, 30 and 40 μm) were fabricated on the same chip.

In addition, a number of reference channels were also fabricated. The reference channels

are identical to the TE-pass polarizer branches with the exception that they have no

HPWG sections.

Fig.5.16. Fabricated device with silicon reference nano waveguides and TE polarizers of different HPWG

lengths.

The sample was cleaved to a length of 4 mm for optical characterization. A SEM image of the

end facet of the input/output silicon nano waveguide is shown in Fig.5.17 (a). Figures 5.17 (b - d)

show the SEM images of the end facet and the top view of the HPWG section. The dimensions

of the silicon core and the silica cladding layer of the HPWG section are the same as the

input/output nano waveguides. A chromium cap is present only on the HPWG section. The

chromium cap is 250 nm wide and 150 nm thick. It is located almost at the middle of the HPWG

section with a small offset from the center (25 nm), which confirms the good alignment achieved

in our fabrication. The RIE etching process produced a trapezoidal shape for the silicon nano

Polarizer

Silicon nano waveguide

73

waveguide with the width of the trapezoid varying from 580 nm at the bottom to 420 nm at the

top. From the simulation results presented later, we shall see that this deviation from the original

design does not significantly affect the device performance.

(a) (b)

(c) (d) Fig.5.17. SEM images of (a) the cross section of the input/output/reference silicon nano waveguides, (b) the

cross section of HPWG section, (c) top view of the HPWG section, and (d) a closer top view of the HPWG

section.

As mentioned earlier, there may be slight misalignment between different layers due to

the fabrication process. We fabricated a second sample which shows a misalignment of

70 nm for the top layer as illustrated in Fig. 5.18. As we already considered the possible

misalignment and designed a narrow chromium cap (250 nm), the chromium cap still sits

74

on the top of the ridge, thus the performance of the final device is not significantly

affected.

(a) (b) Fig.5.18. A sample with around 70 nm misalignment. SEM images of (a) the cross section of the HPWG

section and (b) top view of the HPWG section.

5.10 Conclusion

In this chapter we have described the fabrication steps and presented the images of the

sample. The fabrication is compatible with standard SOI technology. The misalignment

between layers is within an acceptable range. Multiple polarizers and reference

waveguides are fabricated on the sample. In the next chapter we will report the results

from optical characterization of the device.

75

Chapter 6 Optical Characterization

In the previous two chapters we presented the details of the design of a compact HPWG TE-pass

polarizer and outlined the fabrication process. In this chapter we present results on the

characterization of the device. We measured the optical power transmission through the TE-pass

polarizer and compared the value with the power transmission through the reference silicon

waveguides for the TE and the TM modes. The device shows a high extinction ratio over a broad

band for a 30 μm long HPWG section. The results match well with simulations and confirm the

polarization diversity of HPWG.

6.1 Experimental Setup and Measurement Method

The experimental setup used for optical characterization of the HPWG TE-pass polarizer

is shown in Fig. 6.1. We used an end-fire scheme to test the fabricated device. Power

from a continuous wave tunable InGaAsP laser was coupled to free space from a single

mode fiber using a fiber-to-free-space coupler. The polarization of the incident light was

controlled using a combination of half wave plate and polarizing beam cube (PBS). The

sample was mounted on a rig and two 40× microscope objectives were used to couple the

light into and out of the sample. An infrared camera was used at the output to ensure that

light was coupled properly into only one waveguide at a time. The power output from the

waveguide was detected with a Germanium photodiode detector. Another Germanium

photodiode detector was used to detect the reflected power of the incident light from the

76

beam splitter just before the stage. The devices were characterized over a wavelength

range of 1.52 to 1.58 μm.

Fig.6.1. Experiment setup to measure the power transmission through waveguides.

There are various loss mechanisms that contribute to the total power loss between the two

detection points. There are losses from the light coupling in and out of the waveguides,

propagation along the silicon waveguides, coupling between silicon waveguides to the

HPWG section, and propagation along the HPWG section. The typical Fabry-Perot (FP)

loss measurement method is not suitable for this case, because the waveguides are lossy

and formed multiple cavities (two silicon waveguides and the HPWG section). The

insertion loss of the HPWG polarizer can be determined by comparing the transmission

of the waveguides with the HPWG section to that of the reference waveguides. We

fabricated several silicon nano waveguides with and without the HPWG section on the

same sample. The coupling loss from free space is similar for all waveguides because the

facet due to one cleaving is similar for all waveguides on the same sample (though we

haven’t characterized the coupling loss from free space for each waveguides). These

silicon waveguides were fabricated under the same condition, thus the propagation losses

77

from each silicon waveguide are comparable. When the power output of the TE-pass

polarizer waveguide was compared to that of the reference waveguide, the output

difference came from the loss form propagation through the HPWG section and coupling

between the silicon input/output nano waveguides and the HPWG section. Thus the

device insertion loss was measured. We compared the power outputs from a reference

waveguide and a polarizer with a 30 μm long HPWG section. The results are described in

the following.

6.2 Optical Characterization Results

The output mode profiles of both modes of the waveguides were captured with an

infrared camera. Figures 6.2 (a) and (b) show the images of the TE mode output from the

reference waveguide and the polarizer with a 30 μm HPWG section separately. The shape

and brightness of the image for the polarizer is comparable to those of the image for the reference

waveguide. Figures 6.2 (c) and (d) show the images of the TM mode output from the

reference waveguide and the polarizer separately. It is clear that the output from the HPWG is

much less than that from the reference waveguide for the TM polarized light.

(a) T

(c) T

Fig.6.2

waveg

The m

over

from

The e

mode

wave

polar

TE mode outpsilic

TM mode profsilic

2. Camera ima

guide and from

measured ins

a wavelengt

25 dB to 3

extinction ra

e. The exti

elength range

rizers and r

put profile frocon waveguid

file output frocon waveguid

ages of mode o

m the polarizer w

sertion losse

th range of

1 dB and th

atio is the di

inction ratio

e, as shown

reference w

m the referende

om the referende

output profile f

with a 30 μm H

es for both T

1.52 to 1.58

he insertion l

fference of t

o varies fro

n in Fig. 6.4

aveguides;

nce (b) TE

nce (d) TM

for TE and TM

HPWG section

TE and TM m

8 μm. The in

loss for the

the insertion

om 23dB t

. We have c

the perform

E mode outpu

M mode outpu

M mode at 1.55

.

modes are sh

nsertion loss

TE mode va

n losses for t

to 28dB (e

compared se

mance is sli

ut profile from

ut profile from

μm from the r

hown in Fig.

s for the TM

aries from 2

the TE mode

experimental

everal fabric

ightly differ

7

m the polarizer

m the polarize

reference silico

6.3 (marker

M mode varie

2 dB to 3 dB

e and the TM

l) in such

cated TE-pas

rent betwee

78

r

er

on

rs)

es

B.

M

a

ss

en

79

different devices. The error bars in the plot reflect such a difference. Although the device

is expected to work well beyond the 1.52 to 1.58 μm wavelength range, the finite

bandwidth of our tunable laser precluded measurement over a wider range. In addition to

the experimentally measured losses, simulated losses for the TM and TE modes of the

designed polarizer (with rectangular cross section) are shown in Fig. 6.3 (solid line). Fig.

6.3 also displays the simulated losses for the fabricated device with trapezoidal cross

section and 25 nm off center chromium layer (dashed lines). Simulation results for the

designed and fabricated device indicate that deviations of dimensions resulting from

fabrication imperfection have little effect on its performance (less than 3 dB for the TM

mode and less than 1 dB for the TE mode).

1.52 1.54 1.56 1.580

5

10

15

20

25

30

35

TE

Designed device (FDTD) Fabricated device (FDTD) Experimental

Inse

rtion

Los

s (dB

)

Wavelength (μm)

TM

Fig.6.3. Insertion losses of the TE and TM modes for a 30 μm long HPWG TE-pass polarizer.

80

1.52 1.54 1.56 1.5810

15

20

25

30

Designed device (FDTD) Fabricated device (FDTD) ExperimentalEx

tinct

ion

ratio

(dB

)

Wavelength (μm) Fig.6.4. Extinction ratios for a 30 μm long HPWG TE-pass polarizer.

From Fig.6.3 and Fig.6.4 we observe that the experimental results agree well with the

predictions from simulations. The slight discrepancy between the simulations and

experimental results is not unexpected. For our simulations, we have taken the material

properties of the chromium from Palik [31]. The permittivity of the chromium, especially

the imaginary part of the permittivity, can vary significantly depending on the deposition

conditions, which will result in some discrepancy [44]. Moreover, in our simulations we

have neglected the losses due to the scattering from surface roughness. When comparing

the TE-pass polarizer with the reference waveguides, the scattering losses from the

silicon nano waveguides is not an issue because both have similar scattering losses, but

there is additional scattering losses between the chromium and silica in the hybrid section.

The precision of the measurement also affects the experimental results; especially since

the output power of the TM mode is very small, making the recoding of the data for this

mode quite sensitive to the noise. All these contribute to the discrepancy between the

simulations and measurements for the polarizer, but as we can see by comparing the plots

in Fig. 6.3, the agreement between the measurement and simulation is still very good.

81

6.3 Conclusion

We designed and fabricated a HPWG TE-pass polarizer. The results show it outperforms

previously proposed SOI compatible TE-pass polarizers. Although many different types

of TE-pass polarizers were investigated in the past, the number of experimental

demonstrations of SOI compatible TE-pass polarizer is very few [36, 37]. A silicon rib

waveguide coated with aluminum can act as a TE-pass polarizer [36], but the device

length is more than a millimeter and extinction ratio achieved is relatively low (< 20 dB).

Shallow-etched ridge waveguide TE-pass polarizers reported in [37] are very simple to

fabricate and the insertion loss of the TE and TM modes achieved for the device are

comparable to that of our current work, but the device is 1 mm long. Here, we have

achieved an extinction ratio of 23-28 dB and a moderate loss for the TE mode for a

device length of only 30 μm. Therefore, the device presented in this thesis is a compact,

broadband, SOI compatible TE-pass polarizer.

82

Chaper 7 Conclusion and Future works

7.1 Summary of the Contributions We have analyzed the HPWG that consists of a metal plane separated from a high index

slab (silicon) by a low index spacer (silica). To illustrate the features of the HPWG, we

have also analyzed the plasmonic slot waveguide and the DLSPW in terms of

confinement and loss and tried to identify their relative advantages and limitations

compared to HPWG. The results show HPWG can confine the power in a compact region

with moderate propagation loss.

The HPWG also shows polarization diversity for the two fundamental modes. Taking the

advantage of this feature, we can design compact on-chip devices to control and

manipulate the on chip polarization state. A compact on-chip TE-pass polarizer based on

the HPWG concept has been designed, modeled, fabricated and experimentally

characterized. Although many different types of TE-pass polarizers have been

investigated in the past, the number of experimental demonstrations of silicon compatible

TE-pass polarizer is very few. The device is very compact with a low insertion loss, high

extinction ratio. It is highly compatible with standard fabrication techniques. It provides

the possibility to shorten integrated optical circuits.

83

7.2 Future Works

We have successfully demonstrated the application of HPWG as a very compact TE-pass

polarizer. The experience gained during the design and experimental demonstration

activities should be useful for implementation of other on-chip HPWG devices like a

TM-pass polarizer [28], a polarization independent hybrid plasmonic coupler [29]. There

are some fabrication challenges that need to be overcome for future devices. In the

HPWG section, the silicon thickness varies for different applications. We need to

optimize the recipe to achieve a smooth surface for partial etching. The slanted silicon

wall is acceptable in the proposed TE-pass polarizer; however, it may be a problem for

other devices. Deep reactive ion etching (DRIE) method could be used instead of RIE to

achieve more vertical sidewalls.

When the waveguides are used in the integrated optical circuit, it is important to consider

the packing density and in particular how close two waveguides can be put without

causing significant power coupling. The HPWG can offer a way for achieving close

packing with the cost of some propagation loss. We would continue to analyze the

properties of HPWG for application for high density interconnection circuits.

With the experience in design, modeling and fabrication optical devices based on the

HPWG, we can continue further research on the integrated optical circuits, and

investigate the possibility of finding an efficient way to integrate optical circuits with

electronic circuits.

84

Appendix A Optimizion of Silicon Width for Confinement of HPWG

For the power density (D) vs. propagation loss analysis, the structure of HPWG is shown

in Fig. 3.13 (a). For the HPWG, the TM mode is coupled between surface plasmonic

mode and dielectric mode. This results a high power density in the gap (g), as shown in

Fig. 3.13 (b). The properties are affected by w, d, and g. In chapter 3 we have analyzed

the confinement for HPWG with w = 200 nm. The relation of confinement factor (Γ) and

power density (D) with w are plotted in Fig. A.1 for a fixed d = 200 nm. As shown in

Fig.A.1 (b), D is high when w = 200 nm. Thus we choose a fixed w = 200 nm and change

other dimensions in the analysis in chapter 3.

100 150 200 2505

10

15

20

25

30

35

w (nm)

g = 10 nm g = 50 nm g = 100 nm

Γ (%

)

(a)

100 150 200 250

20

40

60

80

100

g = 10 nm g = 50 nm g = 100 nm

D (m

w/μ

m2 )

w (nm)

(b) Fig.A.1. Confinement factor and Power Density for HPWG with w. (a) Confinement factor. (b) Power

density.

85

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88

List of Publications

Journal Contributions [1] X. Sun, M. Z. Alam, S. J. Wagner, J. S. Aitchison, and M. Mojahedi, “Experimental demonstration of a hybrid plasmonic transverse electric pass polarizer for a silicon-on-insulator platform,” Opt. Lett. 37, 4814-4816, 2012.

Conference Contributions [1] X. Sun, M. Z. Alam, S. Wagner, J. S. Aitchison, M. Mojahedi, “Compact hybrid plasmonic TE-pass Polarizer on SOI,” in Conference on Lasers and Electro-optics (CLEO)/Quantum Electronics and Laser Science Conference (QELS), OSA Tech. Digest (OSA, 2012), paper CTu1A.8.

[2] X. Sun, M. Z. Alam, J. S. Aitchison, M. Mojahedi, “Comparison of confinement and loss of plasmonic waveguides,” in Photonics Conference (IPC), 2012 IEEE , paper WX 5. [3] J. S. Aitchison, M. Z. Alam, X. Sun, and M. Mojahedi, “Hybrid Plasmonic Waveguides for On-chip Polarization Control,” in Frontiers in Optics Conference, OSA Tech. Digest (OSA, 2012), paper FTh3A.1.