HT98F069 Two-way Radio Flash MCU Application GuidelinesHT98F069 Two-way Radio Flash MCU Application...

HT98F069 Two-way Radio Flash MCU Application Guideline

AN0439E V1.00 1/39 December 11, 2016

HT98F069 Two-way Radio Flash MCU Application Guidelines

D/N: AN0439E

Introduction The Holtek designed HT98F069 device is a Flash ASSP MCU for analog two-way radio

applications. In professional walkie-talkie applications, by connecting to a suitable RF FM

modulation circuit or IC, the device provides TX/RX baseband signals including audio

tone/sub-tone, DTMF, selective call tone outputs, etc. With regard to the human-machine

interface, the device provides I/O ports for button or number key input and an A/D converter

for temperature or battery power measurement. Regarding the audio functions, the device

provides an MIC input to the internal signal amplifier and an audio output for external power

amplifier driven speakers. The HT98F069 includes an internal audio processor which

provides not only basic processing functions needed by the audio/sub-audio walkie-talkies,

but also advanced functions including pre-emphasis/de-emphasis, CTCSS/DCS codec,

DTMF codec, scramble/descramble and VOX, etc. These signals are transmitted to the

receiver via the RF carrier.

Functional Description Channel limitations exist for general walkie-talkie applications. For example, most of the

Family Radio Service (FRS) walkie-talkies in mainland China provide 16 channels.

Situations where different talk groups select the same channel resulting in cross talk may

occur easily. To solve this problem, the HT98F069 audio processor provides a sub-tone

setup greatly reducing mutual interference between different talk groups.

Regarding its advanced functions, the HT98F069 audio processor provides both DTMF

and select call configurations to specify the recipient, which can be used in systems

similar to phone number applications. The scrambler/de-scrambler function can be used

for audio encryption to improve the signal confidentiality. Different mechanisms including

a compandor, pre-emphasis/de-emphasis and digital filters, etc., are provided to solve

signal interference issues that may be created by a range of conditions.

The VOX function supports multi-level voltage threshold configurations, a baseband

signal level modulation function, an MIC automatic gain control function for volume

adjustment and other functions which are also included in the audio processer.


AN0439E V1.00 2/39 December 11, 2016

Operating Principles The walkie-talkie related functions are introduced below.

• Sub-tone

CTCSS (Continuous Tone Controlled Squelch System) encoder/decoder

This technology, commonly known as sub-tone, adds a frequency in the range of

67Hz~254.1Hz which is lower than the audio frequency, into the audio signal and

transmits them together. The sub-tone, which gets its name as its frequency is

lower than standard audio frequencies, is used as a control signal. In practical

applications, the transmitter and the receiver can hear each other’s voice only

when both sides use the same sub-tone.

DCS (or CDCSS, Continuous Digital Controlled Squelch System) encoder/decoder

DCS or CDCSS technology works in a similar way to CTCSS. The only difference

between them is that the off-tone on/off condition of DCS is digitally encoded.

• Audio signal

DTMF (Dual-Tone Multi Frequency) encoder/decoder

The DTMF signal is composed of a high frequency signal and a low frequency

signal. The high and low frequency groups each include four frequencies. A high

frequency signal and a low frequency signal are superimposed to form a

combined signal which indicates a digital number. The DTMF signaling supports

16 encodings which can be used to call the corresponding walkie-talkie.

Selective call tone (EEA standard) / In-band tone (user-defined)

This allows the user to define a user-tone with a frequency between 300Hz and

3000Hz, such as in 2-tone or 5-tone applications, to call the corresponding

walkie-talkie. An EEA or EIA selective call defined tone set is commonly used in

applications.

• Other signals

DCS turn off tone

An off-tone will be transmitted following the DCS tone to turn off the speaker thus

avoiding tuneless voices. Some walkie-talkies use a 136Hz signal as the off-tone

which will last about 100ms~300ms.

• Advanced audio processing

Scrambler/De-scrambler

This function is used for audio encryption. Only the walkie-talkies using the same

audio encryption function can hear the correct voice while others cannot hear the

clear content.

Compandor

To reduce the noise generated during RF transmission, small signals are

expanded and large signals are compressed when being transmitted. For

reception, small signals are compressed and large signals are expanded.


AN0439E V1.00 3/39 December 11, 2016

Pre-emphasis/De-emphasis

As the signal will deteriorate after its high frequency part is modulated, a

pre-emphasis function is provided, which aims to reduce the low frequency gain

and increase the high frequency gain. The received signal will be recovered using

the de-emphasis function.

Digital Filters: 12.5K, 25K, HPF(300) Filter

• Baseband signal level modulation

This function is used to adjust the audio tone, sub-tone and signal amplitude.

• VOX

The voice-activated emission function does not require users to press the PTT

(Push-to-Talk) button because it uses the voice to activate emission. The

transmitter will stop emission and change to the receiver mode when users stop

talking.

• MIC AGC

The MIC Automatic Gain Control function can automatically adjust gain for

different microphone input signals, to ensure that the audio signal is not too low or

distorted. When the speaker’s voice is too loud or too small, the AGC function will

automatically reduce or increase the gain respectively, to ensure that the

walkie-talkie system maintains a constant volume.

• Application areas

Floor wireless walkie-talkies

These wireless walkie-talkies will gradually replace traditional wired types in order

to save costs for new buildings and to facilitate the replacement of old equipment.

The new type of walkie-talkies can use the VOX function to directly transmit voice

and the CTCSS, DCS, DTMF and Selective Call functions can also be used for

different floor or for household selective intercom and broadcasting.

Handheld walkie-talkies / Car wireless walkie-talkies

The HT98F069, which focuses on these application areas, provides the main

functions needed by walkie-talkies including CTCSS, DCS, DTMF and Selective

Call functions as well as audio processing such as pre-emphasis/de-emphasis,

compandor and scrambler.


AN0439E V1.00 4/39 December 11, 2016

Hardware Description

Block Diagram

MCU

DAC1

MICOP

PGA_B[4:0]EN_PGABEEP1

DEMODAUXVAG

PGAI_S[7:5]

MICOAudio

Processor

/EN_DAC1 SDAO1

AMP1

EN_AMP1

DAC2

/EN_DAC2 SDAO2

AMP2

EN_AMP2

MODO

SMOD

AUDO_S[4:2]

Buffer

EN_BUF

SMOD

DAC bias

BEEP0

Input unit Output unit – MODO / SMOD (to RF)Audio process unit

Output unit – Audio (to Speaker)MCU unit

MICOP

EN_MIC

MICI

Hardware Block Functional Description

• Audio processor unit: Used for audio signal processing.

• Input unit: Used to select the input source and is composed of MIC OPA, Multiplexer and PGA. The Multiplexer can be used to select different audio sources and modulated signals including MICO, DEMOD, AUX and BEEP1.

• Output unit – MODO/SMOD: The signal outputs includes MODO for baseband signal output and SMOD for sub-tone signal output. A user-defined sub-tone signal is also output on the SMOD pin.

• Output unit – Audio: Audio output. The Multiplexer can be used to select the DAC1 or BEEP0 output.

• MCU unit: The MCU control unit is the user program execution unit which is used for I/O and program flow control.


AN0439E V1.00 5/39 December 11, 2016

Application Circuit

The application circuit is divided into four parts, as described below.

• Clock/PLL Circuit: Y1, R7, C16 and C17 are PLL sources, where Y1 should be a 32.768kHz crystal to lock the PLL to the preset frequency. R6, C14 and C15 form the PLL filter circuit. These component values are provided as a design reference.

• MIC/AUX/DEMOD: Microphone/auxiliary audio source/baseband inputs. The MIC interface includes an internal OPA with a gain of -R2/R1, where R2 value should be changed according to actual applications. Refer to the AGC chapter for more information about the R2 value selection if the integrated AGC function is used. DEMOD is the RF modulated baseband signal input port. AUX is the external audio source input port which supports applications requiring an external audio source connection. In principle, the input signal should be limited to meet the following condition: {signal × PGA gain ≤ VDD×0.7(AD max.)}.

• MODO/SMOD/AUDO: Baseband/sub-tone/audio source outputs. MODO outputs the baseband signal which is then connected to the RF input. SMOD outputs the sub-tone signal which can be used in applications requiring sub-tone. AUDO outputs the modulated audio signal, which goes through an LPF circuit and then is connected to a speaker driving circuit, e.g. the HT82V739, to generate the voice. The AUDO output signal presents a ladder pattern by the influence of nearby channel power or sound quality, in which case a LPF circuit must be connected.

• Power Supply Circuit: It is necessary to pay attention to the effects caused by VCC power supply changes due to the large currents generated when the Audio Processor is turned on. This could be 25mA at 3.3V with no load. C11 is a tantalum capacitor for compensation. Considering the situation of analog and digital mutual interference, it is suggested to arrange two groups of VCC and GND, one for the analog circuits and one for the digital circuits. The power supplies and grounds are respectively connected via a BEAD component. With regard to the voltage, it is recommended to provide an operating voltage of 3.6V or more, which is determined by the actual power consumption of the user application circuit.


AN0439E V1.00 6/39 December 11, 2016

Pin Assignment

• 64LQFP Real Chip & OCDS HT98F069: Real Chip HT98V069: OCDS

PD4P

F6P

A7/R

ES

VD

DP

F1P

F2

PF5PF4

PF3

PD5

PD7PD6

HT98F069/HT98V06964 LQFP-A

12345678910111213

20 21 22 23 24 25 26 27 28

6061626364

29 30 31 32

5253545556575859

141516

434445464748

36373839404142

333435

17 18 19

495051DEMOD

VAGREF

PE0

VSSA2VCCA2

VAG

AUDOMODO

VCCA1AUX

SMOD

PE1

PB2/DAO2PB1/DAO1PB0/DAO0

PF0

XO

UT

VS

SA

XIN

PLLC

PB

5/GP

IO1

PB

4/GP

IO0

PD

3P

D2

PB

3/DA

O3

VS

SV

CC

A4

VC

CA

3PA3/AN3/INTPA2/AN2/TMR0/ICPCK/OCDSCKPA1/AN1/PFDPA0/AN0/ICPDA/OCDSDAPB7/GPIO3

PC3/AN7

PC0/AN4

PC2/AN6PC1/AN5

PB6/GPIO2

MIC

_I

PC

6/SP

ICK

PC

7/SP

ISS

PD

0

PF7

MIC

_O

PD

1

PA

6/TMR

2P

A5/M

ISO

PA

4/TMR

1P

C4/M

OS

IP

C5/S

PIR

Q

VS

SV

SS

A1

• 48LQFP Real Chip & OCDS HT98F069: Real Chip HT98V069: OCDS

DEMOD

VAGREF

PE0

PB0/DAO

0

VSSA2VCCA2 PB6/GPIO2

XOU

T

MIC

_I

PC6/SPIC

KPC

7/SPISSPD

0

VSSA1M

IC_O

PD1

PA6/TMR

2PA5/M

ISOPA4 /TM

R1

PC4/ M

OSI

PC5/SPIR

Q

PA3/AN3/INTPA2/AN2/TMR0/ICPCK/OCDSCKPA1/AN1/PFDPA0/AN0/ICPDA/OCDSDAPB7/GPIO3

PA7/RESPC3/AN7

PC0/AN4

PC2/AN6PC1/AN5

VSS

VDD

XINPLLCPB5/G

PIO1

PB4/GPIO

0PD

3PD

2PB3/D

AO3

PB2/DAO

2P B1/D

AO1

VAG

AUDOMODO

VCCA1AUX

SMOD

PE1 HT98F069/HT98V06948 LQFP-A

123456789101112

13 14 15 16 17 18 19 20 21 22 23 24252627282930313233343536

45464748 3738394041424344


AN0439E V1.00 7/39 December 11, 2016

Software Description System Frequency Switching When starting system initialisation a desired operating frequency should first be selected

using the CTRL2[7-5,3-0] and CTRL0[0] bits.

System Control Register 2 (CTRL2)

Bit 7 6 5 4 3 2 1 0 Name M1 M0 PLLD2 AUPRST PLLEN PLLD1 PLLD0 LXTEN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 1 0 0 1 1 0

The CTRL2[3] bit is the PLL on/off control bit for enabling or disabling the PLL circuit. The

CTRL2[7:6] bits are used to select the PLL output frequency. There are four options

which can be selected based on actual applications. The CTRL2[5] bit is used to select

the PLL output frequency division ratio for the Audio Processor, which can be 2 or 4. The

CTRL2[2:1] bits are used to select the PLL output frequency division ratio for the MCU,

which can be 2, 4, 8 or 16. The CTRL2[0] bit, LXTEN, is the external crystal LXT control

bit, which together with the HALT instruction controls whether the system enters the IDLE

mode (LXTEN=1, LXT on) or the SLEEP mode (LXTEN=0, LXT off).

System Control Register 0 (CTRL0)

Bit 7 6 5 4 3 2 1 0 Name PCFG PFDCS – – – PFDC LXTLP CLKMOD R/W R/W R/W – – – R/W R/W R/W POR 0 0 – – – 0 0 1

The CTRL0[0] bit is used to select the MCU speed mode. When the bit is set to “1”, the

MCU will operate in the low speed mode which is 32.768kHz. When the bit is cleared to

“0”, the MCU operates in the PLL mode. Users should first select the PLL output

frequency and PLL output frequency divider for the MCU and Audio Processor

respectively before turning on the PLL. Then wait for 10ms to allow the PLL to stabilise.

After this the frequencies generated by the dividers can be respectively used as clock

sources for the MCU by clearing the CTRL0[0] bit and for the Audio Processor by

properly configuring the CTRL2[4] bit. Once the system has entered the PLL mode, it is

not recommended to change the PLL related configurations.

PLLEN M1, M0

fPLL (Hz)

MCU System Clock, fSYS (MHz) Audio Processor (MHz)

PLLD1 , PLLD0 PLLD2 0,0 (÷2) 0,1 (÷4) 1,0 (÷8) 1,1 (÷16) 0 (÷2) 1 (÷4)

0 X 32.768K 32.768kHz 32.768kHz 1 0,0 24.576M 12.288 6.144 3.072 1.536 12.288 6.144 1 0,1 32.768M 16.384 8.192 4.096 2.048 16.384 8.192 1 1,0 40.960M 10.24(Note) 10.240 5.120 2.560 20.480 10.240 1 1,1 49.152M 12.288(Note) 12.288 6.144 3.072 24.576 12.288

X: Don’t care

MCU and Audio Processor PLL Divider Table

Note: When fPLL=40.960MHz/49.152MHz, the PLLD1 and PLLD0 bits will be forced to “01”

by the hardware to select a division ratio of 4.


AN0439E V1.00 8/39 December 11, 2016

PLL Control Flow for MCU

N

Start

Delay 10ms

Next Step

Y

Set divider & turn on PLL

CLKMOD=0 (MCU=PLL mode)

Flow Description:

<Set … PLL>: configure the PLL output frequency divider and enable the PLL.

<Delay10ms>: Delay 10ms. Wait for 10ms for the PLL stabilisation.

<CLKMOD=0>: The MCU is configured to operate in the PLL mode.

PORCLKMOD

PLLEN

32K CLK

PLL

MCU CLK

LXTEN

Instruction

Power on Slow mode Normal mode

tSST1tRSTD tFUP

Idle mode

Power On Sequence:

HaltLXT EN

PLL EN

CLKMOD DIS


AN0439E V1.00 9/39 December 11, 2016

How to Control Audio Processor

Audio Processor Reset After the PLL is enabled, the audio processor can be turned on using the CTRL2[4] bit.

This bit is the audio processor reset control bit. When changed from “1” to “0” and then to

“1” again it will turn on the audio processor. This bit will be low after a power on reset and

should not be set high when configuring the PLL. After the audio processor has been

reset using the CTRL2[4] bit, first wait for at least 100ms (fAP=24.576MHz(Note)) before

executing any subsequent commands. This time period is required for the Audio

Processor internal initialisation including RAM initialisation and turning on the related

functions such as ADC and DAC. Any SPI commands executed during this time period

will be invalid.

Audio Processor Reset Flow

NDelay > AUP initial time

Next Step

Y

Can set SPI command

Turn on Audio Processor

CTRL2[4] = 1

Delay nop*2

CTRL2[4] = 0

Delay nop*2

CTRL2[4] = 1

Flow description: <CTRL2[4]>: Audio processor reset bit. The correct reset control sequence is 1 0

1, with two “nop” instructions inserted between each control instructions. <Delay>: Audio processor initialisation time. Wait for at least 100ms. The SPI data

transmitted during this period may be overwritten resulting in invalid write operations.

Audio Processor Turn on Timing

0

V

VDDAudio processor reset

(CTRL[4])

Audio processorinitialisation

Time

Audio processor canReceived command

Audio Processor Turn on Timing

Note: fAP=Audio processor system frequency.


AN0439E V1.00 10/39 December 11, 2016

SPI Command The audio processor uses an SPI interface to communicate with the MCU. Some specific

external pin-shared I/O ports will be selected to communicate with the external MCU

when the SPICR[7] bit is cleared to zero. This will be introduced in the next few sections.

The internal SPI circuit will be selected to communicate with the internal MCU when the

SPICR[7] bit is set high, in which case the actual circuit control is implemented using the

related control bits, as described below.

SPI Control Register (SPICR)

Bit 7 6 5 4 3 2 1 0 Name IEMC — ERAM SPISS SPICK MOSI MISO SPIRQ R/W R/W — R/W R/W R/W R/W R R POR 1 — 0 1 0 0 x x

“x”: unknown

SPICK MOSI MISO SPISS SPIRQ SPICR[7]=1 SPICR[3] SPICR[2] SPICR[1] SPICR[4] SPICR[0] SPICR[7]=0 PC6 PC4 PA5 PC7 PC5

SPI Internal/External Control Signal Table

A complete data group with a data length of 20 bits is transmitted MSB first. Each data

group contains a 4-bit group command and 16 bits of data. There are two group types,

one is I/O command group and the other is CLI command group, which support an SPI

frequency of up to 16 MHz and 150 kHz respectively. It is recommended to use an SPI

frequency lower than 150 kHz in applications, in which case both group types can share

the same SPI transmitting and receiving programs. The I/O commands are used for

circuit control, data sharing and other major application blocks. The I/O commands are

named by “I/O CMD-NNh”. The CLI (Control Layer Interface) commands are used to

access the audio processor related parameters such as thresholds, parameters,

variables and execute the advanced application control, etc. Being different from the I/O

Group type, the CLI Group type requires three commands to implement a data write and

two commands for a data read. The CLI commands are named by “CLI CMD-NNNNh”.

SPISS

SPICK

MOSI

MISO

SPIRQ

C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

HT98F069 SPI Communication Format


AN0439E V1.00 11/39 December 11, 2016

SPI Application Description

I/O Command (C[3-0]: Write/Read=8xxxx/9xxxx)

Bits[19-16] are set differently for read and write. They are set to “8(Dec)” for write

commands and “9(Dec)” for read commands. When writing data, the audio processor will

not reply with any data. For a read command, the D7~D0 bits are don’t care and the

A7~A0 bits are the register address. For the audio processor reply, the D7~D0 data bits

will be read.

• Write I/O CMD Master Write

SPI[19:16] SPI[15:8] SPI[7:0] 4’b1000 Address (A7~A0) Data (D7~D0)

Audio Processor Reply

SPI[19:16] SPI[15:8] SPI[7:0] x (no signal) x (no signal) x (no signal)

• Read I/O CMD Master Write

SPI[19:16] SPI[15:8] SPI[7:0] 4’b1001 Address (A7~A0) x (Don’t care)

Audio Processor Reply

SPI[19:16] SPI[15:8] SPI[7:0] 4’b1001 Address (A7~A0) Data (D7~D0)

Example: write data “3Ch” to the I/O command register “1Eh” and read data from the

register to check whether the data has been correctly written.

• Write data to register 1Eh

Done

Audio Processor

No reply

Write data 3Ch to 1Eh Reg.

Done

Master

Command: 81E3Ch

Flow description: <81E3C>: Turn on the DAC2, DAC1, AMP2, AMP1, Buffer, MIC and PGA circuits. After

this command is sent, there is no reply.

• Read data from register 1Eh

Done

Audio Processor

Reply 91E3Ch (1Eh Reg. data)

Read data from 1Eh Reg.

Done

Master

Command: 91E00h

Flow description: <91E00>: Read data from register 1Eh. After this command is sent, the data from the

register 1Eh will be replied.


AN0439E V1.00 12/39 December 11, 2016

CLI Command This interface protocol is different from the I/O command. It requires three 20-bit SPI data

for the write mode and two for the read mode. The first CLI command is the identifier

code, the second one is the 16-bit address and last one is the 16-bit data. There is no

data word for the read command. The identifier code is 14181 for read and is 14082 for

write. The audio processor will continue to receive the next data after verifying that the

indentifier code is correct. After the data has been written, the audio processor will reply

with data, 14000, to indicate that the data has been correctly written. Otherise the data

write operation has falied.

• Write CMD Details

Phase CLI_CMD Major Minor Multi Length ○1 E 4’b0001 4’b0100 4’b0000 4’b1000 4’b0010 A○2 E 4’b0001 Address[15:0] A○3 E 4’b0001 Data[15:0]

Reply

Phase CLI_CMD Major Minor Multi Length A○4 E 4’b0001 4’b0100 4’b0000 4’b0000 4’b0000

Note: When the audio processor replies with “14000”, it means that the write data

condition has been met.

SPISS

SPICK

MOSI

MISO

SPIRQ

1 2 3 4

After the CLI command SPI write command phase 3, the SPIRQ line will be low. The user

must check the SPIRQ status to issue SPI read phase 4. The return data will be “14000”.

• Read CMD Details

Phase CLI_CMD Major Minor Multi Length A○1 E 4’b0001 4’b0100 4’b0001 4’b1000 4’b0001 A○2 E 4’b0001 Address[15:0]

Reply

Phase CLI_CMD Major Minor Multi Length A○3 E 4’b0001 4’b0100 4’b0000 4’b0000 4’b0000 A○4 E 4’b0001 Data[15:0]


AN0439E V1.00 13/39 December 11, 2016

SPISS

SPICK

MOSI

MISO

SPIRQ

1 2 3 4

After the CLI command SPI read command phase 1 and 2, the SPIRQ line will be low.

Users must check the SPIRQ status to issue the SPI read phase 3 and 4. In phase 3, the

HT98R069 will return “14181”. In phase 4, the requested data will be returned.

Example: write data “FFFFh” to CLI register “04CBh” indicating that both the MODO and

SMOD pins output the maximum volume, and then read the register.

• Write data to register 04CBh

NWrite ok?

Done

YReply 14000

Audio Processor

Write data FFFFh to 04CBh Reg.

Identifier ok? N

Y

Done

Audio Processor

Command: 104CBh

Command: 1FFFFh

Command: 14082h

Flow description: <14082>: CLI write identifier code. To execute the CLI command write operation, this

command should first be sent. There is no data reply after this command. <104CB>: Select register 04CB. It assigns the register to be written with data. There is

no data reply after this command. <1FFFF>: Write data FFFFh. Write the data to the register after which a data value of

14000 will be sent back if the write operation is correct. Otherwise the data write will have failed.

• Read data from register 04CBh

Done

Reply 14181h

Audio Processor

Read data from 04CBh Reg.

Identifier ok? N

Y

Done

Audio Processor

Command: 104CBh

Command: 14181h

Reply 1FFFFh (04CBh Reg. data)


AN0439E V1.00 14/39 December 11, 2016

Flow description: <14181>: CLI read identifier code. To execute the CLI command read operation, this

command should first be sent. There is no data reply after this command. <104CB>: Select register 04CB. It assigns the register to be read. After this command

is sent, the audio processor will first reply with a data value of 14181 and then a data value of 1FFFFh. This means that the data in the register 04CB is FFFFh.

External Control In addition to communicating with the integrated MCU, the audio processor also supports

external MCU control using the SPI interface. Some necessary initialisation including PLL

setup, reset control and SPI path selection, should first be executed before using the

external control mode. After the PLL has ben properly configured and the audio

processor has been correctly reset, which have been described in the previous section,

clear the SPICR7[7] (IEMC) bit to zero to switch the SPI path to the external pin-shared

pins. After this, external SPI commands are permitted and the five pin-shared I/O pins

can not be used as other functions.

SPICK MOSI MISO SPISS SPIRQ SPICR[7]=1 SPICR[3] SPICR[2] SPICR[1] SPICR[4] SPICR[0] SPICR[7]=0 PC6 PC4 PA5 PC7 PC5

SPI Internal/External Control Signal Table

ExternalMCU

InternalMCU

Audio Processor

IEMC

HT98F069

SPI SPI

SPI

External MCU Connection Diagram

• Use External Control Flow

SPI Init (Internal)Control signal statusSPI External

SPICR[7] = 0 SPICR[7] = 1

PLL setting

Audio processor turn on

DCS RX

Internal MCUControl flow

External MCUControl flow


AN0439E V1.00 15/39 December 11, 2016

Flow description:

<PLL setting …>: Turn on and configure the PLL.

<Audio processor …>: Audio processor reset control.

<Control Signal status>: Detect the control signal status and select the external or

internal SPI path.

<SPICR[7]=0 or =1>: SPI external/internal mode select.

<External or Internal MCU control flow>: Execute external or internal MCU control flow.

IDLE, SLOW, TX, RX Mode Select Configuration When the device is used in the wireless walkie-talkie applications, different modes are

implemented by different circuit and function on/off controls following different timing.

Energy saving and signal interference elimination can be achieved by switching to the

correct input or output source and turning off unnecessary circuits. It requires a time

period for circuit stabilisation, which is about 250ms and may drift for different circuits,

unless the system enters the sleep status. Circuit controls can be easily implemented by

the I/O command group. In this way unnecessary processing sources can be released.

The following section will introduce three modes while the SLOW mode will be introduced

in the VOX section.

IDLE Mode

When the audio processor is not processing data, it can enter this mode to save power

consumption and the actual power saving capability is determined by actual conditions.

The audio processor on and off control functions are separated. Its turn off control

command sequence is 81EC1h81B93h80F00h and its turn on control command

sequence is 81E3Fh 80F00h80F02h. When no event occurs, first switch off the

audio processor clock and then use the MCU to detect external signals. If an external

signal is acknowledged, turn on the audio processor to process the signal.

• IDLE Mode Setup Flow

N

IDLE Mode

Have event?

Command: 81EC1h

Return

Y

Command: 81B93h

Command: 80F00h

Command: 81E3Fh

Command: 80F00h

Command: 80F02h

Delay 100ms?N Y


AN0439E V1.00 16/39 December 11, 2016

Flow description:

If there is no output or input signals to process, the audio processor can be temporarily turned off. When it is turned on again, it can process signals immediately without re-initialisation.

<81E3F>: Turn on all the audio circuits or only turn on the required circuits.

<80F00>: Execute reset.

<80F02>: Soft start the audio processor.

//

<81EC1>: Turn off all the audio circuits. Reduce or cut off unnecessary power consumption.

<81B93>: Set the internal common-bias as input and output paths. This command will select the common-mode bias as input/output path to reduce decoding errors and will also reset the receiver status.

<80F00>: Turn off the audio processor and reset.

TX Mode

Whether to enter the TX mode is determined by the input data trigger condition, such as a

PTT event or a VOX signal, etc. Operations including mode switch, input source selection

and circuit on/off controls are usually implemented in this mode. It is suggested to switch

the audio buffer input source to the bias path to reduce noise, or turn off the buffer using

the I/O CMD-1Eh[3] or execute both configurations. When switching between the TX and

RX modes, it is recommended to first execute the circuit on/off controls, then select an

input/output path and finally the switch mode. In this way errors can be reduced as much

as possible. A flowchart is provided as follows to illustrate the PTT event processing.

Example: setup the TX Mode, Input = MIC, Output = MODO, No sub-tone.

• TX Mode Setup Flow

N

TX Mode

Is PTT event?

Command: 81E97h

Return

Y

Command: 81B10h

Command: 81140h

Flow description:

<81E97>: Turn on the DAC1, AMP1, MIC and PGA circuits. This command executes circuit on control including DAC1 on, AMP1 on – MODO output on, MIC on – microphone circuit on and PGA on – PGA input on.

<81B10>: Select PGA input source and audio output source. Select MIC as PGA input source, DAC common-mode bias as audio output source to reduce noise.

<81140>: Enter the TX mode. Select the TX mode to enter the TX processing flow.


AN0439E V1.00 17/39 December 11, 2016

RX Mode

This mode is mainly used for baseband signal demodulation. Although the action of

waiting for RF signal can be implemented in this mode, it is strongly recommended to first

check and ensure that the RSSI (Receive Signal Strength Indicator) signal is acceptable,

then switch the input path to DEMOD before finally turning on the audio processor to

process the signal. This will not only save energy but also reduce the possibility of

misjudgment. The SPI command configurations for the mode switch, path selection and

circuit on/off control are provided as follows.

Example: RX Mode, Input = DEMOD, Output = AUDO (Source = DAC1), No sub-tone.

• RX Mode Setup Flow

N

RX Mode

Is RSSI ok?

Command: 81E8Bh

Return

Y

Command: 81B25h

Command: 81160h

Flow description:

<RSSI OK>: Check whether the RF signal is OK.

<81E8B>: Turn on the DAC1, Buffer and PGA circuits. This command executes circuit controls including DAC1 on -- DAC1 output on, AUDO output buffer on – audio output circuit on and PGA on – PGA input on.

<81B25>: Select PGA input source and audio output source. Select DEMOD as PGA input source, DAC1 as audio output source and the internal common-mode bias as DAC1 output pin source to avoid audio signal leakage on the MODO pin.

<81160>: Enter the RX mode. Select the RX mode to enter the RX processing flow.

Audio Processor IRQ Any audio event which occurs can be regarded as an Interrupt Request (IRQ), after which

the master is required to send a 20-bit SPI data. The first 12 bits of data is 100h and the

remaining bits correspond to I/O CMD-23h. As long as there is an event state change,

either from “0” to “1” or from “1” to “0”, the corresponding interrupt request will be

generated. The I/O CMD-23h register should be polled again to check whether the event

is valid or invalid. The I/O CMD-22h register is used for interrupt mask selection. Before

using any interrupt request, the global interrupt request must first be enabled (I/O

CMD-22h[6]=1). This function allows designers to wait for a signal without polling each

event source and to process the event when an event interrupt request is generated. This

improves the MCU execution efficiency. The event interrupt format is described below.


AN0439E V1.00 18/39 December 11, 2016

Event Interrupt Mask -- 22h Address

Bit 7 6 5 4 3 2 1 0

Name — IRQ DTMF INT

Selective call INT

CTCSS INT

DCS INT

Off_Tone INT

VOX INT

Audio Processor IRQ Event Masking Control Register

Event VOX DCS CTCSS SelCal_Tone DTMF off_Tone IRQ SPI data 10001h 10004h 10008h 10010h 10020h 10002h Polling I/O Command 23h

01h 04h 08h 10h 20h 02h

Polling I/O Command 30h

— — 01h — — —

IRQ & Polling Comparison Table (when Signal Asserted)

Example: Detect CTCSS Tone.

• CTCSS Event Interrupt Flow Step 1: Enable CTCSS INT

Done

CTCSS INT turn on

Command: 82248h

Step 2: RX Audio Processor ISR

N

Audio Processor ISR

Is received 10008h?

Done

Y

Command: 92300h Other status

RX message

Step 3: RX 23h Detection Flow

N

Audio Processor ISR

Is received 92308h?

Done

Y

Assert CTCSS status De-assert CTCSS status

RX message


AN0439E V1.00 19/39 December 11, 2016

Flow description (1): <82248>: Interrupt enable and selection. Select the CTCSS interrupt and enable its

interrupt event.

Flow description (2): <Is received 10008>: Confirm that the interrupt signal is a CTCSS event. <92300>: Poll the event status.

Flow description (3): <Is received 92308>: Check whether the CTCSS event is acknowledged (92308h) or not

(92300h).

Audio Processor Status Reset In normal decoding situations, the audio processor will decide how to process according

to the data code, frequency and amplitude of the signal, and the event status register (I/O

CMD-23h, 30h) will change accordingly. If the communication process can follow the

following flow: RF OK Signal OK Signal Fail RF Fail and the audio status

accordingly changes following the sequence of 0 1 0, the audio processor will

re-decode when the next communication is established. In some cases, the audio

processor cannot re-decode due to a variety of function combinations used and remain in

the fault condition. Therefore a decoding reset mechanism is needed to return to the

initial decode status and re-decode. There are two methods to implement a decoding

reset.

• Use a command to reset (I/O CMD: 10000). It is important to note that this command will overwrite the CLI data already written.

• Reset from the signal. Switch the PGA input source to VAG and increase the de-response delay time to put the audio processor back into a status of incorrect decoding, in which case the status register will change to zero. After this switch to the RX mode and detect the signal again. However the disadvantage of this method is the unavoidable delay time.

Another situation is an end-tone detection status of a sub-tone, CTCSS Anti-tone (I/O

CMD-30h[0]=1) or DCS Off-tone (I/O CMD-23h[1]=1). When a CTCSS Anti-tone is

decoded, I/O CMD-30h[0]=1, this status will be kept because of the independent

decoding function. Therefore the command “I/O CMD: 12000” must be executed to reset

the sub-tone end-tone detection function making I/O CMD-30h[0]=0 or I/O CMD-23h[1]=0.

This situation must be taken into consideration in program design, execute the command

when an end-tone is decoded.


AN0439E V1.00 20/39 December 11, 2016

Integrated Audio Functions In a public open wireless system such as for flight communication, when someone desires

to call a certain person or rejects the reception of an undesirable message, the Selective

Call function can be used to specify the desired communication object. When calling

someone the transmitter will first send the 2-tone or 5-tone specification Selective Call and

then the voice signal. Every receiver using the same frequency as the transmitter will

receive this wireless signal, decode the 2-tone or 5-tone data and execute a comparison. If

the Selective Call code decoded is the same as the receiver, its processor will activate the

speaker to allow the user to hear the voice message. In this way the communication

between the two sides is achieved. Additionally, the DTMF signal if used in the key

triggered message can transmit the data input by users to a decode application or a

selective call application. This device provides two main audio options, Selective Call and

DTMF, which include the ability to encode, transmit, receive and decode.

Selective Call Tone Setup The Selective Call Tone is a wave frequency analog signal. There are 16 tone numbers

meeting international standard specifications, EIA, EEA, CCIR, ZVEI 1, ZVEI 2, etc.

Users can also self-define a frequency channel in the range of 300Hz~3000Hz for more

flexible applications. This function is selected by setting I/O CMD-11h[4-2] = b'010. The

TX selective call tone number is assigned by I/O CMD-2Ah[3-0] and parameters for each

number tone are stored in two consecutive CLI CMD registers. For example, the

Selective_Call_0 parameters are located in CLI CMD-04E0h and 04E1h. All the Selective

Call tone numbers can be adjusted by the user program to generate the desired

frequency. When in the RX mode, the processor will detect the received signal frequency

and compare it with the data in CLI CMD-04E0h~04FFh. If the frequency matches a

certain tone number, the corresponding number will be stored in I/O CMD-2Eh[3-0] and

the status bit I/O CMD-23h[4] will be set high. Threshold setup should also be noted

when decoding. The Accepted Threshold which controls the acknowledged tone lowest

value is set by CLI CMD-0324h, and the Released Threshold which defines the deceased

tone high value is set by CLI CMD-0325h. An example is provided as follows:

Example: TX Mode, Output = MODO, Selective Call Tone = 00h.

• Selective Call TX Mode Setup Flow

SelCal TX

Command: 81E91h

Return

Y

Command: 81B92h

Command: 81148h

Command: 82A00h


AN0439E V1.00 21/39 December 11, 2016

Flow description:

<82A00>: Select the Selective Call tone number. Select to call the number 0 (Default EEA: 1981Hz).

<81E91>: Turn on the DAC1 and AMP1 circuits. DAC1 and AMP1 on – MODO output on.

<81B92>: Select PGA input source and audio output source. Select VAG as PGA input, DAC common-mode bias as audio output source to reduce noise, DAC1 as DAO1 input.

<81148>: Enter the TX mode. Select the TX mode and In-Band Tone = Selective Call.

Example: RX Mode, Input = DEMOD, Output = null, No Sub-tone.

• Selective Call Rx Mode Setup Flow

SelCal RX

Return

Save SelCal finder

Command: 92E00h

NIs SelCal event?

(23h[4] = 1)

Y

Command: 81B33h

Command: 81EC3h

NIs RSSI ok?

Y

Command: 81168h

IDLE mode

Flow description:


<81EC3>: Turn on the PGA circuit. PGA on – PGA input on.

<81B33>: Select PGA input source and audio output source. Select DEMOD as PGA input,

DAC common-mode bias as audio output source to reduce noise, DAC

common-mode bias as both DAO1 and DAO2 source.

<81168>: Enter the Rx mode. Select the Rx mode and In-Band Tone = Selective Call.

<Is Selective event>: Check whether this signal includes the frequency which matches a

certain Selective Call tone number.

<92E00>: Read the detected Selective Call tone number. Read the tone number stored

after this Selective Call is detected.

<Save SelCal finder>: Save the Selective Call tone number. Save the tone number

temporarily until the whole signal has been received. It can then

be used in the local device application if required.

<IDLE mode>: Enter the IDLE mode. Wait until the RSSI signal is acceptable.


AN0439E V1.00 22/39 December 11, 2016

DTMF Setup DTMF, Dual-Tone Multi-Frequency, is composed of a high frequency audio and a low

frequency audio. There are 16 groups of DTMF signals (0~D) which are usually used for

number or key tones in a telephone system. The DTMF tone is selected by setting I/O

CMD-11h[4-2]=b'100 and the TX tone number is set by I/O CMD-2Dh[3-0] which once

being assigned will select the corresponding frequency group. When in the RX mode, the

processor will detect the received signal frequency and compare it with the 16 frequency

groups. If the frequency matches a certain tone number, the corresponding number will

be stored in I/O CMD-2Fh[3-0] and the status bit I/O CMD-23h[5] will be set high. The

DTMF Power Threshold, which is set by CLI CMD-01C4h, is determined by the minimum

amplitude of the two frequencies. An example is provided as follows.

Example: TX Mode, Output = MODO, DTMF Tone = 00h.

• DTMF TX Mode Setup Flow

DTMF TX

Command: 81E91h

Return

Y

Command: 81B92h

Command: 81150h

Command: 82D00h

Flow Description:

<82D00>: Select the DTMF tone number. Select DTMF tone number 0.

<81E91>: Turn on the DAC1 and AMP1 circuit. DAC1 and AMP1 on – MODO output on.

<81B92>: Select the PGA input source and audio output source. Select VAG as the PGA

input, DAC common-mode bias as the audio output source to reduce noise

and DAC1 as the DAO1 input.

<81150>: Enter the TX mode. Select the TX mode and In-Band Tone = DTMF.

Example: Rx Mode, Input = DEMOD, Output = null, No Sub-tone.


AN0439E V1.00 23/39 December 11, 2016

• DTMF RX Mode Setup Flow

DTMF RX

Return

Save DTMF finder

Command: 92F00h

NIs DTMF event?

(23h[5] = 1)Y

Command: 81B33h

Command: 81EC3h

NIs RSSI ok?Y

Command: 81170h

IDLE mode

Flow description:



<81B33>: Select the PGA input source and audio output source. Select DEMOD as the

PGA input, DAC common-mode bias as the audio output source to reduce noise,

DAC Common-mode Bias as both the DAO1 and DAO2 sources.

<81170>: Enter the RX mode. Select the RX mode and In-Band Tone = DTMF.

<Is DTMF event>: Check whether this signal includes the frequency which matches a

certain DTMF tone number.

<92F00>: Read the detected DTMF tone number. Read the tone number after this DTMF

signal has been detected.

<Save DTMF Finder>: Save the DTMF tone number. Save the tone number temporarily

until the whole signal has been received which can then be used

in the local device application if required.

<IDLE Mode>: Enter the IDLE mode. Wait until the RSSI signal is acceptable.

Sub-Tone Function

In an open system such as walkie-talkie, the sub-tone mixing encoding method or

anti-interference code is developed because of tone number limitations. It allows the

additions of tone numbers for the same frequency thus extending the application flexibility.

The receiver should select the correct sub-tone type and tone number to decode the

signal correctly. The sub-tone function is helpful to reduce undesired signals and mutual

interference as well as solving the problem of tone number limit. The device provides two

mainstream sub-tone choices as follows.


AN0439E V1.00 24/39 December 11, 2016

CTCSS Setup The CTCSS tone is an analog signal implemented with a frequency in the range of

62.5Hz~254.1Hz. There are 51 standard tone numbers which are in accordance with

relevant specifications. An additional tone number for user self-definition is provided

adding flexibility for data protection. The CTCSS tone number selection is implemented

by I/O CMD-2Bh which is also used for the DCS tone number selection. The shared

command still means two register contents are used for the audio processor. Users

should take care when the contents of these registers are changed. When in the RX

mode, both polling (I/O CMD-23h[3]) and interrupt (10008 I/O CMD-23h[3]) methods

can be used to check whether the received signal matches the preset tone number.

Tone Number

CTCSS Freq. (Hz)

Tone Number

CTCSS Freq. (Hz)

Tone Number

CTCSS Freq. (Hz)

01h 67 12h 123 23h 225.7 02h 71.9 13h 127.3 24h 233.6 03h 74.4 14h 131.8 25h 241.8 04h 77 15h 136.5 26h 250.3 05h 79.7 16h 141.3 27h 69.3 06h 82.5 17h 146.2 28h 62.5 07h 85.4 18h 151.4 29h 159.8 08h 88.5 19h 156.7 2Ah 165.5 09h 91.5 1Ah 162.2 2Bh 171.3 0Ah 94.8 1Bh 167.9 2Ch 177.3 0Bh 97.4 1Ch 173.8 2Dh 183.5 0Ch 100 1Dh 179.9 2Eh 189.9 0Dh 103.5 1Eh 186.2 2Fh 196.6 0Eh 107.2 1Fh 192.8 30h 199.5 0Fh 110.9 20h 203.5 31h 206.5 10h 114.8 21h 210.7 32h 229.1 11h 118.8 22h 218.1 33h 254.1

CTCSS Frequency vs. Tone Numbers Table

The device supports 180° phase reversal. When in the TX mode, the anti-tone effect will

be generated when the I/O CMD-31h[0] bit changes from 1 to 0 or from 0 to 1. When in

the RX mode, the I/O CMD-31h[1] bit can be set to enable the anti-tone detection. If the

phase reversal is detected, the I/O CMD-30h[0] bit will change to 1. It is important to note

that the I/O CMD-30h[0] bit should be cleared to zero by the program. Refer to the Audio

Processor Status Reset section for more details. As the IRQ SPI data and CTCSS share

the same command, 10008h, if the CTCSS anti-tone detection function is used, both I/O

CMD-23h[3] and I/O CMD-30h[0] should be checked.


AN0439E V1.00 25/39 December 11, 2016

Event2 Control -- 31h Address

Bit 7 6 5 4 3 2 1 0

Name — — — — — — En_CTC

Rx_Anti-tone En_CTC

Tx_Anti-tone

Event2 Control Register

Event2 Status -- 30h Address

Bit 7 6 5 4 3 2 1 0 Name — — — — — — — CTC Anti-Tone Event

Event2 Status Register

Example: TX Mode, Input=MIC, Output=MODO&SMOD, Sub-tone=CTCSS, CTCSS

Tone=01h。

• CTCSS TX Mode Setup Flow

CTCSS TX

Command: 81E37h

Return

Y

Command: 81B10h

Command: 81142h

Command: 82B01h

Flow description:

<82B01>: Select sub-tone number. Select CTCSS number 1.

<81E37>: Turn on the DAC1, DAC2, AMP1, AMP2, MIC and PGA circuits. DAC1 and

AMP1 on – MODO output on, DAC2 and AMP2 on – SMOD output on, MIC on –

microphone circuit on, PGA on – PGA input on.

<81B10>: Select PGA input source and audio output source. Select MIC as the PGA input,

DAC common-mode bias as the audio output source to reduce noise.

<81142>: Enter the TX mode. Select the TX mode and Sub-tone = CTCSS.

Example: RX Mode, Input = DEMOD, Output = AUDO (source = DAC1), Sub-tone = CTCSS,

CTCSS tone=01h.


AN0439E V1.00 26/39 December 11, 2016

• CTCSS RX Mode Setup Flow

CTCSS RX

Return

Command: 81B25h

Command: 81E8Bh

NIs CTCSS event?

(23h[3] = 1)

Y

Command: 81B33h

Command: 81EC3h

NIs RSSI ok?

Y

Command: 81162h

IDLE modeCommand: 82B01h

Flow description:


<82B01>: Select sub-tone number. Select CTCSS number 1.


<81B33>: Select the PGA input source and the audio output source. Select DEMOD as the

PGA input, DAC common-mode bias as the audio output source to reduce noise.

<81162>: Enter the RX mode. Select the RX mode and Sub-tone = CTCSS.

<Is CTCSS event>: Check whether this signal includes the frequency which matches the

preset CTCSS sub-tone number.

<81E8B>: Turn on the DAC1, Buffer and PGA circuits. DAC1 on - DAC1 output on, AUDO

Output Buffer on – audio output circuit on, PGA on – PGA input on.


PGA input, DAC1 as the audio output source and the internal common-mode

bias as the DAC1 output pin source to avoid audio signal leakage on the MODO

pin.

DCS Setup The DCS tone is a digital carrier signal which is implemented by logic low and highs. A

DCS code has 23 bits in total including checking code and data code. There are 83×2

standard tone numbers which include the inverted DCS codes and an additional tone

number for user self-definition. This function is selected by setting I/O CMD-11h[1-0] =

b’01. The TX encoding tone number is selected by I/O CMD-2Bh[6-0] which is also used

for the CTCSS tone number selection. The DCS code is set by CLI CMD-04DCh (DCS

code bit0~bit15) and CLI CMD-04DDh (DCS code bit16~bit22). Before communication is

finished, an off-tone of about 200ms~300ms will be transmitted, which is implemented by


AN0439E V1.00 27/39 December 11, 2016

setting I/O CMD-2Bh[6-0] = h’7F. A self-defined DCS code is set by CLI CMD-04DCh and

CLI CMD-04DDh if needed, in which case the I/O CMD-2Bh[6-0] bits must be set to h’00.

Two important points must be noted. First, the data will be inverted, second, the data is

transmitted with MSB first. In the following example, if the DCS code is 1BF1C8h, the

waveform observed is 763813h as the LSB of the inverted code is first sent.

• 1BF1C8h = 001, 1011, 1111, 0001, 1100, 1000

• Inverted code = 110, 0100, 0000, 1110, 0011, 0111

• Waveform observed by oscilloscope (The LSB of the inverted code is on the left and is converted last) = (Fore) 1110, 1100, 0111, 0000, 0010, 011

7 6 3 8 1 3

When in the RX mode, the received DCS code is checked based on the preset value in

I/O CMD-2Bh. If a correct code is decoded, a DCS event will be declared by its polling bit

(I/O CMD-23h[2]) or by interrupt (10004 I/O CMD-23h[2]), and in some systems an

DCS turn off tone event (I/O CMD-23h[1]) will also be declared to indicate that the audio

output has ended. The relevant setup is shown as follows.

Tone Number

DCS Code

Tone Number

DCS Code

Tone Number

DCS Code

Tone Number

DCS Code

Inverted Tone

Number DCS Code

Inverted Tone

Number DCS Code

Inverted

01h 023 1Dh 174 39h 445 81h 023 9Dh 174 B9h 445

02h 025 1Eh 205 3Ah 464 82h 025 9Eh 205 BAh 464

03h 026 1Fh 223 3Bh 465 83h 026 9Fh 223 BBh 465

04h 031 20h 226 3Ch 466 84h 031 A0h 226 BCh 466

05h 032 21h 243 3Dh 503 85h 032 A1h 243 BDh 503

06h 043 22h 244 3Eh 506 86h 043 A2h 244 BEh 506

07h 047 23h 245 3Fh 516 87h 047 A3h 245 BFh 516

08h 051 24h 251 40h 532 88h 051 A4h 251 C0h 532

09h 054 25h 261 41h 546 89h 054 A5h 261 C1h 546

0Ah 065 26h 263 42h 565 8Ah 065 A6h 263 C2h 565

0Bh 071 27h 265 43h 606 8Bh 071 A7h 265 C3h 606

0Ch 072 28h 271 44h 612 8Ch 072 A8h 271 C4h 612

0Dh 073 29h 306 45h 624 8Dh 073 A9h 306 C5h 624

0Eh 074 2Ah 311 46h 627 8Eh 074 AAh 311 C6h 627

0Fh 114 2Bh 315 47h 631 8Fh 114 ABh 315 C7h 631

10h 115 2Ch 331 48h 632 90h 115 ACh 331 C8h 632

11h 116 2Dh 343 49h 654 91h 116 ADh 343 C9h 654

12h 125 2Eh 346 4Ah 662 92h 125 AEh 346 CAh 662

13h 131 2Fh 351 4Bh 664 93h 131 AFh 351 CBh 664

14h 132 30h 364 4Ch 703 94h 132 B0h 364 CCh 703

15h 134 31h 365 4Dh 712 95h 134 B1h 365 CDh 712

16h 143 32h 371 4Eh 723 96h 143 B2h 371 CEh 723

17h 152 33h 411 4Fh 731 97h 152 B3h 411 CFh 731

18h 155 34h 412 50h 732 98h 155 B4h 412 D0h 732

19h 156 35h 413 51h 734 99h 156 B5h 413 D1h 734

1Ah 162 36h 423 52h 743 9Ah 162 B6h 423 D2h 743

1Bh 165 37h 431 53h 754 9Bh 165 B7h 431 D3h 754

1Ch 172 38h 432 9Ch 172 B8h 432

DCS Code vs. Tone Numbers Table


AN0439E V1.00 28/39 December 11, 2016

Example: TX Mode, Input=AUX, Output=MODO&SMOD, Sub-tone=DCS, DCS tone=01h.

• DCS TX Mode Setup Flow (1) TX DCS Signal

DCS TX

Command: 81E33h

Return

Y

Command: 81B50h

Command: 81141h

Command: 82B01h

(2) An Off_tone following the DCS Signal

N

DCS TX Off_tone

Delay 200ms

Return

Y

Command: 82B7Fh

Command: 81161h

Flow description (1):

<82B01>: Select sub-tone number. Select DCS number 1.

<81E33>: Turn on the DAC1, DAC2, AMP1, AMP2 and PGA circuits. DAC1 and AMP1 on –

MODO output on, DAC2 and AMP2 on – SMOD output on, PGA on – PGA input

on.

<81B50>: Select PGA input source and the audio output source. Select AUX as PGA input,

DAC common-mode bias as audio output source to reduce noise.

<81141>: Enter the TX mode. Select the TX mode and Sub-tone=DCS.

* * * After the DCS signal is transferred * * *


<82B7F>: Select off-tone. Select the off-tone number to generate a 134Hz signal.

<81101>: Return to the IDLE mode. After this DCS transmission has finished, return to the

wait status.


AN0439E V1.00 29/39 December 11, 2016

Example: RX Mode, no audio tone signal, DCS sub-tone, AUDO source = DAC1, DAC2

off, MIC off, DCS tone=01h. This example is implemented using an IRQ. When the DCS

event interrupt has been received, an additional command is executed to read I/O

CMD-23h to check the event status.

• DCS RX Mode Setup Flow (1) RF Signal Detection

DCS RX Setting

Return

Command: 81161h

Command: 81EC3h

Command: 82B01h

NIs RSSI ok?Y

Command: 81B33h

IDLE mode

(2) Audio Processor IRQ Processing

N

Audio Processor IRQ

Is Data = 10004?(23h[2] = 1)

Return

Y

Command: 92300h Other status processing

(3) Turn on and output AUDO signal

N

DCS RX

Is DCS event?(23h[2] = 1)

Return

Y

Command: 81B25h

Command: 81E8Bh


AN0439E V1.00 30/39 December 11, 2016



<82B01>: Select sub-tone number. Select DCS number 1.


<81B33>: Select the PGA input source and the audio output source. Select DEMOD as P

the GA input, DAC common-mode bias as the audio output source to reduce

noise.

<81161>: Enter the RX mode. Select the RX mode and Sub-tone=DCS.


<Is Data = 10004>: Check whether this signal includes the frequency which matches the

preset DCS sub-tone number.

<92300>: Poll the event status again to check DCS event status is 1 or 0.


<Is DCS event>: Check whether this signal includes the frequency which matches the

preset DCS sub-tone number.

<81E8B>: Turn on the DAC1, Buffer and PGA circuits. DAC1 on – DAC1 output on, AUDO

Output Buffer on – audio output circuit on, PGA On – PGA input on.


PGA input, DAC1 as the audio output source and the internal common-mode

bias as DAC1 output pin source to avoid audio signal leakage on the MODO

pin.

Audio Advanced Functions

The device provides multiple audio processing functions including scrambler, compandor,

emphasis, HPF, LPF, etc., which are used according to different application requirements.

These functions are controlled by I/O CMD-2Ch[7-2]. There are some restrictions on the

function combination when in the TX and RX mode depending on different audio

processor operating frequencies.

Audio Control -- 2Ch Address

Bit 7 6 5 4 3 2 1 0

Name EN_Scram EN_Comp EN_Emp EN_NBW EN_WBW EN_HPF300 EN_VOX EN_AGC

Advanced Audio Processor Control Register


AN0439E V1.00 31/39 December 11, 2016

Audio – Low Pass/High Pass Filters Setup In a communication system, the data to be transmitted or received may be damaged due

to the nearby channel signal interference and channel noise, in which case filters can be

used to improve the problem. The device provides wide band-width (3.0kHz) and narrow

band-width (2.55kHz) low pass filters as well as a 300Hz high pass filter, to filter out the

sub-tone and remove the signals from other channels. These filters are controlled by I/O

CMD-2Ch[4-2], as shown below.

• Turn on 12.5kHz LPF & 300 HPF Flow

Done

Master

Command: 82C14h

Flow description: <82C14>: Set data 14h. 2Ch[4]=1 to turn on the 12.5kHz LPF, 2Ch[2]=1 to turn on the

300Hz HPF.

Audio – Pre-emphasis/De-emphasis Setup The emphasis function is used for power spectrum density promotion and demotion for

high and low frequencies respectively, obtaining a more regular power spectrum density

distribution and resulting in a better S/N ratio. For a typical signal, the power spectrum

density of its high frequency part presents a declining trend where its noise rapidly

increases with increasing frequency, resulting in an undesirable relative S/N ratio.

Therefore the emphasis function, which is controlled by I/O CMD-2Ch[5] as shown below,

can be implemented to improve the problem.

• Turn on Emphasis Flow

Done

Master

Command: 82C20h

Flow description: <82C20>: Set data 20h. 2Ch[5]=1 to turn on the emphasis function.

Audio – Scrambler/De-scrambler Setup The scrambler function, as a cryptographic method, works by inversing the transmitted

audio frequencies. In the TX mode, signals processed using the scrambler are less

susceptible to re-use after interception during transmission. In the RX mode, a

de-scrambler is used to convert the received scrambled signals back to their original

audio frequency content. The device provides eight scrambler inverse frequencies which

are set by CLI CMD-013Ah and 013Bh. To change the scrambler inverse frequency, the

scrambler function should first be turned off. After the desired inverse frequency has been

set the scrambler function can be turned on again to complete the change. The scrambler

function is controlled by I/O CMD-2Ch[7].


AN0439E V1.00 32/39 December 11, 2016

• Turn on Scrambler Flow

Done

Master

Command: 82C80h

Flow description: <82C80>: Set data 80h. 2Ch[7]=1 to turn on the scrambler function.

• Change Scrambler Inverse Frequency (3200Hz) Flow

Master

Command: 14082h

Return

Y

Command: 1013Ah

Command: 19871h

Command: 82C00h

Command: 1013BhY

Command: 14B3Eh

Command: 82C80h

Command: 14082h

Flow description:

<82C00>: Set data 00h. 2Ch[7]=0 to first turn off the scrambler function.

<14082>: CLI write identifier code. To implement the CLI command write operation, this

command should first be executed. There is no data reply after this step.

<1013A>: Select register 013A. Select the register to be written with data. There is no

data reply after this step.

<19871>: Set data 9871h. Write data to the register. There will be a reply of 14000 if the

data has been correctly written. Otherwise the write operation will have failed.

<14082>: CLI read identifier code. To implement a CLI command read operation, this

command should first be executed. There is no data reply after this step.

<1013B>: Select register 013B. Select the register to be written with data. There is no

data reply after this step.

<14B3E>: Set data 4B3Eh. Write data to the register. There will be a reply of 14000 if the

data has been correctly written. Otherwise the write operation will have failed.

<82C80>: Set data 80h. 2Ch[7]=1 to turn on the scrambler function.

Audio – Compandor (Compressor/Expander) Setup The compandor is used to reduce the dynamic range by compressing or expanding the

signals. The supported dynamic range is 60dB for the input voltage and 30dB for the

output voltage. The compressor ratio value is 0.5 for MIC in. In the wireless transmission

process, the received RF signals will certainly include some noise, therefore the signals

are compressed according to the preset ratio before being transmitted. The received

signals will be expanded with the same ratio and then recovered to their original content.

In this way most of the non-original RF signals can be removed after expansion,

effectively reducing noise in the output unit. The compandor threshold voltage is set by


AN0439E V1.00 33/39 December 11, 2016

CLI CMD-012Ah (TX mode) and CLI CMD-012Bh (RX mode). The compandor threshold

values for the TX mode and RX mode are different even under the same change point.

For example, under a 100mV change point, a 1V signal transmitted in the TX mode will

be 550mV when it is measured on the MODO pin, while a 1V signal received in the RX

mode will be recovered to 1900mV. It is important to note that the signal after

compression should not exceed the limiter value. The compandor is controlled by I/O

CMD-2Ch[6] as shown below.

• Turn on Compandor Flow

Done

Master

Command: 82C40h

Flow description: <82C40>: Set data 40h. 2Ch[6]=1 to turn on the compandor.

Baseband Signal level Modulation Function

In different application systems, the supported output modulation levels will also be

different. This device provides multiple modulation levels for different paths as well as a

mixer circuit, as shown in the following diagram.

In Band Tone(VR1)

Voice

MUX VR4

Mixed(VR3)

VR5Sub Audio

Tone(VR2)

Limiter DAC1

MODO

AUDO

DAC2 SMOD

Modulation Path Block Diagram

• VR1: In-band tone (I/O CMD-11h[4-2: b’010]) modulation level selection. 256 levels, default value: 00h.

• VR2: Sub-tone modulation level selection. 256 levels, default value: 00h.

• VR3: Mixer selection and modulation level setup. When VR3=0, the mixer is not used. 256 levels, default value: 00h.

• VR4: MODO pin baseband audio output modulation level selection. 1024 levels, default value: 3FFh.

• VR5: SMOD pin sub-tone output modulation level selection. 1024 levels, default value: 3FFh.


AN0439E V1.00 34/39 December 11, 2016

The MODO output is determined by VR1 (if the in-band tone generator is used), VR4 and

the system operating voltage. The SMOD output is determined by VR2, VR5 and the

system operating voltage. But there will be some loses regarding the actual

measurement result of the output due to the RC filter, etc. For example, in a 3V system,

MODO Output (max.) ≈ 2780mV and SMOD Output (max.) ≈ 1920mV. Since the audio

processor has a set of default configurations, the desired modulation circuits should be

turned on and then change the modulation level manually according to the actual

application requirements.

Regarding the high frequency modulation mechanism, the CTCSS tone and DCS tone

are input separately when in the TX mode, so that the DCS digital signal that changes

rapidly between high and low can be effectively processed. In this device the CTCSS tone

and DCS tone are output on the same pin, SMOD. A mixed mechanism is designed

allowing the modulated DCS tone to be output on the MODO pin. Usually the CTCSS

sub-tone is output on the SMOD pin, in which case VR3 is off (CLI CMD-04D2h=0000h)

and the CTCSS signal is determined by VR2 and VR5. While the DCS sub-tone is mixed

in the audio signal and is output on the MODO pin, in which case VR3 is on with a certain

ratio, VR5 is off (CLI CMD-04D5h=0000h) or DAC2 is off, and the DCS signal is

determined by VR2 and VR3. The TX DCS function can be effectively used in such a way

to implement associated applications. However, whether this function can be applied to

user systems depends on actual application situations.

Example: Operating voltage=3V, configure and turn on the maximum modulation level for

the sub-audio path, VR5=default value (3FFh).

• Sub-audio Path Modulation Level Setup Flow

Master

Return

Write message ok= VR2 is turn on & level:256

NIs reply 14000h?Y

Command: 104CBh

Command: 14082h

Command: 100FFh

Write message fail

Flow description: <14082>: CLI write identifier code. <104CB>: Select register 04CB. <100FF>: Set data 00FFh. VR2=FFh to turn on the maximum modulation level for VR2. <Is reply 14000>: Audio processor write response.


AN0439E V1.00 35/39 December 11, 2016

Voice Control Function – VOX The VOX function is used for some special applications. This function uses the VOX high

level threshold (CLI CMD-04CDh) and low level threshold (CLI CMD-04CEh) to

determine whether the input signal is larger than the high level threshold (I/O

CMD-29[1-0]=02h) or less than the low level threshold (I/O CMD-29[1-0]=01h). The VOX

function is controlled by I/O CMD-2Ch[1].


Bit 7 6 5 4 3 2 1 0 Name EN_Scram EN_Comp EN_Emp EN_NBW EN_WBW EN_HPF300 EN_VOX EN_AGC

VOX Selection Register

High threshold

Low thresholdSignal

I/O command:23h = No event29h = 00h

I/O command:23h = 01h29h = 01h

I/O command:23h = 01h29h = 02h

I/O command:23h = No event29h = 00h

VOX Status Detection Chart

To use this function, first configure to operate in the SLOW Mode reducing the audio

processor operating frequency from 24.576MHz to 6.144MHz, and turn off unnecessary

circuits such as output circuits to achieve the lowest power consumption. When the input

signal is acknowledged, enter the TX mode to continue to transmit messages, as

described below.

• Turn on VOX Flow (1) Setup VOX and Slow Mode

VOX Setting

Command: 81B10hY

Command: 81120h

CTRL2[7~6]=00b

Command: 81EC7h

Done

CTRL2[5]=1b

Command: 82C02h


AN0439E V1.00 36/39 December 11, 2016

(2) VOX Signal Status Detection

VOX procedure

N

Is above VOX highThreshold (29h = 02h)?

N Is VOX event(23h = 01h)?

YCommand: 92900h

CTRL2[5]=0b

CTRL2[7~6]=11b

Continue TX Control flow

Done

Command: 81160h(Back RX mode)

Y

Is below VOX lowThreshold (29h = 01h)?

N

Y


<81EC7>: Turn on the MIC and PGA circuits. MIC on – microphone circuit on, PGA on –

PGA input on.

<81B10>: Select the PGA input source and the audio output source. Select MIC as the

PGA input, DAC common-mode bias as the audio output source to reduce

noise.

<81120>: Set to operate in the Slow Mode.

<CTRL2[7-6]=b’00> & <CTRL2[5]=b’1>: Configure the audio processor to operate at the

lowest frequency of 4MHz.

<82C02>: Set data 02h. 2Ch[1] = 1 to turn on the VOX function.


<Is VOX event>: Check whether a VOX event has occurred.

<92900>: VOX High/Low Threshold Status. Read VOX data compare result. If

29h[1-0]=b’10 which indicates the input signal is larger than the high threshold,

the VOX event is acknowledged. Otherwise if 29h[1-0]=b’01 which indicates the

input signal is less than the low threshold, the VOX event is invalid.

<CTRL2[7-6]=b’11> & <CTRL2[5]=b’0>: Configure the audio processor to operate at the

highest frequency of 16MHz (assume that it is the original value).

<Contiune Tx…>: Enter the TX control flow.


AN0439E V1.00 37/39 December 11, 2016

Automatic Gain Control – AGC

Usually the output voice quality is unstable due to the MIC input source volume changes,

in which case an additional AGC circuit is required to resolve this problem. This usually

results in increased cost and increased circuit area. However this device includes an

integrated AGC function which together with the MIC internal OP gain configurations

implements the automatic gain control function internally. The AGC function is controlled

by I/O CMD-2Ch[0].


Bit 7 6 5 4 3 2 1 0

Name EN_Scram EN_Comp EN_Emp EN_NBW EN_WBW EN_HPF300 EN_VOX EN_AGC

AGC Selection Register

• Turn on AGC Flow

Done

Master

Command: 82C01h

Flow description: <82C01>: Set data 01h. 2Ch[0] = 1 to turn on the AGC function.

Example: Select an OP gain under the voltage of 3.3V. (Standard: MIC=16rms)

Solution:

• Step 1: AD range (max.): 3.3×0.7 = 2310mV

• Step 2: Input source: 16rms × (2 /√2) = 45.3mV

• Step 3: Rule: 2310 ≥ 45.3 × 8 × C (8 = PGA max. gain, C = OPA max. gain)

→ C = 6.37

• Step 4: Calculate the OPA resistances: R2 / R1 = 6.37

→ If R1 = 10K → R2 = 62K

AGC Application Circuit @3.3V:

MIC and Driver Circuit


AN0439E V1.00 38/39 December 11, 2016

Audio Processor Function Combination Below is provided the list of the HT98F069 audio processor supported functional

combinations - fAP=24.576MHz

• RX Max. Functional Combination Capability Table

Sub-audio Voice Band De-scrambler Compandor De-emphasis LPF HPF

CTCSS

Audio Band tone √ √ √ √ √

DTMF √ √ √ √ √

Selective Call √ √ √ √

DCS


DTMF √ √ √ √ √


VOX √ √

• TX Max. Functional Combination Capability Table

Sub-audio Voice Band Scrambler Compandor Emphasis LPF HPF

CTCSS

Audio Band Tone √ √ √ √ √

DTMF √ √ √ √ √


DCS


DTMF √ √ √ √ √


“fAP”: Audio processor system frequency.

CTCSS: Either CTCSS or User-defined CTCSS.

DCS: Either DCS, reversed DCS or User-defined DCS.

Selective Call: Either Selective Call or User-tone.

Compandor: Expander for RX mode or compressor for TX mode.

Parameter Setup The audio processor audio generation, threshold values, variable values, drop time,

limiter values are allowed to be modified according to the actual application requirements.

The required parameters can be configured using the attached application program.

• Use HT98F069App_v1.exe to generate the desired parameters.

Conclusion

This application note has summarised some considerations and advice regarding using

the HT98F069 for wireless walkie-talkie applications. Together with the provided audio

processor basic and advanced functions as well as related flowcharts, the application

note should assist users to understand the operating principles and allow easier use of

the device.


AN0439E V1.00 39/39 December 11, 2016

Versions and Modification Information

Date Author Issue

2016.09.02 陳志強 First Version

Reference File

Reference file: HT98F069 datasheet.

For more information refer to the Holtek’s official website http://www.holtek.com.tw.

Disclaimer All information, trademarks, logos, graphics, videos, audio clips, links and other items

appearing on this website ('Information') are for reference only and is subject to change at

any time without prior notice and at the discretion of Holtek Semiconductor Inc.

(hereinafter 'Holtek', 'the company', 'us', 'we' or 'our'). Whilst Holtek endeavors to ensure

the accuracy of the Information on this website, no express or implied warranty is given

by Holtek to the accuracy of the Information. Holtek shall bear no responsibility for any

incorrectness or leakage.

Holtek shall not be liable for any damages (including but not limited to computer virus,

system problems or data loss) whatsoever arising in using or in connection with the use of

this website by any party. There may be links in this area, which allow you to visit the

websites of other companies. These websites are not controlled by Holtek. Holtek will

bear no responsibility and no guarantee to whatsoever Information displayed at such sites.

Hyperlinks to other websites are at your own risk.

Limitation of Liability In any case, the Company has no need to take responsibility for any loss or damage

caused when anyone visits the website directly or indirectly and uses the contents,

information or service on the website.

Governing Law This disclaimer is subjected to the laws of the Republic of China and under the jurisdiction

of the Court of the Republic of China.

Update of Disclaimer Holtek reserves the right to update the Disclaimer at any time with or without prior notice,

all changes are effective immediately upon posting to the website.

http://www.holtek.com.tw/

HT98F069 Two-way Radio Flash MCU Application GuidelinesHT98F069 Two-way Radio Flash MCU Application...

Documents

Transcript of HT98F069 Two-way Radio Flash MCU Application GuidelinesHT98F069 Two-way Radio Flash MCU Application...