Hsing-Chih Chang Chien

Hung-Chih Ou

Tung-Chieh Chen

Ta-Yu Kuan

Yao-Wen Chang

Double Patterning Lithography-Aware Analog Placement

Outline

Introduction DPL conflict handling The algorithm flow Experimental results Conclusions

Introduction

DPL decompose patterns of a layer into two sub-patterns and

then use two masks to manufacture the two sub-patterns

DPL conflict Two patterns separated by the distance less than Smin

belong to the same mask.

Analog Placement Problem

Previous Works corner stitching compliant B*-tree (CB-tree) [14]

DPL is not considered in previous works.

Analog designers usually reduce mismatches by predefining masks (colors)

Preliminaries

For constraint-driven analog placement, CB-tree is the most effective and efficient topological representation with module adjacency information

Review of Corner Stitching Corner stitching is a data structure for representing

non-overlapping rectangular modules in a two-dimensional plane (called tile plane).

Analog Constraints

Symmetry constraints are use to place some pairs of modules symmetrically

along a vertical or a horizontal symmetry axis. It can reduce mismatches of sensitive modules.

Proximity constraints are use to place modules at closest proximity to reduce

process variation.

Problem Formulation

Rectangular modules M = {mk|1 ≤ k ≤ |M|} Nets N = {nk|1 ≤ k ≤ |N|} Placement Constraints S = {sk|1 ≤ k ≤ |S|} Pre-coloring Constraints R = {rk|1 ≤ k ≤ |R|}

Place all modules in M to minimize the total area, wirelength, and DPL conflict

DPL conflict handling

Resolving an analog placement with DPL conflicts. extended conflict graph(ECG) to model the global

relationship among patterns/modules.

Module Flipping

Extended Conflict Graph (ECG)

The traditional conflict graph considers the information from a fixed layout.

Since a poly can only be placed vertically, there are only two choices for module orientations: non-flipped and flipped.

Basic Integer Linear Programming (ILP) Formulation

ILP Problem-Size Reduction

Connected Component Computation Two-Edge-Connected Component Computation

identify a bridge

The algorithm flow

Perturbation

In stage 1 & 3

In stage 2

The Three-Stage Placement Flow

Tile Plane Updating to create new tiles and update the corner stitches to

record the neighbors for each tile.

Experimental results

C++ programming language. Intel Xeon X5647 2.93GHz Linux workstation with

48GB memory. CPLEX12.3 [1] library to solve the ILP problems. Two industrial analog circuits Case1 and Case2.

Conclusions

DPL-aware analog placement flow to simultaneously minimize area, wirelength, and DPL conflicts.

Propose an extended conflict graph (ECG). Develop an ILP algorithm considering symmetry and

pre-coloring constraints to minimize conflicts. A three-stage flow.