Hsabaghianb @ kashanu.ac.ir Microprocessors 1- 1 University of Kashan Department of Computer...

hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir MicroprocessorsMicroprocessors 11- - 11

University of KashanDepartment of Computer Engineering

MicroProcessors&

MicroControlers

H. Sabaghian B.Spring 2006


Text Books

Microcontroller 8051Author: Mohammad ali Mazidi Translator: Dr. Sepidnam

The 8051 MicrocontrollerAuthor: Iscott Makenzi

Translator: Dr. Seyed RaziEdition : 3


Lec note 1

Introduction


outline

MicroprocessorMicro-computerMicrocontroller3_Bus (Data, Address, Control)I/OMemory


Microprocessor (µP)(MPU)µP = CPU on a single chip Components of CPU

Registers: Temporary storage locations for

program instruction or data.

The Arithmetic Logic unit (ALU): performs

both arithmetic and logical operations

Timing and Control Circuits: keeps all

working together in the right time sequence

Bus: n_bit (internal) path for data exchange


Microprocessor Microprocessor=µP=MPU Tasks

processing data controlling all components make µP the µComputer system

µP executes instructions in memory Fetch, Decode, Execute


Microcomputers Micro-computer (µ-Computer) small computer specifically for data acquisition and control applications


Microcomputers

All Microcomputers consist of (at least) : Microprocessor Unit (µP) Program Memory (ROM) Data Memory (RAM) Input / Output ports (IO) Bus System (External) (and Software)

MPU is the brain of microcomputer


The Input/Output (I/O) System

I/O links MPU to outside world.

Input port : a circuit through which an external device can send signals (data?) to the MPU.

Output port is a circuit that allows the MPU to send signals (data?) to external devices.

I/O ports connect both digital and analogue devices by DAC and ADC


Bus A common communications pathway that carry

information between the various elements of system

The term BUS refers to a group of wires or conduction tracks on a printed circuit board (PCB)

though which binary information is transferred

Subsystems are connected through BUS together


3_Bus

There are three main bus grouPs ADDRESS BUS DATA BUS CONTROL BUS


Data Bus

The Data Bus carries the data which is transferred throughout the system. ( bi-directional)

Examples of data transfers Program instructions being read from memory into MPU. Data being sent from MPU to I/O port Data being read from I/O port going to MPU Results from MPU sent to Memory

These are called read and write operations


Address Bus

Address = binary number that identifies a specific memory storage location or I/O port involved in a data transfer

Address Bus = pathway transmit address to memory or I/O port.

Address Bus is unidirectional (one way): addresses are always issued by the MPU


Control Bus

Control Bus = grouP of control signals Control signals are unidirectional, and are

mainly outputs from the MPU.

provide synchronization (timing control) between MPU and other components.

ExampleRD: (read signal) read data into MPUWR: (write signal) write data from MPU


Main memory Memory

Stores programs Provides data to the MPU Accepts result from the MPU for storage

Main memory Types ROM : read only memory. Contains program

(Firmware). does not lose its contents when power is removed (Non-volatile)

RAM: random access memory (read/write memory) used as variable data, loses contents when power is removed volatile. When power up will contain random data values


Read-Only Memory

µP can read instructions from ROM quickly

Cannot write new data to the ROM

ROM remembers the data, even after power cycled

When power is turned on, the microprocessor will start fetching instructions from ROM (bootstrap )


Available ROMs Masked ROM or just ROM PROM or programmable ROM(once only) EPROM (erasable via ultraviolet light) =UVROM Flash

re-writable about 10000 times usually must write a whole block not just 1 or 2

bytes, slow writing fast reading

EEPROM (electrically erasable ROM) fast writing slow reading can program millions of times useless for storing a program good for save configuration information.


ROMA0

A1

A2

Am

D0

Dn

D1

D2

OECE

n+1 bitData

12 mCapacity :

m+1 bitAddress

OE : Output Enable connect to RD of µP

)(CSCE : Chip Enableto Address decoder

)1(2 1 nm

ROMPROM

EEPROM


ROM Read Timing

CE

A0-Am

D0-Dn

OE falls to data valid

Addr valid to data valid

OE


27XX EPROMU1

2716

87654321232219

1820

21

910111314151617

A0A1A2A3A4A5A6A7A8A9A10

CEOE

VPP

O0O1O2O3O4O5O6O7

16 kbit2 kbyte

U2

2732

8765432123221921

1820

910111314151617

A0A1A2A3A4A5A6A7A8A9A10A11

CEOE/VPP

O0O1O2O3O4O5O6O7

32 kbit4 kbyte

U3

2764

109876543252421232

1112131516171819

2227

1

20

A0A1A2A3A4A5A6A7A8A9A10A11A12

O0O1O2O3O4O5O6O7

OEPGM

VPP

CE

64 kbit8 kbyte

PGM and VPP are used to programming


27XXX EPROM

U4

27128

10987654325242123226

1

1112131516171819

20

2227

A0A1A2A3A4A5A6A7A8A9A10A11A12A13

VPP

D0D1D2D3D4D5D6D7

CE

OEPGM

U5

27256

1098765432524212322627

2022

1

1112131516171819

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14

CEOE

VPP

D0D1D2D3D4D5D6D7

U6

27512

10987654325242123226

2022

27

28

1

1112131516171819

A0A1A2A3A4A5A6A7A8A9A10A11A12A13

CEOE/VPP

A14

VCC

A15

O0O1O2O3O4O5O6O7

U7

27010

12111098765272623254282932

1314151718192021

2431

1

22

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16

D0D1D2D3D4D5D6D7

OEPGM

VPP

CE

128 kbit16 kbyte

256 kbit32 kbyte

512 kbit64 kbyte

1024 kbit128 kbyte


28256

109876543252421232261

1112131516171819

28

20

2227

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14

D0D1D2D3D4D5D6D7

VCC

CE

OEWE

256 kbit32 kbyte

2864

20

22

28

109876543252421

27

1112131516171819

232

1

CE

OE

VCC


WE

I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7

A11A12

RDY/BUSY

64 kbit8 kbyte

28010

12111098765272623254282932

1314151718192021

32

22

2431


D0D1D2D3D4D5D6D7

VCC

CE

OEWE

1026 kbit128 kbyte

28040

12111098765272623254282932

1314151718192021

32

301

22

2431


D0D1D2D3D4D5D6D7

VCC

A17A18

CE

OEWE

4096 kbit512 kbyte

2816

18

20

24

87654321232219

21

910111314151617

CE

OE

VCC


WE

I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7

16 kbit2 kbyte

28XX E2PROM


RAM (Random Access Memory)

µP can read the data from RAM quickly µP can write new data to RAM quickly RAM forgets its data if power is turned offTwo type is available :

Static RAM(SRAM): ff base, fast, expensive, low cap/vol, applied for cache , no refresh

Dynamic RAM (DRAM): cap base, slow , low cost high capacity/volume , applied for main memory(pc) need refresh.


RAM(Static)A0

A1

A2

Am

D0

Dn

D1

D2

RDWR

n+1 bitData

12 mCapacity :

m+1 bitAddress

CS: Chip Select to Address decoder

)1(2 1 nm

RAM

CS

RD: Read signal connect to MemRD of µP

WR: Write signal connect to MemWR of µP

Data bus isBidirectional


Static RAM


Dynamic RAM


Dynamic RAM

Write : Charge bitline HIGH or LOW and set wordline HIGH

Read : Bit line is precharged to a voltage halfway between HIGH and LOW and then the word line is set HIGH.

Sense Amp Detects change

Reads are destructive (Must follow with a write)

Address Buffer

Hsabaghianb @ kashanu.ac.ir Microprocessors 1- 1 University of Kashan Department of Computer...

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