Homework 2, Summer 2000 Page 1 ECE/CS/352

Department of Electrical and Computer Engineering University of Wisconsin - Madison

ECE/Comp Sci 352 Digital System Fundamentals

Homework #2 (Solution 2000)

1). (Code Converters/Logic Synthesis) Book Problem 3-11.

2). (Decoders) Book Problem 3-14.

3). (Decoders) Book Problem 3-17. (Hint: Use a 3-line to 1-of-8 decoder).

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4). (Encoders) Book problem 3-20.

5). (Multiplexers) Book Problem 3-24.

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6). (Multiplexer/Adder) Book Problem 3-27. Also, using one inverter, implement a full adder with a dual 4-to-1 multiplexer.

7). (Adders) Book Problem 3-34.

8) (Carry Look-ahead Adders) A four-bit carry look-ahead adder circuit is implemented as shown in Figure 3-29, Page 130. Use two 4-bit stages of these circuits and any external logic needed to implement an 8-bit adder with: a). Ripple carry through the upper, 4-bit stage. Draw the diagram. (Hint: use c4 to stage 2)

Answer: Connect up all data lines as shown. Connect C4 (Cary out) from the first stage to C0 (Carry in) of the second stage. GG = Group Generate (G(0-3) in book). GP = Group Propagate.(P(0-3) in the book).

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b). A second level carry-lookahead generator. Draw the diagram.

ANSWER: Carry in to the second stage is G(0-3) + P(0-3)•C(0).

9) (1 and 2's complement) Book Problem 3-38.

0123 0123

4-BIT ADDER

- A - - B -

0123- SUM -

C4 C0

GPGG

0123 0123

4-BIT ADDER

- A - - B -

0123- SUM -

C4 C0

GPGG

C(0)C(8)

0123 0123

4-BIT ADDER

- A - - B -

0123- SUM -

C4 C0

GP GG

0123 0123

4-BIT ADDER

- A - - B -

0123- SUM -

C4 C0

GP GG

A(7)A(6)A(5)A(4)

B(7)B(6)B(5)B(4)

A(3)A(2)A(1)A(0)

B(3)B(2)B(1)B(0)

S(3)S(2)S(1)S(0)

S(7)S(6)S(5)S(4)

C(0)C(8)

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10) (Unsigned subtraction) Book Problem 3-39.

11) (Signed 2's complement) Book Problem 3-40

12) (Signed 2's complement) Book Problem 3-41.

13). (Adder/Subtractor) Book Problem 3-45.

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14). (Multiplier) Book Problem 3-46

15) (9's Complement) Book Problem 3-49.

16) (Verilog Description) Book Problem 3-72

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17). (Basic Latches SR) Book problem 4-1, page 240.

18). (Basic Latches D-type) Book problem 4-3, page 240.

19). (Edge Triggered D-type) Hand simulate the behavior of the basic edge-triggeed D Flip Flop shown in book Figure 4-10.

20). (Master-Slave Flip Flop) [Required as part of Project Part 1] Figure 4-7 in Mano and Kime shows a basic gated SR Latch. Figure 4-10 uses two gated SR latches and an inverter to form a SR Master-Slave flip-flop. Use Mentor Graphics to design a master-slave flip flop of figure 4-7. Use hand simulation to simulate the behavior of the latch. You will need to the intermediate output (Y or Y' in figure 4-10) to understand the behavior of the device. Your simulation should show the following concepts: a). S active over several clock cycles. b). R active over several clock cycles. c). S and R active over a portion of clock cycle showing "ones catching". d). S and R both active near the end of the positive clock interval (simulate for a short time to see oscillation behavior).

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When do the outputs (intermediate Y and final Q) change in relationship to the inputs? In relationship to the clock? (Part of Project Part 1 -- NOT DONE HERE)

21). (Clocking Flip-Flops) Four D-type Flip-Flops or Latches are shown on the next page. Each device has the same clock and input signals. Plot the signal waveforms expected for Q. You may assume that all flip-flop Q outputs are "0" to begin with. You can assume the clock period is long compared to the logic delay.

CD Q

Q

C

D Q

Q

CD Q

Q

C

D Q

Q

CK

AA

CK

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22) (Clocked Flip-Flop behavior) The T, D, and JK, and JK-Master-slave flip-flops are connected to a common clock and input signals as shown on the last page. Plot the signal waveforms expected for Q. You may assume that all flip-flop Q outputs are "0" to begin with. You can assume the clock period is long compared to the logic delay.

CD Q

QCK

A

A

CK

J Q

Q

C

J Q

Q

CT Q

Q

K

K

C

BB