HIGHLY RECONFIGURABLE MULTI-

RADIX TRIVIUM DESIGN FOR

SECURED DATA TRANSMISSION

1Mr.T.R.Dinesh Kumar,2Dr.KMohanasundaram3Dr.M.Anto Bennet,

1Assistant professor,3Professor,Electronics and Communication Engineering, Vel tech, Chennai-600062

2Professor,Electrical and Electronics Engineering,Vel Tech Multitech Dr. Rangarajan Dr. Sakunthala Engineering

College,,Chennai,Tamilnadu,India

M Priyanka K Lakshmi Ravali

UG students,Department of Electronics and Communication Engineering

VEL TECH Chennai-600 062

Email:1dineshkumartr@veltechengg.com

Abstract:

A low-power dynamically reconfigurable Multi radix Trivium standard (MRT) is proposed for highly

protected data transmission in hardware to

Overcome side channel attack’s. The architecture is

functioned as a scalable IP Core Characterized by

means of having dynamic reconfigurable while in

curing only a ratio of ~2% increase in the energy

consumption and requiring ~40% less area then a

2048 –point non-reconfigurable MRT fabric using

register merging technique on the former hand,

compared with existing multi- radix trivium

architecture which is mapped onto the general

persistence reconfigurable architecture, It devours 30 ~94%less energy consumption. The tools required for

stimulation are Model-Sim and MATLAB and for the

tenacity of synthesis Quartus II IDE and Xilinx are

been used.

Index terms:

Trivium, Multi-radix, Reconfigurable FFT,Multi-

radixtrivium standard(MRT),Advanced Encryption

Standard (AES), Side Channel Attack (SCA),

HardwareTrojan, Quartus

1. Introduction:

The FFT (Fast Fourier Transform)takes a timedomain

signal then transforms it into frequency domain

signal that can bewidely used to find the unfilled part of the spectrum in 4G transmission and can

furthermore be castoff to design filters. Orthogonal

Frequency Division Multiplexing (OFDM), since its

discovery, has become an modulation of choice that

is being used in almost all wireless Low Noise

Amplifier standards like HiperLAN2, 802.11a,

802.16a, DAB, VDSL, ADSL and Digital Video

Broadcasting standard (DVBT). OFDM is an multi-

carrier system which encodes data bits on to multiple

subcarriers and transmitted instantaneouslyin time.

The transmitted stream of data experiences fading

due to its signal arrival from multi paths. This cause

received signal power to fluctuate. Different sub-

channels are distorted differently. A fixed set of

orthogonal sub-carriers together forms an OFDM

symbol. To avoid inter symbol interference (ISI) due to multiple paths, consecutive OFDM symbols are

alienated by the guard band. This makes it an very

proficient scheme for the transmission in multi-path

wireless channels. The usage of an FFT/IFFT pair for

the tenacity of modulation and demodulation makes

the transmission computationally efficient as well.

The enhancement in parallelism is equivalent to the

number of pipes introduced. Memory based

architectures are repeatedly used to analyze FFT in a

serial manner with one or few processing elements.

Intermediate FFT result and the twiddle factors are being stored in system memory. Memory based

architectures are well suitable for area efficient low

power applications[6,7,8].

TABLE I

HARDWARE COMPLEXITY OF THE FFT

ARCHITECTURES

International Journal of Pure and Applied MathematicsVolume 118 No. 20 2018, 3365-3372ISSN: 1314-3395 (on-line version)url: http://www.ijpam.euSpecial Issue ijpam.eu

3365

. Also, for very long length FFT calculations these

memory architectures might be best suited. Different

butterfly dispensation elements can require erratic

memory access patterns and provide various power

and speed results. Based on results from prior work we have also elected three FFT implementations that

would maximize/minimize power and area, power

and speed or area and speed. Table 1 gives the

various hardware difficulty of FFT architecture i.e

the number of registers, multipliers and adders.

Trivium:

Todeliveran flexible trade of amongst speed and the

gate count in hardware, Synchronous stream cypher

is designed called the trivium which is also

effectively used in software implementation. Output of about 264bit can bespawned from a 80 bit key plus

an 80 bit IV. This is a simplest

eSTREAMentrant,while this shows an remarkable

resistance to cryptanalysis on behalf ofit’s simplicity

and performance, present-day attacks leaves the

security margin consideringquite slim. Trivium's 288-

bit, internal state comprises of three shift registers of

alteredlengths. At every round a bit is being shifted to

each of the three shift registers by non-linear

combination of the taps from one register to other

register, one bit of the output is shaped. To initialize

cipher, key and IV are engraved onto two of the shift registers, with residual bits beginning in a static

pattern cipher state is formerly updated 4 × 288 =

1152 times, subsequently that every bit of the core

state depends on every single bit of its key and the IV

in an complex nonlinear way. Here no taps appear on

the first sixty five bits of every single shift register,

so every novel state bit is not been used until at least

65 rounds after it is generated. This is the vital key to

the Trivium's software performance & flexibility in

hardware.A straightforward hardware

enactmentoftheTrivium would use 3488 logic gates and produces one bit per clock cycles.

However, every state bit is not been used at least for

64 rounds, 64 state bits can also be generated parallel

at anmarginallysuperiorhardware cost of totally 5504

gates. Different trade-offs amongst speed and the

areas are also possible. The same property consents

an effectual bit slice execution in software,

performance testing by eSTREAM gives an bulk

encryption speed of around 4 cycles/byte on some x86platforms, which relates well to 19

cycles/byte of the AES reference execution on the

identical platform[8]Advanced Encryption

Standard (AES)AES is built on the design principle

which is known as a substitution-permutation

network, aamalgamation of both thesubstitution and

the permutation, andit’s comparatively fast bothin

software as well as in the hardware. Unlike it’s

antecedent DES, AES doesn’t use an Feistel network.

AES is anvariation of the Rijndael which has its

fixed block size of 128 bits, and a key size of 128,

192, or even 256 bits. By disparity, Rijndael specification is specified in terms of theyblock and

key sizes that might be between any multiples

ranging from 32 bits, with a minimum of 128 and an

maximum of 256 bits.AESfunctions on 4 × 4 column-

major order matrix of bytes termed the state, though

certain versions of Rijndael has an larger block size

and also has additional columns in the state. Most of

the AEScalculations are completed in a

particular finite field.For example, if there exist 16

bytes, these bytes are represented in the matrix

form.The key size that’s been used for the AES cipher specifies the total number of recurrences of the

transformation rounds that converts the input called

plaintext into the final output, called cipher text.

Total number of cycles of recurrence are as

follows,10 cycles of recurrence for 128-bit keys.

12 cycles of recurrence for 192-bit keys.

14 cycles of recurrence for 256-bit keys.

Every round consist of numerous processing step’s

each enclosing four alike but different stages,

including the one that depends on its encryption key

itself. A set of reverse rounds are applied to change

cipher text back into the original plaintext using the

equivalent encryption key[8].

The core objective of this paper is to design a novel

low-power, radix reconfigurable and input scheduling algorithm which is suitable for System on Chip

applications which can also be used in

implementingthe design MRT system that can be

designed as from 8-point to 128-point which is

mapped into a general purpose reconfigurable

architecture, can attain lower power and low area

consumption.

Side-channelattack:

Algorithm O

f Storage O

f No. No. O

f No.

Registers Adders Multipliers

SDF Radix-2 log 2 N − 2 2 log

2 N N − 1

Radix-4 SDF 0 . 5 log 2 N − 1 log 4

2 N N − 1

Radix- 2 2 SDF 0 . log 5 2 N − 1 log 2

2 N N − 1

MDC Radix-2 log 2 N − log 2 2

2 N 1 . 5 N − 2

Radix-4 MDC 1 . 5 log 2 N − 3 4 log

2 N 2 . 5 N − 4

Radix- 2 2 MDC log 2 N − 2 2 log

2 N 1 . 5 N − 2

International Journal of Pure and Applied Mathematics Special Issue

3366

Side-channel attacks don’t attack the cipher as

a black box, and thus are not related to the cipher

security as defined in the classical context, but are

significant in practice. They attack enactments of the

cipher on hardware or software systems that

involuntarily leak data. There are several such type of known attacks on various implementations of AES

fig 1 shows the overview of in memory block.

.

Fig.1 The overview of in-memory AES

computingarchitecture at memory block level

Literature Survey:

The Security Data present on USB memory and sd

cards has not been sufficiently addressed in cryptography .TES (Tweable Enciphering Schemes)

Well recognized as the proper Secured data storage

Actual challenge is to Design an low cost TES which

can perform at the data rates of target memory device

.its combine a stream chipper with a universal hash

functions .STES was to obtain TES which can be

implemented in compact form and also in low power

[5]. FFT architecture are designed that cooley-tukey

class of algorithm this FFT designs are target for

OFDM application especially in future generation of

software radio design FFT works 64 Point Complex

input sample value and 16 bit precision FFT algorithm Efficient Computation of FFT here

optimize area, power and speed [7]. Hardware

Trojan(HJ) is one amongst the very well know

hardware security issue in past decades. HJ research

is abruptly focused on defense, detection and novel

designing HJ’sare transmitted by a adversary for

leaking secret data, DNS etc. The Frequency of clock

used in sensitive operation which are applied on AES

benchmarks [2]. In government, business and other

fields for very high security Cryptographic chip is

used. But the attackers mainly modify those chips namely Trojan implementation. Efficient method in

Hardware Trojan is also used in AES circuit it will

judge weather the circuit is injected with Trojan or

not[6]. This result will improve the Trojan triggering

AES cryptographic circuits [3].AIDA/cube testers

arebeneficial in building distinguisher for

cryptography skill which is comprehensively used for

distinguishing purpose. Multi-x2 and AIDA/cube

tests are utilized in normal form of monomial test

were output reduce the round trivium for being random. AlgebraicIV differential attack is one

amongst the main concern the appropriate choice of

variables and data [1]. In DFT, the computation is

completely based on structural pattern which is

widely used in design is Radix 2n were n denotes

number of points. The FFT/IFFT complexity of task

is n-log2n. The non -reconfigurable input output data

is proposed two algorithms DFT&IDFT [4]. There

adaptive reconfigurable to any two point FFT/IFFT

input output sequence.

STANDARD MULTI-RADIX TRIVIUM

HARDWARE IMPLEMENTATION

Trivium is an synchronous stream cipher intended to

generate up to 264 bits of pseudorandom key stream

froms an 80-bit secret key (KEY) and also an 80-bit

initialization vector (IV). It was first proposed by De

Canniere along withPreneel. The cipher’s

architecture is completely based on an 288-bit cyclic

shift register (also called an internal state register),

with combinational logics (AND and XOR gates)

providing its nonlinear feedback. Implementations of Trivium algorithm comprise three shift registers of

varying lengths. The total number of output bits

generated per clock cycle is called radix. This paper

describes enactments of the Trivium algorithm that

generate radix-1, radix-2, radix-8, and radix-16.

These multiple radices are generated using the similar

internal state register but shifting it one or more bits

to its right depending on the radix (1, 2, 8, or 16 bits)

as shown in the schematic of the radix-m Trivium

stream cipher

LOW-POWER MULTIRADIX TRIVIUM

HARDWARE IMPLEMENTATION- The parallelization technique cannot be

applied directly to all the state register flip-flops in

the Trivium stream cipher, because the outputs of

some of them are involved in combinational

operations

Data / address / command IO External processor

Data array

In - memory AES logic

Local data path for in - memory logic

memory

Local data / AES logic pair

International Journal of Pure and Applied Mathematics Special Issue

3367

Fig.2Schematic of the radix-mTrivium cipher.

. We suggest two new low-power multi-radixTrivium

implementations using logic parallelization

techniques: MPLP and FPLP. In MPLP,

parallelization is applied to flip-flops unaffected by

nonlinear feedback paths, i.e., the less significant bits

from each shift register; 196 out of 288 bits in the

state register for radix-1 and radix-2, 144 out of 288 for radix-8, and 96 out of 288 for radix-16.

Parallelization requires a slight hardware

modification in each shift register shown in Fig. 1. A

schematic representation of the radix-2 MPLP

Trivium is shown in Fig. 2. The first shift register

contains bits 0–63, the second, bits 93–156, and the

third, bits 177–240. With the parallelization

technique, the bits in every shift register not involved

in feedback or combinational operations (LSB bits)

are divided into two separate shift registers

denominated odd and even shift registers. Each of

these has half-bits, so the total length of the shift register remains the same.

Proposed system:

A low-power dynamically reconfigurable Multi radix

trivium is proposed in this paper. The architecture is

served as a scalable IP Core which is suitable for real

time andfor highly secured hardware cryptography.

The proposed trivium architecture can also be

configured as 8,16,64, 128 and 256 point multi radix.

Compared with the conventional trivium, this MR-

Trivium design is characterized by having dynamic reconfigurable structure while incurring only a

12~19% increase in the energy consumption and

requiring 14% more area than a 512-point non-

reconfigurable trivium fabric. While on the other

hand, using clock skew analysis a new model delay

based combined flip flop algorithm is proposed to

reduce sequential circuit reduction in trivium.

FIG 3 block diagram

FPGAs have become a best applicable alternative

VLSI implementation technology due to its

reconfigurabilty. Development of Trivium hardware

has been achieved high throughput and of low power

consumption .The proposed architecture is

synthesized using Quartus II IDE with Cyclone III

FPGA. Experimental results show that the

architecture attains the throughput as essential by the

cryptography standard as well as the design has

additional features such as low area and high security

related to its previous methodologies. The design used 5% of the total obtainable FPGA resources and

the maximum clock frequency of 5 GHz can be

achieved.

Result And Analysis:

TABLE II HARDWARE AES

AREA

POWER Fmax

Total

powe

r

Dyna

mic

Static I/O

Power

4983(10

iteration

s)

525

(Register

s)

598.8

7mw

73.13

mw

81.60

mw

444.14

mw

125.77

Mhz

TABLE III

HARDWARE TRIVIUM

AREA

POWER Fmax

Total

po

wer

Dynamic

Static

I/O Pow

er

627(1

iteratio

n)

512

(Regist

ers)

218

.08

mw

56.6

2mw

80.

28

mw

81.1

8mw

228.87Mhz

International Journal of Pure and Applied Mathematics Special Issue

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Fig 4 AES waveform

Fig 5 Trivium waveform

Fig 6Trivium Key

Conclusion:

In this work, we have proposed a multi radix trivium

in which the data is highly secured from the external

norms were as the previously used algorithms

consists of the 2-radix,4-radix and 8-radix were the

expected security is not attained therefore by using of

the Advanced encryption standard(AES). Here, the

transmitter as well as the receiver will not be aware

of the radix type been executed during transmission

as it is automatically generated[fig 6] . In the conventional trivium an output power of 218.08mW

is achieved were as in the implemented design an

output power of 168.39mW is attained.[table III,IV]

The area is reduced from 4983(LE) to 627(LE) [table

II,III] successfully and the output delay is reduced by

0.0041(micro seconds) compared to the conventional

trivium.

Reference:

[1] FahadQureshi, Muazam Ali, and JarmoTakala.” Multiplierless Reconfigurable Processing Element for Mixed Radix-2/3/4/5 FFTs” 978-1-5386-0446-5/17/$31.00 ©2017 IEEE.

[2] Kunpeng Bai1,2 and Chuankun Wu1∗.”An AES-Like

Cipher and Its White-BoxImplementation”. [3] Md. Jahiruzzaman, MasudAnNur Islam Fahim, SakibMostafa, A. B. M. AowladHossain.” An Adaptive Reconfigurable Radix-2n FFT/IFFTArchitecture”. 2016 5th International Conference on Informatics, Electronics and Vision (ICIEV).

[4] J. Gong, G. Chen, L. Li, and J. Li, “A secure authentication protocol for RFID based on Trivium,” ,Jun. 2011, pp. 107–109. [5] DebrupChakraborty, CuauhtemocMancillas-L_opez, and PalashSarkar.” STES: A Stream Cipher Based Low

TABLE IV PROPOSED HARDWARE TRIVIUM

AREA

POWER Fmax

Total po

wer

Dynamic

Static

I/O Pow

er

627(1 iteratio

n) 512

(Registers)

168.39mw

15.75mw

80.12

mw

72.52mw

239.35Mhz

International Journal of Pure and Applied Mathematics Special Issue

3369

Cost Scheme for Securing Stored Data”.0018-9340 _ 2014 IEEE.

[6] Dr. AntoBennet, M, SankarBabu G, Suresh R,

Mohammed Sulaiman S, Sheriff M, Janakiraman G

,Natarajan S, “Design & Testing of Tcam Faults

Using TH Algorithm”, Middle-East Journal of

Scientific Research 23(08): 1921-1929, August 2015

.

[7] Dr. AntoBennet, M “Power Optimization

Techniques for sequential elements using pulse

triggered flipflops”, International Journal of

Computer & Modern Technology , Issue 01

,Volume01 ,pp 29-40, June 2015.

[8] Dr. AntoBennet, M,Manimaraboopathy M,P.

MaragathavalliP,Dinesh Kumar T R, “Low

Complexity Multiplier For Gf(2m) Based All One

Polynomial”, Middle-East Journal of Scientific

Research 21 (11): 2064-2071, October 2014.

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