Spring semester (4/2009)

High Speed Signal Processing Board Design

By: Nir Malka, Lior RomInstructor: Mike Sumszyk

הטכניון - מכון טכנולוגי לישראל

הפקולטה להנדסת חשמל המעבדה למערכות ספרתיות

מהירות

Characterization report

Table of contents Project Goals Part A Goals High speed Current High Speed Technology Altera DE3 Block Diagram A/D & D/A Signal Integrity Time table

Spring semester (4/2009)

Project goals Design, implement and debug a high speed

analog to digital daughter board which interfaces to Altera DE3. Part A: implement a daughter board

that can sample at high speed an analog signal and transfer it to the DE3

that can receive a wide band digital signal from the DE3 and convert it an analog signal

Part BImplement a real time signal processing algorithm on the FPGA, which will process an analog input from

the daughter board .

Spring semester (4/2009)

Part A Goals

Study the architecture of Altera DE3. Study the components and interfaces of

the daughter board. Orcad Design. Layer Design of the PCB. Validation of the daughter board.

Spring semester (7/2008)

High Speed

Spring semester (7/2008)

Bit rate examples-

Audio• 8 kbit/s – telephone quality • 32 kbit/s – AM quality • 96 kbit/s – FM quality • 224–320 kbit/s –CD quality. Video 1.25 Mbit/s – VCD quality 5 Mbit/s – DVD quality 15 Mbit/s – HDTV quality 36 Mbit/s – HD DVD quality 54 Mbit/s – Blu-ray Disc quality Video camera 530 Mbit/s – Pixel size- 1280*720 with 30fps framerate. (RGB)

Current High Speed Technology

LVDS - Low-voltage differential signaling, is an electrical signaling system that can run at very high speeds over inexpensive twisted pair copper cables

CML- Current mode logic is a differential digital logic family intended to transmit data at speeds between 312.5 Mbit/s and 3.125 Gbit/s over a standard printed circuit board.

LVPECL- Low-voltage positive emitter-coupled logic is a power optimized version of the positive emitter – coupled logic (PECL) technology, requiring a positive 3.3V instead of 5V supply. LVPECL is a differential signaling system and mainly used in high speed and clock distribution circuits.

Spring semester (7/2008)

Current High Speed Technology

Spring semester (7/2008)

We will use the LVDS technology for it’s low power consumption andThe compatible Altera DE3 interface

Altera DE3

Spring semester (4/2009)

The following hardware is implemented on the DE3 board: • Altera Stratix® III FPGA device (3SL150.........) with 142,000 logical elements.• the highest speed I/O transmission reaches 1.25…..1.6 G bps (top limitation of Stratix III).• High speed expansion Interface:

• 8 HSTC connectors• Two 40-pin Expansion Headers

• Memory Interface • DDR2 SO-DIMM socket – (up to 4

GB)• SD Card socket – 512MB

True and Emulated LVDS

HSTC Connectors

Spring semester (4/2009)

Technologies. (J1 ~ J8), which can be used toconnect the Stratix III FPGA with daughter boards. Bank 1 supports True LVDS on both RX and TX. Bank 2 and 3 supports True LVDS on RX.

• The High Speed Terasic Connector (HSTC) is a high speed expansion interface defined by Terasic• The DE3 board is equipped with 8 HSTC connectors• There are three banks on a HSTC connector

Critical questions

Can we use emulated LVDS pins? Can we use at the same time true and

emulated LVDS pins? Can this involve synchronization problems?

In case we use several HSTC connectors, how can we handle the synchronization problems?

Highspeed A/D and D/A Daughter Board

Dual AD channels with 14-bit resolution and data rate up to 65 MSPS.

Dual DA channels with 14-bit resolution and data rate up to 125 MSPS.

Dual interfaces include HSMC and GPIO, which are fully compatible with Cyclone III Starter Kit and DE1/DE2/DE3, respectively

Made by Terasic, price 219$.

Block diagramHigh Speed signal processing Board

Analog Input Circuit

ADC

Analog Output Circuit

DAC

DE3 (Digital Processing)

Analog signal Analog signal

Digital signal Digital signal

Analog Input Analog Output

HSTCHSTC

AD9211- 10-Bit, 300 MSPS Main Features:• LVDS at 300 MSPS.

• 700 MHz full power analog bandwidth.

• Input Voltage range- 1v-1.5V, nominal 1.25v.

• 1.8V analog and digital supply operation.

AD9780- 12-Bit, 500 MSPS Main Features:• LVDS inputs with dual-

port

• Sample rates of up to 500

MSPS • Operates from 1.8 V and

3.3 V supplies.

• Input Voltage range 0.8V-1.6V

SiI 1161 Receiver The SiI 1161 receiver

uses PanelLink Digital technology to support

high-resolution displays up to UXGA (25-165MHz). This receiver supports up to true

color panels (24 bits per pixel, 16M colors) with both one and two pixels per clock.

3.3V operation

SiI 1162 Transmitter The SiI 1162 transmitter

uses PanelLink® Digital technology to support

displays ranging from VGA to UXGA

resolutions in a single link interface. The SiI 1162 transmitter uses a 12-bit interface, taking in one half-pixel per clock edge.

Low Voltage Interface: 3.0V to 3.6V range and 1.0 to 1.9V range.

Scaleable Bandwidth: 25 - 165 Mps

Signal Integrity

Spring semester (7/2008)

Some of the main issues of concern for signal integrity are:

• Overshoot• Jitter• Cross-talk• Ringing• Ground bounce

Time Table

Spring semester (4/2009)

Due Date StatusStudy Signal integrity, similar project’s, LVDS, DE3.

Done

Study the components and interfaces of the daughter board. (2 weeks) and LVDS connections on Stratix III

25.5.09 In progress

Orcad Design:Analog input & output (1 week)A/D & D/Aconvertors Voltage supply (1 weeks) HSTC connector (3 week)

2.6.09

16.6.09

23.6.09

Time TableStudy Signal integrity, similar project’s,

LVDS, DE3. Study the components and interfaces of

the daughter board. (2 weeks) Orcad Design:

Analog input & output (1 week) A/D & D/A convertors (2 weeks) HSTC connector (1/2 week) Voltage supply (1/2 week)

Spring semester (4/2009)