High speed-pcb-board-design-and-analysis

High Speed PCB Design and Analysis

2 CADENCE DESIGN SYSTEMS, INC.

®

Agenda

• Today’s High Speed PCB design challenges

• Cadence PCB solution overview

• Demonstration overview

• Summary

• Q&A


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MARKET CONVERGENCEIS DRIVING DESIGN CONVERGENCE

MARKET CONVERGENCE DESIGN CONVERGENCE

Hardware Software

Digital Analog

Communications

Consumer

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IC Board


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High Speed Design Challenges

• Power and/or ground plane stability– Are power voltages at the ICs sufficiently controlled?

• EMI (differential and common mode)– Are critical signals radiating too much energy?– Are power planes producing common-mode radiation?

Hol

d

D0

D1

D2

D0

D1

D2

ClockDriver

Driving Receiving

Tco

Flight Time

Setu

p

1

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• System timing– What is the maximum data rate for reliable data transfer?

• Waveform integrity– Do signals meet applicable electrical requirements?

• Crosstalk– Do the signals interfere with each other?

D0 D1 D2D0 D1 D2

IC Board


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PCB System Design Flow and Products

Design EntryDesign Entry

High-SpeedPCB LayoutHigh-SpeedPCB Layout

IC Packaging

IC Packaging

ExplorationExploration

Capture CISConcept HDLCapture CIS

Concept HDL

AllegroSPECCTRA

AllegroSPECCTRA

Advanced Package Designer


NC SimPSpice/AWB

NC SimPSpice/AWB

PC

B D

esig

n In

fras

tru

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FunctionalVerificationFunctionalVerification

Floorplanning Floorplanning

SI

ANALYSIS

SI

ANALYSIS

CONSTRAINTS

CONSTRAINTS

IC Board

Digital Analog

Communications

Consumer

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SPECCTRAQuestSPECCTRAQuest



CONSTRAINT

MANAGER

CONSTRAINT

MANAGER


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PCB System Design Flow and Products

Design EntryDesign Entry

High-SpeedPCB LayoutHigh-SpeedPCB Layout

IC Packaging

IC Packaging

ExplorationExploration

Capture CISConcept HDLCapture CIS

Concept HDL

AllegroSPECCTRA

AllegroSPECCTRA



NC SimPSpice/AWB

NC SimPSpice/AWB

PC

B D

esig

n In

fras

tru

ctu

re

FunctionalVerificationFunctionalVerification

Floorplanning Floorplanning

SI

ANALYSIS

SI

ANALYSIS

CONSTRAINTS

CONSTRAINTS

IC Board

Digital Analog

Communications

Consumer

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IC Board

CONSTRAINT

MANAGER

CONSTRAINT

MANAGER


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An environment forcreation, verification and management

of all types of models



SPECCTRAQuest products today

Signal Integrity (SI)

PCB Systems IC-Packaging

SPECCTRAQuest SI Expert


SPECCTRAQuest Signal Explorer


Power Integrity (PI) SPECCTRAQuest Power Integrity

SPECCTRAQuest Power Integrity

SPECCTRAQuest IC Packaging (SQIC)SPECCTRAQuest

IC Packaging (SQIC)

Model Management Environment


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Introducing the Design Flow

• High speed design issues must be managed throughout the PCB design process

Model Development & Verification

Post Route Analysis

Verification

Topology Entry &

Floorplanning

Constraint Driven Layout

Simulation

Layout

Pre-Route Sol’n-Space

Analysis

IC Board


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SQ-SigXPSQ-SigXP Concept HDL ExpertConcept HDL Expert

• Timing driven floorplanning • Post placement verification• Post route verification

CMCM CMCMAllegro ExpertAllegro Expert

CMCM

I/Omodels

• Model Verification• Topology explorations• Rules development

Design Specs

SQSQ

CMCM


CMCM

SPECCTRA

ExplorationExploration Physical Layout Place Route Physical Layout Place RouteDesign/ImplementationDesign/Implementation FPFP

VerificationVerificationSimulationSimulation

SPECCTRAQuest in the PCB Design flowIC Board


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Constraint Driven Layout• Design rule violations during

interactive routing are identified in real-time

• Autorouter follows design rules - powerful integration with SPECCTRA!

• Because solution space analysis has defined a set of conditions under which the nets are known to work, chance of first-pass success is high.

– Nets can be ripped up and rerouted, as long as they still adhere to the design rules


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PSD 14.0 Constraint Manager

• Common, powerful environment for constraint entry / editing / management and verification

• Single mechanism for managing constraints throughout the design process


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Constraint Manager – Key Features

• Spreadsheet-based graphical interface

– No cryptic formats or cumbersome updating

• Provides unsurpassed Integration across the entire design flow

– Consistent Front to Back solution

– No translations with static constraint data

– Directly integrated with schematic and PCB databases

– Analysis engines can update spreadsheet data interactively

CADENCE DESIGN SYSTEMS, INC.

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• Innovative technology developed and proven by Sun Microsystems, now commercialized by Cadence Design Systems, Inc. to address Power Delivery issues in high-speed PCB System Designs.

• A design tool / methodology used to design and optimize the frequency-dependent characteristics of Power Delivery Systems in high-speed system designs

• An integrated solution to allow many quick iterations of “change-simulate-analyze”

• Introduced in PSD 14.1 release

CADENCE DESIGN SYSTEMS, INC.

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Power Delivery Requirements Trend

Year Voltage Power Current Frequency Ztarget

(Volts) (Watts) (Amps) (MHz) (m-Ohms)1990 5 5 1 16 2501993 3.3 10 3 66 541996 2.5 30 12 200 101999 1.8 90 50 600 1.82002 1.2 180 150 1200 0.4

• Power dissipation and longer battery life fueling decreasing chip power supply voltages – Maximum allowable supply ripple decreases accordingly

• SoC, SiP fueling trend towards devices with large number of devices – The instantaneous switching current required is enormous

• The maximum acceptable power supply ripple voltage determines the target impedance which must be maintained across the PCB


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Power Delivery System Design Challenges

• Power supply droop

– Alters system timing and can cause Setup failures

– Can cause sampling errors that results in a system crash

• Unreliable power delivery system design can cause increased common-mode EMI preventing product shipment due to compliance problems

• Power delivery system impedance is frequency-dependent

– Must be controlled for all frequency range of all transient currents

Increases Development Costs and Time to Market is LOST!Increases Development Costs and Time to Market is LOST!


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Power Delivery System Design -How it is done today

• Standalone analysis tools

– Design data translation is left up to the user

– Changes to the design resulting from simulation is manual

• Use Time Domain simulation

– Power delivery system impedance is frequency-dependent!

– With only time domain simulation, it is like searching for needle in a haystack

• Over design - add more de-coupling capacitors than necessary

– Expensive solution that may not work


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The Cadence approach

• Allow users to determine the needs of the power delivery system

– Target impedance

– Decoupling capacitor requirements

• Provide frequency domain analysis to find problem areas

• Provide an integrated PCB design editor to optimize capacitor placement

Develop reliable power delivery systemwhile shortening design cycle timeDevelop reliable power delivery systemwhile shortening design cycle time


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Introducing …SPECCTRAQuest Model Integrity(in v14.2)

Signal Integrity (SI)

PCB Systems IC-Packaging

Model Integrity (MI)(in v14.2)

SPECCTRAQuest Model Integrity






Power Integrity (PI) SPECCTRAQuest Power Integrity


SPECCTRAQuest IC Packaging (SQIC)SPECCTRAQuest

IC Packaging (SQIC)


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SQ Model Integrity

• Family of products that offers model creation, manipulation and verification environment

– First release (PSD release 14.2) will offer the basic creation/editing and sanity check environment for IO buffer models for following formats

– Cadence (DML)

– Quad [translator only]

– IBIS 3.2 [.ibs, .pkg, .ebd files]

– Future releases will offer advanced options that will provide verification environment and handle different kinds of models

– Capacitor models for use with SPECCTRAQuest Power Integrity

– S-Parameters

– IC Package models

– Connector/FPGA models

– Link with PCB Librarian Expert series


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Demonstration Overview

• Model development and validation using SPECCTRAQuest Model Integrity

• Constraint Development using SPECCTRAQuest SigXP

• Topology development using SPECCTRAQuest Floorplanner

• Constraints verification throughout the process

• System level verification using Design Link capability

• Power Integrity


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Brief Description - SPECCTRAQuest 14.2

• SQ/Allegro, SQIC/APD UI Synchronization

Allow users to switch between SQ & Allegro and SQIC & APD plus following commands to be changed in SQ

– Display > Element to replace Info > Item

– Logic > Net Schedule to replace Topology > Edit Pin Order

– Place > Manually to replace Floorplan > Component Place


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Brief Description – SPECCTRAQuest SI Expert 14.2

• Custom measurements

Custom measurements and Custom Stimulus will be available when simulating from the board level through the CM. In prior releases they were only available from SigXP

• Differential Signalling improvements

Extraction and simulation of coupled differential pairs in SQ, SigXP


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Brief Description - Constraint Manager 14.2

• Concept Database Synchronization

Synchronizes constraints stored as Schematic properties and CM worksheets

• Custom Measurement

Provides SigXP’s custom measurement capability in CM. Ability to store custom measurements and to display measurement results in CM [requires SQ SI Expert]

• Cross Probing ImprovementsCross probing with Allegro to handle segments/ratsnest, pin pairs, DRCs and Clines

High speed-pcb-board-design-and-analysis

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