High Speed Digital Signal Processing - the Bedlam...

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High Speed Digital Signal Processing - the Bedlam Board Paul Roberts – CASS Engineering Development Group EoR Workshop November 2012

Transcript of High Speed Digital Signal Processing - the Bedlam...

Page 1: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

High Speed Digital Signal Processing - the Bedlam Board

Paul Roberts – CASS Engineering Development Group EoR Workshop November 2012

Page 2: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Introduction

• Background on the Bedlam System

• Developed for a lunar Cherenkov experiment at Parkes • Influenced design choices and peripherals

• General purpose enough for many applications

• Used in several observation and measurement applications

including EoR

• Representative of typical DSP backend available for EoR experiments

Page 3: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Bedlam DSP Board

Page 4: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Bedlam Key Specifications

• 8 input channels at 512 MHz bandwidth

• 4 input channels 1024 MHz bandwidth • 2 x EV8AQ160 8-bit quad channel 1.25 GHz ADC • RF input bandwidth DC-2GHz (-3dB) • 4 x XC5VSX95T DSP oriented FPGAs • 1 x XC5VLX30T I/O FPGA • Simple parallel control/data interface to external PCI card • Dual 1 Gbit optical SFP ethernet interface • Add on mezzanine interface to 16 x 3.75 Gbit/s transceivers per

DSP FPGA (10 GbE CX4 etc) • Power 75W @ 12V DC or AC

Page 5: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Bedlam System Schematic

iI

ADC 4 channel 8 bit-1GS/s

ADC 4 channel

8 bit-1GS/s

FPGA XC5VSX95T

FPGA XC5VSX95T

FPGA XC5VSX95T

FPGA XC5VSX95

FPGA XC5VLX30T

RF INPUTS 1-4 RF INPUTS 5-8 C

ON

TRO

L /D

ATA BU

S

1 GbE SFP

1 GbE SFP

HIG

H B

W

CO

NTR

OL

/DA

TA

16 x 3.65G

b/s

Page 6: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

DSP Resources per SX95 (4 off)

SLICES (4 LUTs 4 FFs) 14,720 RAM 8784 kbit MULTIPLIERS (25x18) 640

3.65 Gbit/s Serial I/O 16 Ethernet MAC 4

Example 2 input 4096 channel DFB auto/cross correlator (2 auto / 1 cross with 64 bit accumulators) SLICES (67%) MEMORY (81%) MULTIPLIERS (37%)

Page 7: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Typical Operation Modes

Transient Mode

Spectrometer/Correlator Mode

Several reference designs

Page 8: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Features

Simple standalone instrument – 2U Rack case Easy to understand and use Simple to manufacture Reference designs available Can use open source (CASPER) high-level DSP blocks for easy adoption and customization

Attractive features

Limitations

No external memory on board

Page 9: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Applications

High Energy Particle detection via radio Cherenkov emission - Ekers et al

UHE neutrino/CR > 1020 eV

radio photon

shower

Page 10: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Parkes 21cm Multibeam Experiment

Centaurus A neutrinos

RFI

Veto

Page 11: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Parkes: RFI pulse

Pol A Pol B

4 micro sec 4 micro sec

Page 12: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Parkes: Possible Event

Pol A Pol B

4 micro sec 4 micro sec

Veto

8.1σ

Page 13: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Applications – Spectral RFI Monitoring

4096 Channel DFB Spectrometer - Band 800-1000MHz

GSM900

NextG

Page 14: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Applications - Precision system testing ASKAP RFoF link stability

V1 V2*

v1

v2 Cross-correlator

NOISE SOURCE

RFoF Link 3km

Perturbation – temp, mechanical etc

Page 15: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Applications - Precision system testing ASKAP RFoF link stability

Phase @ 1.4 GHz vs time

Page 16: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Applications - Precision system testing ASKAP RFoF link stability

Phase @ 1.4 GHz vs time

Amplitude @ 1.4 GHz vs time

Measurement variance - 0.001 db 0.001 deg

10s

Mechanical perturbation – oscillating pedestal fan

8 um var

Page 17: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Applications-Transient RFI Monitoring and Mitigation

Parkes 0.5-6GHz survey Boolardy RFI site monitor

Page 18: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

CSIRO. Science Review 2011

Applications-Transient RFI decoding – Aircraft Tracking

Page 19: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Use in cross-correlation Question of input coupling in cross-correlation mode ADC has inter-channel isolation typically -57 db from datasheet ⇒ Voltage coupling ~ 0.001

⇒ Correlator muliplies voltages

V

0.001 V

| V1 V2* | = 0.001 |VV|

Compare with other uwave components in coupled signal chain

Include in model and/or Use phase switching to reduce

Page 20: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Current developments

EoR – other talk - BIGHORNS - Self-Calibrating receiver –Keith’s talk Short pulse calibration methods -Nipanjana broadband pulses can be gated out simple identification of discontinuities unambiguous time/phase other uses- direct ionospheric dispersion (TEC) measurement etc ?

Page 21: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Pulse calibration

v1

v2

PULSE SOURCE

SYSTEM

REF

SYNC ACCUM

TRIGGER

SIG

Radiated/direct BEDLAM

Page 22: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Pulse calibration – making pulses

CSIRO. EoR Workshop 2012

Pulse width : 350 ps

Pulse amplitude 400 mV into 50 ohm.

Page 23: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Pulse calibration – making pulses

CSIRO. EoR Workshop 2012

Pulse amplitude 700V into

50 ohm (10kW).

Pulse rise time 950 ps

Page 24: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Summary

Real-time digital signal processing can help solve many of the problems encountered in EoR experiment design

Cheap, easy to use hardware platforms exist.

Should be fully exploited

Page 25: High Speed Digital Signal Processing - the Bedlam Boardcaastro.org/files/30/1416096950/roberts_bedlamdsp.pdf · Bedlam Key Specifications • 8 input channels at 512 MHz bandwidth

Contact Us Phone: 1300 363 400 or +61 3 9545 2176

Email: [email protected] Web: www.csiro.au

Thank you

CASS Engineering Development Group Dr. Paul Roberts Phone: 61 2 9372 4365 Email: [email protected] Web: www.csiro.au/org/cass