High Speed Digital Design & Verification Seminar...Real time ‘scope versus other jitter solutions...
Transcript of High Speed Digital Design & Verification Seminar...Real time ‘scope versus other jitter solutions...
High Speed Digital
Design & Verification
Seminar
Measurement fundamentals
Agenda
Sources of Jitter, how to measure and why
Importance of Noise
Select the right probes!
Capture the eye diagram
Why measure Jitter?
Determine the probability of how often a design will meet a bit error rate specification (10-12 BER typically desired).
Understand the source of jitter in order reduce jitter to meet a timing budget requirement.
Test for compliance to ensure compatibility between components from multiple vendors.
Ensure that digital designs have the timing margins to operate reliably 24 hours a day.. 7 days a week.. without crashing!
Where does jitter come from?
Transmitter Receiver
•Thermal Noise (RJ)
•DutyCycle Distortion (DCD)
•Power Supply Noise (RJ, PJ)
•On chip coupling (PJ, ISI)
•Lossy interconnect (ISI)
•Impedance mismatches (ISI)
•Crosstalk (PJ)
•Termination Errors (ISI)
Total jitter components
TJ: Total Jitter (convolution of RJ (based on BER) & DJ, and measured in peak-to-peak.
RJ: Random Jitter (rms)
DJ: Deterministic Jitter (peak-to-peak).
• PJ: Correlated & uncorrelated Periodic Jitter (caused by cross-talk and EMI)
• DDJ: Data Dependent Jitter
• DCD: Duty Cycle Distortion (caused by threshold offsets and slew rate mismatches).
• ISI: Inter-Symbol Interference (caused by BW limitation and reflections).
Jitter probability: BER
random tic determinis pk pk n J J s ´ = -
=
How do real time ‘scopes measure jitter?
NRZ
Serial
Data
Recovered
Clock
Jitter
Trend
Jitter
Spectrum
Units in Time
Units in Time
Jitter
Histogram
Important settings for accurate results in
eye diagram & jitter analysis
• Clock signal edge position are compared against reference Clock edges
• Data signal edge position are compared against reference Clock edges
Is my serial system using an explicit clock I can probe ?
• Yes-> Probe the clock and configure scope to use it!
– If receiver apply a multiplier -> scope must be configured to to the same
– If receiver apply a PLL on explicit Clock -> scope must do the same
• No? -> Derive the clock from the data using software PLL emulation
• Software clock recovery must be flexible to imitate Receiver Clock recovery
• Jitter Observed on Oscilloscope depend on Soft PLL Bandwidth Parameter
• Too Big PLL bandwidth transalte into lower observed Jitter
• Too Small PLL bandwidth translate into higher observed Jitter
• The good software PLL BW Value is the one from YOUR Reciever
What is real-time jitter analysis?
The timing variation measurements can be…
• Data: Time Interval Error (TIE), sometimes called “phase error”
• Clock: Period, Cycle-to-Cycle, N-Cycle
• Parametric: Frequency, rise time, setup time, hold time in a synchronous system
The views includes…
• Eye Diagrams (repetitive volts vs time)
• Histograms (N vs time error)
• Trend (time error vs time)
• Spectrum (time error vs frequency)
• RJ/DJ separation (rms/p-p tabular)
• Bathtub curves (BER vs eye opening)
Real-time jitter analysis consists of a collection of successive
timing variation measurements displayed in multiple views
where…
•Can measure data rates up to >28Gb/s
•Can measure jitter frequencies up to 1/2 the data rate
•Can use software for ideal clock recovery (no added jitter)
• Can correlate jitter to other signals (power supply, cross-talk)
• Can measure jitter on live signals with active probes
• General purpose tool, useful for other tasks
• 1ps@12GHz / 150fs@33GHz rms jitter noise floor typical
Weakness of Real Time Oscilloscope Jitter Measurements
Measuring low frequency jitter requires lots of Memory
Real time Oscilloscope trade-offs
Benefits of Real Time Oscilloscope Jitter Measurements
Compliance
• Component Manufacturers
• 50 ohm fixtured
• Driven by standards work
Debug
• PCB/System Engineering
• Live Signals
• Logic Analyzers
• Jitter Identification!
Real time ‘scope versus other jitter solutions
Verification
• Probing Sweatshops
• Live Signals
• Ease of use, reliability
RT Scopes -
Active Probes
Needed
BERTs, TIAs,
DCAs,
Generators
Agilent EZJIT jitter measurement application
Signal
Trend
Histogram
Spectrum
Best shown live
on scope (NB This note disappears in
slideshow mode)
Why is Noise important?
Noise eats up margin
•By adding vertical noise
•By increasing jitter
Noise is a significant concern in real-time scopes:
• Wideband front end
• High-speed digitizer
Why is vertical noise floor important ?
Let’s consider theoretical signals with Zero jitter and fixed voltage noise
with three different edge speeds and crossing a Threshold at 50%
1)Voltage noise translates directly to Timing uncertainty (Jitter)
2)Higher Vertical Noise Floor translates to higher Timing uncertainty
3)At constant amplitude noise floor, slower edge speed translates to higher
Timing uncertainty
Noise sources
Noise
Probe Attenuator A/D Amplifier
Probe Noise Quantization Noise
Quantify your scope noise!:
• AC Vrms Measurement
• Histogram-standard deviation
• FFT
Auto measurement of noise: AC Vrms
Best shown live
on scope (NB This note disappears in
slideshow mode)
Histogram: standard deviation ~ AC Vrms
Best shown live
on scope (NB This note disappears in
slideshow mode)
FFT
Best shown live
on scope (NB This note disappears in
slideshow mode)
FFT- ADC spurs
Best shown live
on scope (NB This note disappears in
slideshow mode)
FFT-harmonic distortion
Best shown live
on scope (NB This note disappears in
slideshow mode)
Noise minimization technology
Patented, proprietary Agilent Faraday Shield packaging
• Means measurement accuracy for HSD
Why are probe loading and response Important?
Probe loading affects your device under test.
You want to observe as nearly as possible the
operation of your circuits without the probe.
You want to see as nearly as possible what is happening at
the probe tip. You don’t want to make assumptions or
guesses.
Probe selection fundamentals
The probe becomes part of the circuit under test and may
change your circuit’s operation (ZPROBE Infinity)
The probe may or may not accurately reproduce the signal
under test
Circuit Under Test
Simplified probe loading model
Zsource
CPROBE RPROBE
LGROUND
LSIGNAL
• Resistive, capacitive and inductive
loading effects must be considered
Probe impedance versus frequency
R
C
L
|Z|
f fRES
fRES 1
2 LC =
Dominates Z At Low Frequencies
Resistive loading
Effects
• Bias change
• Amplitude reduction
• Offset shift
For Errors Less than 10%
RPROBE 10 RSOURCE >
Dominates Z At Mid-Band Frequencies
Capacitive loading
Effects
• Risetime Change
– Could cause circuit to START working
– Could cause circuit to STOP working
• Propagation Delay Increase
• Bandwidth Reduction
Minimize probe tip capacitance to improve
timing measurement accuracy
Dominates Z At High Frequencies
Combined inductive-capacitive loading
Effects
• Resonant LC Tank
• Low Input Impedance
Minimize the length of connection
accessories (inductance = 1nH/mm)
fRES 1
2 LC =
Compensated High-Resistance Passive Dividers
Passive probes
6-14 pF
9 MW Adjustable Compensation
Capacitor
Probe Tip
Cable Oscilloscope Input
1 MW
Features:
Higher input resistance
High dynamic range
(>100V)
Benefits:
Applications: Tradeoffs:
Rugged vs. an active probe
Low cost
Small probe tip
General purpose probing
High resistance
nodes (<100kW)
Lowest bandwidth
(<500MHz)
Heaviest capacitive loading
50W Terminated Resistive Dividers
Passive probes
Probe Tip
450 W 950 W
Oscilloscope Input
50 W
50 W Cable
Input C < .2 pF
Features:
Low capacitive loading
Highest bandwidth ( 6GHz)
Benefits:
Applications: Tradeoffs:
Timing measurement
accuracy
Low cost vs. active probe
Low Z systems
Transmission line
systems
Heavy resistive loading
Active probing
The performance of an active
probe is dominated by the
connection to the point being
probed
+
-
Oscilloscope
ZO = 50W
50W
50W 50W 25KW
200 fF
ZO=50W
50W RF Connector
+sig
ZO=50W
200 fF
-sig
50W 25KW
Probe Cable ~ 5 mm ~ 10 cm (~4 in) Probe Amplifier
The InfiniiMax I Technology
Response and loading
The secret
Differential or single-ended?
EVERY signal is differential.
“Ground” is a convenient fantasy.
Differential probes offer:
•Higher CMRR, especially at high frequencies
•Immunity to “Outside mode” effects
•Higher impedance at high frequencies
Probing Methods for Differential Signals
• InfiniiMax Active Differential Probes • 13 GHz Solder-in, Socket, Browser,
SMA, ZIF
• Differential or Single-ended
• Use with Real-time Scope, DCA-J &
BERT
• Soft Touch Probes: • No PCB layout modification required
• No remaining stubs or sockets
• Use with 16800/16900 Series Logic
Analyzers, E2960 Series PCI Express
Tools
• DDR2/3 BGA Probes: • Access Command & Data signals
• Use with Scopes & Logic Analyzers
Active probes
Probe Amplifiers Agilent 1169A Agilent 1168A Specified Bandwidth 12 GHz 10 GHz
Characterized Probe Tips Yes Yes
Noise Referred to Input 2.5 mV rms 2.5 mV rms
Attenuation 3.45:1 3.45:1
Differential Dynamic Range 3.3 V p-p 3.3 V p-p
DC Offset Range +/- 16 V +/- 16 V
Maximum Voltage +/- 30 V +/- 30 V
Agilent offers excellent
bandwidth, characterized
performance for various
probe tips, low noise,
low attenuation, good
dynamic range and small
size in its InfiniiMax II
series probes
N5380A 12 GHz Differential
SMA Adapter Probe Head
N5381A 12 GHz Differential Solder-in Probe
Head: 210 fF input capacitance, 50 kOhm input resistance
N5382A 12 GHz Differential Browser: 210 fF input C, 50 kOhm input Resistance
Capturing an eye diagram
The easiest way to get an overall idea of the quality of the serial signal
Trigger on Clock signal (if available) as the rough first pass to build Eye Diagram
Eye Diagram is the superposition in the middle of the screen of 3 bits
Multiple case combined form the Eye (000,001,010,011,100,101,110,111)
Preceeding bits might impact the ones you’re seeing - this is called Inter Symbol Interferences
Use Clock Recovery with PLL Emulation on 8B/10B signal and memory folding to build eye
101 Sequence
Building an Eye diagram the synchronous way: Explicit Clock used as Trigger
011 Sequence Overlay of all combinations
Best shown live
on scope (NB This note disappears in
slideshow mode)
What represents “good enough”?
The eye-mask is the common industry approach to measure the eye opening
Failures usually occur at mask corners
• But what is cause of failure?
Violating USB FS 12Mb/s Eye Diagram Good Displayport Eye Diagram
Best shown live
on scope (NB This note disappears in
slideshow mode)