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High performance sensor interfaces: Efficient system architectures and calibration techniques Marc...
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Transcript of High performance sensor interfaces: Efficient system architectures and calibration techniques Marc...
High performance sensor interfaces: Efficient system architectures and
calibration techniques
Marc Pastre – 2011
High performance sensor interfaces, Marc Pastre 2011 2
Outline
• Sensor interfaces– System architectures
• Open-loop vs. Closed-loop• Continuous-time vs. Sampled
– Frontends• Voltage-, current-, charge-mode
• Case studies– Hall sensor
– MEMS-based accelerometer
• Digital calibration– Successive approximations
– M/2+M Sub-binary DACs for successive approximations
• Conclusion
High performance sensor interfaces, Marc Pastre 2011 3
Open-loop vs. Closed-loop
• Straightforward implementation
• Analog output
• Sensitive to sensor non-linearity
• Directly compatible with a loop
• Digital or analog output
• Insensitive to sensor non-linearity
• Sensitive to actuator non-linearity
• Feedback loop stability
• Bandwidth
Sensor FE BE Sens
Act FE Filter
feedback
High performance sensor interfaces, Marc Pastre 2011 4
Continuous-time vs. Sampled systems
• Continuous-time:– Straightforward– Low power consumption– High bandwidth– Not really compatible with continuous-time calibration
• Sampled systems directly compatible with:– Closed-loop modulators– Switched capacitor circuits– Digital calibration
High performance sensor interfaces, Marc Pastre 2011 5
Voltage-, current-, charge-mode
• Voltage-mode:– Hi-Z Instrumentation amplifier, Op-Amp (+ input)– Low-Z Op-Amp circuit, switched capacitor
• Current-mode:– Transimpedance amplifier
(based on common-source transistor, Op-Amp, …)– Switched capacitor circuit used as integrator– Virtual ground @ input
• Charge-mode:– Transimpedance integrator
(based on common-source transistor, Op-Amp, …)– Switched capacitor
High performance sensor interfaces, Marc Pastre 2011 6
Case studies
• Hall sensor microsystem:– Open-loop– Voltage-mode– Sampled– Continuous-time sensitivity calibration
• MEMS-based accelerometer:– Closed-loop– Voltage-/Charge-mode– Sampled – Sensor included in a loop
High performance sensor interfaces, Marc Pastre 2011 7
Hall sensor microsystem
• Continuous-time sensitivity calibration• Reference field generated by integrated coil• Combined modulation scheme mixes up reference and
external signal• Parallel demodulation schemes allow continuous
background sensitivity calibration• Compensation of any cause of drift (temperature,
mechanical stresses, ageing)
High performance sensor interfaces, Marc Pastre 2011 8
Sensitivity drift of Hall sensors
• Drift due to– Temperature– Mechanical stresses– Ageing
• Typical temperature drift– 500 ppm/°C uncalibrated – 300 ppm/°C with 1st order correction
• Typical ageing drift– 20’000 ppm (2 %)
SI/SI0
1.05
1.00T [°C]
30 100-40
High performance sensor interfaces, Marc Pastre 2011 9
System architecture
High performance sensor interfaces, Marc Pastre 2011 10
Spinning current modulation
• 2 modulation phases• Modulated signal, constant offset• Offset-free signal extracted by demodulation
A
Ibias
Bext
Vext Voff
Vext Voff
Voff
Switchbox
High performance sensor interfaces, Marc Pastre 2011 11
Combined modulation
• 4 modulation phases• Modulated signal & reference, constant offset• Modulation frequency of 1 MHz
ASwitch
box
Ibias
Bref
Voff
Iref
Bext
+(Vext + Vref) + Voff
(Vext Vref) Voff
(Vext Vref) Voff
(Vext Vref) Voff
High performance sensor interfaces, Marc Pastre 2011 12
Demodulation schemes
• 3 different demodulation schemes• Offset-free signal & reference demodulation, using
synchronous switched-capacitor circuits
Modulation
+(Vext + Vref) + Voff
4Vext 4Vref 4Voff
Phase Spin. Coil Amplifier output
Demodulation
Sig. Ref. Off.
+
-
+
-
+
-
-
+
+
+
+
+
-(Vext + Vref) + Voff
+(Vext - Vref) + Voff
-(Vext - Vref) + Voff
+
+
-
-
+
-
+
-
1
2
3
4
High performance sensor interfaces, Marc Pastre 2011 13
Reference signal demodulation
• 2 limitations for precise reference signal extraction:– Low reference signal level
• VHall;ref = (SI;Hall Ibias) (EI;coil Iref) = 40 V
• VHall;ref 0.1% = 40 nV
• Input-referred noise = 20 nV/Hz @ 1 MHz
– External signal aliasing• Vext;max = 100 Vref
• High-pass parasitic transfer function
• Solution: Reference signal filtering
High performance sensor interfaces, Marc Pastre 2011 14
Reference signal filtering
• Filtering combined with reference signal demodulation and analog-to-digital conversion
• Second-order low-pass filtering• Demodulator pole @ 1 kHz
– Feedback path in the switched-capacitor demodulator
• Delta-sigma pole @ 0.1 Hz– Long integration period
High performance sensor interfaces, Marc Pastre 2011 15
Filtering transfer function
High performance sensor interfaces, Marc Pastre 2011 16
External signal aliasing
• Variation of the external signal between the reference demodulation phases alias
• Derivative effect high-pass transfer function• Zero @ 100 kHz
[(Vext;1 Vref) Voff]
[(Vext;2 Vref) Voff]
[(Vext;3 Vref) Voff]
[(Vext;4 Vref) Voff] = 4Vref [(Vext;1 Vext;2) (Vext;3 Vext;4)]
Parasitic term
High performance sensor interfaces, Marc Pastre 2011 17
Effect of filtering on alias
• Minimum attenuation of 120 dB
High performance sensor interfaces, Marc Pastre 2011 18
Effects of filtering
• On noise– Bandwidth limited to less than 1 Hz– White noise integrated in limited bandwidth– Total input-referred RMS noise < VHall;ref 0.1% = 40 nV
• On aliased external component– Minimum attenuation of 120 dB– Vext;max = 100 Vref attenuated to
100 Vref / 106 = Vref 0.01%
• Extraction of Vref 0.1% possible sensitivity calibration with 1’000 ppm accuracy
High performance sensor interfaces, Marc Pastre 2011 19
Sensitivity drift compensation
• Sensitivity compensated by sensor bias current adjustment
• VHall = (SI;Hall Ibias) B
High performance sensor interfaces, Marc Pastre 2011 20
Offset compensation
• Compensation current injection into preamplifier• Demodulator can be optimized (low-pass filter)
High performance sensor interfaces, Marc Pastre 2011 21
Circuit micrograph
• 11.5 mm2 in AMS 0.8 m CXQ• Hall sensors & coils integrated
High performance sensor interfaces, Marc Pastre 2011 22
Measurement results
• Compared to state of the art:– High bandwidth– Low gain drift (6-10 times better)
Supply voltage
Sensitivity
Full scale
Bandwidth
Non-linearity
Gain drift
5 V
35 V/T
50 mT
500 kHz
< 0.1 %
< 50 ppm/C
High performance sensor interfaces, Marc Pastre 2011 23
MEMS-based accelerometer
• Closed-loop system• 5th order loop: Sensor (2nd order) + Filter (3rd order)• Low-precision front-end (7 bits)• Internally non-linear ADC• Digital filter (3rd order)• Versatile and reconfigurable system, yet featuring high
performances
High performance sensor interfaces, Marc Pastre 2011 24
System architecture
Sensor
7-bitADC
GN
D+
HV
-HV
Pre-amplifier
Demodulators(CDS) BufferHigh voltage
3rd orderdigital filter
HV switchcontrol
HV & Analog front end ASIC
Digitaloutput
bitstream
A/Dconversion
High performance sensor interfaces, Marc Pastre 2011 25
Frontend
• 11.5 mm2 in AMS 0.8 m CXQ• Hall sensors & coils integrated
fresetVpre
GN
D+
HV
-HV
reset sense actuation
t [s]
V
0.25 0.5 1
Hi-Z
+HV
-HV
GND
+HV
-HV
GND
+HV
-HV
GND
( )( ) 2
( ) ( )t
midt b
C xV x HV HV
C x C x
High performance sensor interfaces, Marc Pastre 2011 26
Time-interleaved CDS
Vin
Csum
freset;1
fsense fsub
fsense+ fadd
fsub
Cin
fadd
t
fsense
+sense actuation
freset;1
reset -sense actuationreset
fadd
fsub
freset;2
Vin
Csum
freset;2
fsense fsub
fsense+ fadd
fsub
Cin
fadd
fsub
Vout
fadd
High performance sensor interfaces, Marc Pastre 2011 27
Internally non-linear ADC
Resistors &ComparatorsA thermometric
decodingnon-lineardecoding
64 bits 6 bits 16 bits
High performance sensor interfaces, Marc Pastre 2011 28
Circuit micrograph
High performance sensor interfaces, Marc Pastre 2011 29
Measurement results
• Compared to state of the art:– High bandwidth– Low noise
f [Hz]
Nor
mal
ized
out
put n
oise
[dBF
S/√H
z]
100
101
102
103
104
105
-160
-140
-120
-100
-80
-60
-40
-20
f [Hz]
Nor
mal
ized
out
put [
dBFS
/√H
z]
100
101
102
103
104
105
-160
-140
-120
-100
-80
-60
-40
-20
Without signal 8g @ 222Hz
High performance sensor interfaces, Marc Pastre 2011 30
Measurement results
Supply voltage
Sampling frequency
loop order
Full scale
Bandwidth
Dynamic range (300 Hz)
3.3V / 9V
1 MHz
2 + 3 = 5
11.7 g
300 Hz
19 bits
SNR (300 Hz) 16 bits
Input noise 1.7 g/Hz
High performance sensor interfaces, Marc Pastre 2011 31
Digital calibration
• Digital compensation of analog circuits• Successive approximations:
– Algorithm– Working condition
• Sub-binary DACs for successive approximations:– Resolution– Radix– Tolerance to component mismatch– Architectures– Design
High performance sensor interfaces, Marc Pastre 2011 32
Digital compensation
• High-precision calibration of low-precision circuits• Alternative to intrinsically precise circuits
(matching & high area)
Analog systemInput Output
Digital calibrationalgorithm
DAC
CompensationDetection
High performance sensor interfaces, Marc Pastre 2011 33
Compensation methodology
• Detection configuration– Continuous: normal operation configuration– Interrupted: special configuration
• Detection node(s)– Imperfection sensing– Usually voltage-mode
• Compensation node(s)– Imperfection correction– Current-mode
High performance sensor interfaces, Marc Pastre 2011 34
Offset cancellation in OAs
• Closed-loop: calibration during operation possible• Open-loop: higher detection level
V -VO Vout = AVO
Closed-loop Open-loop
High performance sensor interfaces, Marc Pastre 2011 35
Offset compensation in OAs
• Compensation by current injection• Unilateral/bilateral• Compensation current sources: M/2+M DACs
High performance sensor interfaces, Marc Pastre 2011 36
Choice of compensation node(s)
• Compensation current corrects imperfection only• Current injected by a small current mirror, taking into
account:– Channel length modulation– Saturation voltage
• Connection of the current mirror does not affect the compensation node characteristics:– Impedance– Parasitic capacitance– System parameters linked to parasitics
High performance sensor interfaces, Marc Pastre 2011 37
Offset distribution before compensation
• Gaussian distribution• Depends on component matching
Voffset
[mV]
% o
f sam
ples
-10 -5 0 5 100
5
10
15
High performance sensor interfaces, Marc Pastre 2011 38
Offset reduction
• Offset can be reduced by:– Matching Increase area– Digital calibration
• Digital calibration circuits can be made very small• In deep sub-micron technologies:
– Design analog circuits with reasonable performance– Enhance critical parameters by digital calibration
• Mixed-signal solution is optimal in terms of global circuit area
High performance sensor interfaces, Marc Pastre 2011 39
Offset distribution after digital compensation
• Uniform distribution (in a 1 LSB interval)• Residual offset depends on DAC resolution
Voffset
[V]
% o
f sam
ples
-80 -70 -60 -50 -40 -30 -20 -10 0 100
2
4
6
8
10
High performance sensor interfaces, Marc Pastre 2011 40
Successive approximations
• The algorithm decides on the basis of comparisons• A comparator senses the sign of the imperfection
• Working condition: (i [2, n])
1
11
i
jji bbb
reset all di = 0for i = n downto 1
set di = 1if Cout > 0
reset di = 0end if
end for
High performance sensor interfaces, Marc Pastre 2011 41
Offset compensation: Target
• Z0: Correction value that perfectly cancels the offset
• A < Z0: Resulting offset negative
• A > Z0: Resulting offset positive
Digital input code (D)
Ana
log
outp
utva
lue
(A)
0 2 4 6 8 10 12 14 160
2
4
6
8
10
12
14
positive offset
negative offset
Z0
VO
Ctrl &SAR
AZ
DAC
High performance sensor interfaces, Marc Pastre 2011 42
Offset compensation: Algorithm execution
• From MSB to LSB• Bit kept if compensation value insufficient
Algorithm step
DAC
outp
utva
lue
0 1 2 3 4 50
2
4
6
8
10
12
14
reset all di = 0for i = n downto 1
set di = 1if Cout > 0
reset di = 0end if
end for
High performance sensor interfaces, Marc Pastre 2011 43
DAC Resolution
• Full scale chosen to cover whole uncompensated offset range
• Resolution corresponds to residual offset achieved after compensation
max;;
max;;
dcompensateoffset
teduncompensaoffset
V
V
LSB
FullScaleResolution
High performance sensor interfaces, Marc Pastre 2011 44
DACs for successive approximations
• Imperfections in DACs for compensation– Missing codes are problematic– Redundancies are acceptable
Ideal Missing code Redundancies
Binary radix Sub-binary radix
High performance sensor interfaces, Marc Pastre 2011 45
Sub-binary radix DACs
• Code redundancies are voluntarily introduced to:– Account for variations of component values– Avoid missing codes
• Arbitrarily high resolutions can be achieved without exponential increase of area
• For successive approximations:– Precision is not important– Resolution is the objective
• Sub-binary DACs are ideal in conjunction with successive approximations– Very low area
High performance sensor interfaces, Marc Pastre 2011 46
Digital input code (D)
Ana
log
outp
utva
lue
(A)
0 2 4 6 8 10 12 14 160
2
4
6
8
10
12
14
Sub-binary DACs: Radix
Digital input code (D)
Ana
log
outp
utva
lue
(A)
0 2 4 6 8 10 12 14 160
2
4
6
8
10
12
14
Radix = 1.5 Radix = 1.75
High performance sensor interfaces, Marc Pastre 2011 47
Radix: Tolerance to component mismatch
• Radix-2 tolerates no mismatch!• 100 % mismatch thermometric DAC (radix-1)
d
R
0.0 0.2 0.4 0.6 0.8 1.01.0
1.2
1.4
1.6
1.8
2.0
component mismatch
Radix
High performance sensor interfaces, Marc Pastre 2011 48
Implementation: Current-mode R/2R converters
• Req;i = 2R ( i)
• Current divided equally in each branch (ii = bi)
• Component imperfection current imbalance missing code (or redundancy)
1
11
i
jji bbb
Ibias
2R
R
2R
R
2R
R
2R 2R
Req;i
iibi
Iout
d1d2d3
High performance sensor interfaces, Marc Pastre 2011 49
R/2+R converters
• x > 2 ; Req;i < xR ; ii > bi
• Current division voluntarily unbalanced– Radix < 2 (sub-binary)– Code redundancies
1
11
i
jji bbb
Ibias
xR
R
xR
R
xR
R
xR xTR
Req;i
iibi
Iout
d1d2d3d4
High performance sensor interfaces, Marc Pastre 2011 50
R/2+R converters: Pseudo-MOS implementation
• Resistors can advantageously be replaced by transistors to implement the current division
• Unit-size device with fixed W/L implements R• Unit-size devices are put in series (2R) or in parallel (R/2)• Unit-size transistors are kept very small
• Condition: VG identical for all transistors
2RR R/2W/L
W/L
W/L
W/L W/L
High performance sensor interfaces, Marc Pastre 2011 51
M/3M converters
• Radix 1.77 ; maximum mismatch 13 %
• VG = VDD allows driving di directly with logic
Ibias
Iout
VG
d5 d5 d3 d3 d2 d2 d1 d1d4 d4
High performance sensor interfaces, Marc Pastre 2011 52
M/2.5M converters
• Radix 1.86 ; maximum mismatch 7.3 %
• VG = VDD allows driving di directly with logic
Ibias
Iout
VG
d5 d5 d3 d3 d2 d2 d1 d1d4 d4
High performance sensor interfaces, Marc Pastre 2011 53
Current collectors & Output stage
• Current mirrors simple to implement V is not problematic
Ibias
Iout
VG
d5 d5 d3 d3 d2 d2 d1 d1d4 d4
Iout V
High performance sensor interfaces, Marc Pastre 2011 54
Conclusion
• Closed-loop systems are less sensitive to imperfections• Calibration can be included transparently in sampled
systems• It is advantageous to include sensors in loops• Switched capacitor circuits enable flexible and
reconfigurable systems• Calibration is necessary in deep sub-micron technologies
to reach high performances• Improve analog performance with digital calibration:
– Design analog circuits with reasonable performance– Enhance critical parameters by digital calibration– Mixed-signal solution optimal in terms of global circuit area
High performance sensor interfaces, Marc Pastre 2011 55
References
• M. Pastre, M. Kayal, H. Blanchard, “A Hall Sensor Analog Front End for Current Measurement with Continuous Gain Calibration”, IEEE Sensors Journal, Special Edition on Intelligent Sensors, Vol. 7, Number 5, pp. 860-867, May 2007
• M. Pastre, M. Kayal, H. Schmid, A. Huber, P. Zwahlen, A.-M. Nguyen, Y. Dong, “A 300Hz 19b DR capacitive accelerometer based on a versatile front end in a 5th order ΔΣ loop”, IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 288-291, September 2009
• M. Pastre, M. Kayal, “Methodology for the Digital Calibration of Analog Circuits and Systems – with Case Studies”, Springer, The International Series in Engineering and Computer Science, Vol. 870, ISBN 1-4020-4252-3, 2006
• M. Pastre, M. Kayal, “Methodology for the Digital Calibration of Analog Circuits and Systems Using Sub-binary Radix DACs”, IEEE Mixed Design of Integrated Circuits and Systems Conference (MIXDES), June 2009
• M. Pastre, M. Kayal, “High-precision DAC based on a self calibrated sub-binary radix converter”, IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 1, pp. 341 344, May 2004
• C. C. Enz, G. C. Temes, “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization”, Proceedings of the IEEE, Vol. 84, pp. 1584-1614, November 1996