IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 52, NO. 9, SEPTEMBER 2005 591

High-Performance Error Amplifier for FastTransient DC–DC Converters

Jeongjin Roh

Abstract—A new error amplifier is presented for fast transientresponse of dc–dc converters. The amplifier has low quiescent cur-rent to achieve high power conversion efficiency, but it can supplysufficient current during large-signal operation. Two comparatorsdetect large-signal variations, and turn on extra current supplier ifnecessary. The amount of extra current is well controlled, so thatthe system stability can be guaranteed in various operating con-ditions. The simulation results show that the new error amplifierachieves significant improvement in transient response than theconventional one.

Index Terms—Boost converter, dc–dc converter, error amplifier,operational transconductance amplifier (OTA), pulsewidth modu-lation (PWM), transient response.

I. INTRODUCTION

THE switch-mode dc–dc converters have been widely usedin power supply systems and are becoming a common

building block in modern VLSI systems [1]. Especially forthe growing number of battery-operated portable systems, thedc–dc converter is an essential block since the linear voltageregulator cannot be used because of its low power efficiency.

CMOS controller ICs for dc–dc converters should bedesigned for low quiescent current consumption and for rea-sonably high-speed operation. However, the low-power andhigh-speed requirements are contradicting, which make thecircuit design a challenging task.

Fig. 1 illustrates a simplified structure of a current-modeboost converter [2]. Its main function is to convert input dcvoltage to higher output dc voltage with minimum power loss.The converter is composed of a power stage and feedbackcontrol circuits. is a battery voltage, which supplies input dcvoltage, and is the boosted output dc voltage. The inductor

, diode , and output capacitor are off-chip componentsbecause of their large sizes. Resistors and sense theoutput voltage and generate the scaled output voltage to theerror amplifier. is the load of the dc–dc converter, whichcould be any digital or analog systems.

All other blocks are integrated in a single controller IC. Theclock in Fig. 1 generates short pulses at a predetermined pe-riod, so that the SR latch can be set high by the pulses. Thereset timing of the latch is controlled by the comparator, whichcompares the output voltage of the error amplifier with the drainvoltage of M1. The drain voltage of M1 is proportional to thecurrent flowing, so if the scaled output voltage is lower than

Manuscript received June 16, 2004; revised January 6, 2005. This work wassupported by the Research Fund of Hanyang University (HY-2004-S).

The author is with the Department of Electrical and Computer Engineering,Hanyang University, 426-791 Ansan, Korea (e-mail: jroh@hanyang.ac.kr).

Digital Object Identifier 10.1109/TCSII.2005.850521

Fig. 1. Block diagram of a dc–dc boost converter.

, then the reset time of the latch will be delayed for morecurrent to charge the output capacitor . In effect, the latchgenerates a pulsewidth modulation (PWM) signal which is con-trolled by the feedback loop. In general, M1 is implemented asa very large transistor with its turn-on resistance of less than 1to reduce power loss of M1 itself. The error amplifier is an im-portant block for fast and accurate operation of the system. It de-tects and amplifies the difference between the reference voltageand the scaled output voltage. Then, the detected error voltageis processed by the compensator for the stability of the dc–dcconverter [2], [3].

II. STABILITY OF DC–DC CONVERTERS

Since switch-mode dc–dc converters are nonlinear circuits,linearized small-signal models are required to analyze the sta-bility of the feedback loop. The current-mode boost converterhas two poles and a right-half plane (RHP) zero [2]. The secondpole is well separated from the dominant pole and is close tothe switching frequency. Therefore, a simple first-order modelwith a single pole and a single RHP zero can be used as aclose approximation to the accurate model [2]. We use the ac-curate model for the computer analysis of stability to decide thefrequency compensation parameters. However, the first-ordermodel is used for hand calculation because of too much compli-cation of the accurate model, which does not give much intuitionabout the behavior of the circuit. The following equation shows

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592 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 52, NO. 9, SEPTEMBER 2005

Fig. 2. Control-to-output transfer function, G (s).

the first-order model of the control-to-output transfer function:

(1)

where equals the duration of the low PWM duty cycle [2].The main advantage of the current-mode converter is its

simpler dynamics. The small-signal control-to-output transferfunction contains one less pole than that of the voltage-mode converter. Therefore, simple robust output voltage controlcan be obtained without the use of a compensator lead network.The simple proportional-plus-integral (PI) compensation iscommonly used in current-mode converters, which is alsoused here.

Fig. 2 shows the Matlab plot of by the accurate model[2]. It shows that the uncompensated system has its crossoverfrequency at 10 kHz. The second pole is at 300 kHz, which isnot represented in the simple first-order model in (1). Fig. 3 isa frequency response of the PI compensation circuit toattain a crossover frequency at one-twentieth of the switchingfrequency [2].

The frequency characteristic of the compensated error ampli-fier is combined into the total feedback loop characteristic ofa dc–dc converter. Overall, the locations of the pole and zeroshape the feedback loop characteristic of the dc–dc converter toachieve a sufficient phase margin [3]. The loop gain equation ofthe total feedback loop is shown in

(2)

and is plotted in Fig. 4. The current sense resistance is in-cluded in the equation because (1) has its input as a controlcurrent.

The value of is 0.2 in our circuit design, which is theturn-on resistance of the nMOS switch, and other circuit param-eters are summarized in Section IV. The frequency response inFig. 4 shows the phase margin of 59 , which is very close to theoptimal phase margin of 60 .

Fig. 3. Compensated error amplifier, G (s).

Fig. 4. Total feedback loop, G (s).

Fig. 5. Compensated OTA.

Fig. 5 is an example of a compensation circuit [3], which isused in our circuit design with the proposed error amplifier. Thetwo off-chip capacitors and a resistor determine the location ofa zero and a pole.

III. DESIGN OF THE ERROR AMPLIFIER

A conventional current mirror operational transconductanceamplifier (OTA) in Fig. 6 is a reasonable candidate for the error

ROH: HIGH-PERFORMANCE ERROR AMPLIFIER FOR FAST TRANSIENT DC–DC CONVERTERS 593

Fig. 6. Conventional OTA.

amplifier. The design of the circuit is done by using a stan-dard 0.5- m CMOS process with threshold voltages of 0.9and 0.7 V for pMOS and nMOS transistors, respectively. Thetransistors are implemented by placing multiple unit transis-tors in parallel for better device matching, rather than makinga device wider. The width and length size of an unit pMOStransistor is m m and that of a unit nMOS tran-sistor is m m. The below each transistor name inFig. 6 shows the number of multiple unit transistors. For thesetransistor sizes, the overdrive voltages of pMOS transistors areabout 200 mV and those of nMOS transistors are about 140 mV.Since the tail current of the OTA is designed as 1.2 A, the draincurrents of input transistors M1 and M2 are 0.6 A each. Sincethe transconductance, which can be represented in the followingequation, is important for better performance of OTA, the widthsof input differential pair and are increased by making

:

(3)

Therefore, the input transistors have a relatively low overdrivevoltage of about 120 mV.

Since the current mirror ratio for the output stage is 20, themaximum output current is , which is 24 A. This max-imum current can be increased by higher current mirror ratio,but it will also increase the quiescent current of the amplifier,which is not desirable in dc–dc converters.

For high dc gain of the amplifier, the OTA’s output stage canbe modified into a cascode circuit [1], but at the cost of limitedoutput swing. Cascoding is not used in our circuit to have asimpler circuit to understand our proposed technique.

The current mirror OTA has a limited output current and, asa result, low slew rate such as

(4)

where is the current mirror ratio of M4 and M6 and isthe load capacitance. If or is increased, it will directlyviolate the requirement of low quiescent current.

Fig. 7. New OTA.

Fig. 8. Transconductance of the conventional and new OTA.

In order to increase the performance, a new OTA architectureis developed as in Fig. 7. Without the transistors M9–M12,the amplifier is same as the conventional one in Fig. 6. How-ever, the new OTA has an extra current driving capabilitycontrolled by the switches M10 and M11, which are drivenby their respective comparators, PDRIVE and NDRIVE. Thecomparators have built-in offset voltages, which make theswitches turned-off in quiescent condition. When the scaleddc–dc converter output voltage differs significantly from thedesired reference voltage, either PDRIVE or NDRIVE willactivate its respective switch M10 or M11, which have thewidth and length size of m m. The activated switchwill enable extra current to flow.

Recently, a similar amplifier architecture was proposed in[4] and [5] for flat-panel display application, which has about600-pF load capacitance. Conceptually, their idea is similar toours, if M9 and M12 are removed, in the sense that extra cur-rent is supplied during large-signal operation. However, directapplication of their architecture will lead to instability in dc–dcconverters, as will be explained later.

The simplified voltage–current characteristic of the error am-plifier is shown in Fig. 8, where its slope is the transconductance

. The dotted line is the characteristic of the conventionalOTA, while the solid line is that of the new OTA. If the inputsignal to the error amplifier is small in stable operation, thetransconductance of the error amplifier will be

(5)

594 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 52, NO. 9, SEPTEMBER 2005

where the transconductance can be expressed as in (3). The newOTA has increased transconductance when the input signal islarge. The new transconductance in large-signal operation willbe

(6)

The boundary for in Fig. 8 is determined by the offsetvoltage of the comparators PDRIVE and NDRIVE. Theoffset voltage is controlled by the built-in mismatch of the inputdifferential pair of the comparators. For the designed error am-plifier in Section IV, is set to 30 mV. Since the error ampli-fier’s input is the scaled output voltage by and in Fig. 1,which are 500 and 100 k , respectively, the output voltage vari-ation of the dc–dc converter should be larger than to turn onthe extra current supplier. The architecture of the conventionalOTA is also used for the design of the comparators.

The contribution of this study is twofold. First, the slewingproblem of the error amplifier is solved, and, as a result, thedc–dc converter has improved large-signal behavior as demon-strated in next section. As mentioned earlier, the conventionalOTA circuit may cause a slewing problem and lead to slowtransient response. We overcome this problem by employing ahigh-performance error amplifier.

Second, the extra current supplier is under complete controlin our amplifier. This is the significant improvement from thehigh slew amplifiers in [4] and [5] for the stable operation ofdc–dc converters. That is, if M9 and M12 are removed in Fig. 7,M10 and M11 will act as a current supplier, which makes theamplifier similar to that of [4] and [5]. For a simple buffer ap-plication, the large load capacitance, introduced by flat-paneldisplay, makes the buffer a single pole system. This enablesthe buffer stable even if varies. However, since dc–dc con-verters have several poles and zeros with complicated compen-sation, any variation in the compensator gain may affect theoverall feedback stability. For example, if the current supplieroperates in triode region, the transconductance will be

. The value of is critical sincedetermines the phase margin [3] of the feedback system,

where is the total transconductance of the OTA includingthe effect of such as

(7)

In (7), is the gain of the comparators that controls thecurrent driving transistors. The transconductance in the trioderegion heavily depends on , which is same asfor M11 or for M10, if we assume the architectureof [4] and [5]. Therefore, as the output voltage of the error am-plifier changes, the overall feedback characteristics will changeas well. Also, since most controllers for dc–dc converters usethe boosted dc–dc output voltage as a power supply of the con-troller itself, the variation of of a controller would be verywide depending on wide application of the dc–dc converters.This observation explains why a stable dc–dc converter in a cer-tain condition becomes unstable in different conditions, as willbe demonstrated in next section.

Therefore, it becomes mandatory to implement a stable erroramplifier regardless of and variations. Our new OTAhas well controlled extra current, which is determined by the

Fig. 9. Transient response with a conventional OTA.

current mirror ratio M9/M7 and M12/M4 in Fig. 7. Since theOTA has controlled current capability, the trasconductance ofthe amplifier is also controlled by current mirrors. Therefore,

is always well controlled regardless of the variations inand .

The available output swing of the error amplifier is limitedby the overdrive voltage of the output transistors. In order tohave large output swing, the cascode output stage such as in[1] is avoided in our design. Instead of using cascode stage,we increased the length of the output current mirror transistors

– and to increase the output impedance. These largetransistors also increase the parasitic capacitors, which are notdesirable in general designs. However, even a large parasitic ca-pacitor is negligible in the compensator architecture in Fig. 5since it already has huge off-chip capacitors.

IV. SIMULATION RESULTS

The HSPICE simulation results are shown in this section with0.5 m CMOS process parameters. The normal quiescent outputcurrent of the new error amplifier is designed as 14 A, and themaximum output current can be increased up to 48 A as wasexplained in previous section. The dc–dc converter is designedwith H and F at its switching frequency of500 kHz. The compensation circuit in Fig. 5 has k ,

nF, and pF. The sizes of these passivecomponents are common values in commercial high-frequencydc–dc converters.

In order to evaluate the load regulation of the controller, loadcurrent is changed from 100 to 300 mA at 1 ms. For the stepchange of load current, the large output capacitor loses itscharge, and therefore its voltage level drops. The error ampli-fier detects the voltage drop, and increases the compensatoroutput voltage, which in turn increases the PWM pulse width. Inorder to achieve fast transient response, the compensator outputvoltage should be increased swiftly.

Fig. 9 is from the simulation with the conventional error am-plifier in Fig. 6, which is similar to the error amplifier in [1]. Wecan observe large dc–dc output voltage drop and slow voltage

ROH: HIGH-PERFORMANCE ERROR AMPLIFIER FOR FAST TRANSIENT DC–DC CONVERTERS 595

Fig. 10. Transient response with a proposed OTA.

Fig. 11. Line regulation with a proposed OTA.

recovery. When the load current is increased to even larger cur-rent than 300 mA, the output voltage drop is more significant.

The transient response is also measured with the new erroramplifier for the same step change of load current from 100 to300 mA at 1 ms. Fig. 10 shows that the output voltage drop issignificantly less than that of the conventional circuit. As theoutput voltage variation becomes large, the new error amplifiersupplies extra current for fast settling. After the output voltageis recovered and as the dc–dc output voltage approaches thetarget, the extra current driving circuit turns off. In this case, theoutput of the compensator is the charged voltage of the capaci-tors, which is not high enough yet. Therefore, the dc–dc outputvoltage drops slightly because of the PWM duty ratio change.Then, it settles to the final voltage without the help of the extracurrent supplier, as in the conventional circuit.

For the line regulation test, a step input between 2.0 and2.4 V is applied like the lower trace in Fig. 11 with the dc–dc

Fig. 12. Unstable output voltage when too much extra current is supplied.

converter’s load resistance set to 10 . The output voltage,which is the upper trace in Fig. 11, experiences a sudden changewhen the input voltage changes, but it recovers immediatelyby the operation of the error amplifier and other feedbackcircuitry. As it was emphasized, the maximum extra currentand the transconductance of the error amplifier should be wellcontrolled for stable operation of the dc–dc converters. The

of the error amplifier shown in Fig. 8 is increased fivetimes to show the possibility of output voltage oscillation asin Fig. 12. The output voltage does not stabilize in this case,and keeps oscillating.

V. CONCLUSION

Fast transient response and low quiescent current are twoimportant, but contradicting, requirements of the controllersin dc–dc converters. In order to satisfy both requirements,an efficient amplifier architecture is developed. The designederror amplifier effectively increases the supply current forlarge-signal variations, while maintains small quiescent currentduring normal operation. In order to maintain stability of thesystem, the transconductance of the error amplifier is wellcontrolled in our design. Simulation results prove the fast andstable operation of a dc–dc converter.

REFERENCES

[1] C. F. Lee and P. K. T. Mok, “A monolithic current-mode CMOS DC-DCconverter with on-chip current-sensing technique,” IEEE J. Solid-StateCircuits, vol. 39, no. 1, pp. 3–14, Jan. 2004.

[2] R. W. Erickson and D. Maksimovic, Fundamentals of Power Elec-tronics, 2nd ed. Norwell, MA: Kluwer, 2001.

[3] A. I. Pressman, Switching Power Supply Design, 2nd ed. New York:McGraw-Hill, 1998.

[4] P.-C. Yu and J.-C. Wu, “A class-B output buffer for flat-panel-displaycolumn driver,” IEEE J. Solid-State Circuits, vol. 34, no. 1, pp. 116–119,Jan. 1999.

[5] C.-W. Lu and C. L. Lee, “A low-power high-speed class-AB buffer am-plifier for flat-panel-display application,” IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 10, no. 4, pp. 163–168, Apr. 2002.