High Performance Current-Mode Differential Logic
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2008-1-17 1 High Performance Current-Mode Differential Logic Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Univ. of California, San Diego Masanori Hashimoto Osaka University
Transcript of High Performance Current-Mode Differential Logic
2008-1-17 1
High Performance Current-Mode Differential Logic
Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Univ. of California, San Diego
Masanori HashimotoOsaka University
22008-1-17
Outline
IntroductionCurrent-Mode Differential Logic (CMDL)
Basic ConceptsStructure of CMDLExamples
Design Cases32-bit Multiplexer8-bit shifter16-bit adder
Performance comparisonConclusions and future work
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Introduction
Continuous scaling of semiconductor technology requires high performance circuit design:
Clock skew, wire delay and pipeline overhead increase:
Challenges on operation speed Clock frequency becomes higher:
Challenges on power budgetingdesign that has lower delay*power is desired.
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Previous works
Voltage-mode logic: Cascode Voltage Switch Logic (CVSL) [Heller et al. 1984]Complementary Pass-transistor Logic (CPL) [Yano et al. 1990], Low Voltage-Swing Logic (LVS) [Deleganes et al. 2004];
Current-mode logic: Dynamic Current-Mode Logic (DyCML) [Allam et al. 2001]
Properties:Differential logic: CommonLow swing vs. full swing output
Low swing output: LVS, CPLFull swing output: DyCML, CVSL
Pre-charge/reset required vs. not requiredPre-charge/reset not required: CPLPre-charge/reset required: others
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Cascode Voltage Switch Logic [Heller et al. 1984]
Introduced the concept of differential logic.Full swing outputsOutputs are pre-charged to low.Improvements:
SODS [Acosta et al. 1995] DCSL [Somasekhar et al. 1996]CSDL [Park et al. 1999]
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Complementary Pass-transistor Logic [Yano et al. 1990]
Differential inputs and outputs.Drain and gate inputsLow swing outputs: extra inverters are needed.No pre-charge phase.
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Low Voltage Swing logic [Deleganes et al. 2004]
Differential inputs and outputsLow swing outputs: sense amplifier is neededReset operation is needed.
Transistor count doubles.Load on clock increases.Need one extra stage of logic for thru-gate.A reset phase is inserted to each clock cycle.
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Dynamic Current-Mode Logic [Allam et al. 2001]
Differential inputs and outputsFull swing outputsPre-charged is required.
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Current-mode differential logic
Differential inputs and outputsLow swing outputs: sense amplifier is needed.
Fast operation speedPre-charge/reset is not needed, only evaluation phase is needed.
Less number of transistorsNo need for thru-gate: more headroom of logic depthLow power consumption
More reliable against noise effect
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OutlineIntroductionCurrent-Mode Differential Logic (CMDL)
Basic ConceptsStructure of CMDLExamples
Design Cases32-bit Multiplexer8-bit shifter16-bit adder
Performance comparisonConclusions and future work
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Basic concepts of Current-mode logic
1. Fast operation speedReduced RC time constant
2. To maintain the low swing outputCurrent-mode logic inherently enables low swing operation.For voltage-mode logic: reset operation is required.
3. To reduce the noise effect
r1 r2r1
c1 c1
(a) (b)
1 1
11cra =τ1.
2.
2
11 1
2b r cr
r rτ
+=
2
11
2b inV r
r rV
+=
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3. Immunity of noise in current-mode logic
Current-mode loop in steady state can be approximated by a resistor loop.Node a1 has voltage V1, which is subjected to a noise ΔV.
Noise in high-branch:
Noise in low-branch:
a1r1
a1
r1
1rrr
VV
total
srs
−=
ΔΔ
v1
1rrr
VV
total
srs
−−=
ΔΔ
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Basic Design blocks of CMDL
S0
Clock’
a0
a0’
b0
b0’
a0
a0’
b0
b0’
Si
bi
bi’
ai
ai’
Clock
Si
bi
bi’
ai
ai’
Si’
o
o’Clock
o
o’
Rs
CMDF CMDG CMDL
LVSF LVSG LVSL
First stage Last stageMiddle stages
LVS:
CMDL:
Thru-gate
To connect primary inputs
To connect primary outputs
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Design rules for CMDL
The internal and output nodes are low swing, and the output must be greater than 0.1v (For Vdd=1.0v)
To guarantee the low swing outputs:For any input pattern, the differential inputs must be connectedthrough a shunt resistor or a closed transistor.
To guarantee the differential output is larger than 0.1v:For each pair of differential output, there shall be no other shunt resistors or close transistors on the active path.
The DCN can have multiple inputs and multiple outputs.Any path from the input to output has at most six stages of logic.
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CMDL examples
a0
a0’
a1
a1’
S
S’
b
b’CMDF
a0
a0’
b
b’
S
CMDL
CMDFa1
a1’
S’
out
out’
a’
a
1
0
b
b’
CMDFa’
a
out
out’
b
CMDL
CMDF1
0
b’
2-inputs NAND gate in CMDL
2:1 multiplexer in CMDL
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CMDL examples
a’
a
0
1
b’
b
out
out’CMDF
a’
a
out
out’
b’
CMDL
CMDF0
1
b
2-inputs NOR gate in CMDL
b
b’
out
out’
a’
a
a
a’
CMDFa’
a
out
out’
b
CMDL
CMDFa
a’
b’
2-inputs XOR gate in CMDL
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4:1 MUX in CMDL
a0
a0’
a1
a1’
b0
S0 S1
S0’
a2
a2’
a3
a3’
S0
S0’
S1’
S1
S1’
b0’
b1
b1’
out
out’S0’
CMDFout
out’CMDL
CMDF
CMDGa0
a0’
a1
a1’
S0 S1
S0’
CMDF
CMDF
a2
a2’
a3
a3’
S0
CMDG
S1’
CMDL examples
When S0=1, S1=1, shunt transistor is needed to maintain the low swing at b1,b1’
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CMDL examples2-bit adder in CMDL
Controlled shunt resistor is used to avoid multiple shunts along Cin Cout path
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OutlineIntroductionCurrent-Mode Differential Logic (CMDL)
Basic ConceptsStructure of CMDLExamples
Design Cases32-bit Multiplexer8-bit shifter16-bit adder
Performance comparisonConclusions and future work
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32-bit MultiplexerUse 4:1 MUX as building block.Build 16:1 MUX with five 4:1 MUX.Build 32:1 MUX with two 16:1 MUX and one 2:1 MUX.Maximal logic depth is five.
4:1 4:1 4:1 4:1
4:1
S0’
CMDFoutout’
CMDF
CMDGa0
a0’
a1
a1’
S0 S1
S0’
CMDF
CMDF
a2
a2’
a3
a3’
S0
CMDGS1’
S0’
CMDGoutout’
CMDG
CMDGa0
a0’
a1
a1’
S0 S1
S0’
CMDG
CMDG
a2
a2’
a3
a3’
S0
CMDGS1’
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8-bit rotator/shifterAdopt the barrel shifter structure proposed in [Pereira et al. 1995].Can left rotate or shift the operand by 0 to 7 bits.Maximal logic depth is 4.Function correctness:
proper input pattern
Function table for RO/PA
ls lr c1 c2 Out action0 0 1 0 In1
In20-
No shift1 1 0 1 rotate1 0 0 0 Padding 00 1 1 1 Not
allowed
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16-bit carry-skip adderTwo kinds of cells:
Carry-skip cell (CS)Full adder cell (FA)
Primary inputs:Carry propagation signal: PiCarry generation signal: GiCarry kill signal: KiCarry-skip control signal: Pij
Maximal logic depth is six.
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Sense amplifierA traditional sense amplifier from textbooksWhen En signal is high, sense amp is pre-charged to low.The cross-coupled PMOS and NMOS pair provide positive feed-back loop for quick restoring.
En
En En
In In’
Out’ Out
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OutlineIntroductionCurrent-Mode Differential Logic (CMDL)
Basic ConceptsStructure of CMDLExamples
Design Cases32-bit Multiplexer8-bit shifter16-bit adder
Performance comparisonConclusions and future work
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Experiment settingsThree different logics are compared:
CMOS logic (standard cell), LVS logic CMDL.
Three design cases are compared:32-bit MUX, 8-bit shifter and 16-bit adder
Simulation tool: HspiceLibrary: TSMC-90nm technologyInputs and outputs:
inverters are used as inputs drivers and loads.Cycle time for each logic:
determined by the worst case delay.Sense amp outputs:
The high voltage of sense amp is greater than 0.8v.Power measurements:
100 randomly generated input patterns are used.
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Performance comparison
CMDL operates faster than CMOSDifferential small signal.Diffusion Connected Network
The speed of CMDL is comparable to LVSSlower in adder case by 9%.With the elimination of reset stage, the differential output needs to be charged from the opposite voltage level instead of zero.
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Performance comparison
CMDL is more power efficient than LVSPower saving: 15%, 14% and 40% for three cases.Due to the elimination of reset network
CMDL dissipates more power than CMOSPower increase: 14% and 23% for shifter and adder.Static current: ~10uAMore overhead comes from inputs, loads and sense amps.
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Performance comparison
CMDL has the best delay*power metric.The reduction is up to 50%.The delay2*power is also reduced by up to 80%.
CMDL has the smallest number of transistors.Usage of Diffusion Connected NetworkElimination of the reset network
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Waveforms of different logicsCMDL waveform LVS waveform
CMOS waveform
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Conclusions and future work
The effectiveness of CMDL is demonstrated by three design cases.Simulation results show that:
CMDL can achieve much better delay*power and delay2*power.
Next steps:Detailed experiments of energy overhead of CMDL on small circuitNoise test of CMDLTechnology scalingOther possible alternative architectures
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Thank you
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