High Performance ADCs for 5G · Wu, ISSCC 2016 4 GS/s 56dB SNDR 300mW Case study: Industry...
Transcript of High Performance ADCs for 5G · Wu, ISSCC 2016 4 GS/s 56dB SNDR 300mW Case study: Industry...
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High Performance ADCs for 5G
Benjamin Hershberg
imec, Leuven, Belgium
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5G NR FR2:ADC REQUIREMENTS
Benjamin Hershberg High Performance ADCs for 5G 2 of 60
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5G Bandwidth Specs
◼ Channel: 50MHz, 100MHz, 200MHz, 400MHz
◼ Max. Aggregation: 800MHz
◼ Widest Band: 3.25GHz (24.25GHz – 27.50GHz)
◼ Agg. 28GHz Bands: 5.25GHz (24.25GHz – 29.50GHz)
...and need >1.5x more bandwidth to relax anti-alias filter.
5G Modulation Specs
◼ QPSK, 16 QAM, 64 QAM, 256 QAM
◼ Future: 1024 QAM
5G NR FR2: 3GPP specs
Benjamin Hershberg High Performance ADCs for 5G 3 of 60
[3GPP, 2019]
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Translation into ADC specs depends heavily on system-level choices
◼ Receiver chain SNR budget
◼ % of standard supported
Let’s see what we can do across the large range of likely 5G ADC specs:
◼ Resolution: 7 – 13 bits
◼ Speed: 400 MS/s – 12 GS/s
◼ Linearity: 65 dB – 85 dB SFDR
(needs to cover Mobile-Terminal, Base-Station, etc...)
5G NR FR2: ADC specs
Benjamin Hershberg High Performance ADCs for 5G 4 of 60
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CH
AN
NEL
AG
G.
CH
AN
NEL
BAN
D
5G NR FR2: ADC SoTA
Benjamin Hershberg High Performance ADCs for 5G 5 of 60
[Murmann, 2019]
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Linearity SoTA
Benjamin Hershberg High Performance ADCs for 5G 6 of 60
[Murmann, 2019]CH
AN
NEL
AG
G.
CH
AN
NEL
BAN
D
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SFDR/THD specs can be harder than SNR specs!
◼ Noise power gets spread across large bandwidth
◼ Distortion power remains concentrated at specific frequencies
Linearity considerations
Benjamin Hershberg High Performance ADCs for 5G 7 of 60
dB
fS1/2
dB
fS2/2
dB
freqfS1/2 fS2/2
Continuous-time input spectrum:
Low speed ADC after sampling:
High speed ADC after sampling:
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Beamforming requires many ADCs
◼ Power efficiency
◼ Area efficiency
Reconfigurability
◼ Large variation in required performance depending on mode (e.g. 50MHz vs. 800MHz BW)
More considerations
Benjamin Hershberg High Performance ADCs for 5G 8 of 60
Vaz
ISSCC
2017
Devarajan
ISSCC
2017
Straayer
ISSCC
2016
Wu
ISSCC
2016
Ali
VLSI 2016
Architecture Pipe-SAR Pipeline Pipeline Pipeline Pipeline
Sampling rate [Gsps] 4 10 4 4 5
Technology [nm] 16 28 65 16 28
ENOB Nyquist [bit] 9.2 8.8 8.9 9.0 9.3
SFDR Nyquist [dB] 67.0 64 64.0 68.0 70
Power [mW] 513 2900 2214 300 2300
FoMWalden [fJ/c.step] 214 631 1130 145 709
FoMSchreier [dB] 153 147 145 154 148
Area [mm²] 1.04 20.2 11.0 0.34 14.4
Industry SoTA
500mW 4GS/s ADC in 0.5mm2
x 128 element digital beam-forming= 64 Watts= 64 mm2
An industrial solution today:
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Case Study: MIMO Transceiver
Benjamin Hershberg High Performance ADCs for 5G 9 of 60
[Jann ISSCC 2019]
◼ First fully-integrated 5G TRX
Modest ADC specs
◼ 400 MS/s
◼ 7.7 ENOB
◼ ...but ADC is still biggest slice of RX power!
Many ADCs
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High speed (400MS/s - 12GS/s)
Medium resolution (7 - 13b)
High linearity (65dB - 85dB)
Low power
Low area
Conclusions: 5G NR FR2 requirements
Benjamin Hershberg High Performance ADCs for 5G 10 of 60
Industry SoTA can meet these specs...
...but not necessarily with acceptable power / area.
☺
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GETTING TO GIGA-SAMPLE SPEEDS
Benjamin Hershberg High Performance ADCs for 5G 11 of 60
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Two possible strategies:
1. Fast single-channel
Practical technology speed limits
Many clocking overheads don’t scale w/ clock
Limited architecture choices
Giga-samples: how do we get there?
Benjamin Hershberg High Performance ADCs for 5G 12 of 60
2 GS/sVIN
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Two possible strategies:
1. Fast single-channel
Practical technology speed limits
Many clocking overheads don’t scale w/ clock
Limited architecture choices
2. Interleave several slower channels
Interleave errors (spurs)
Easy to correct: Offset, Gain
Hard to correct: Skew, Bandwidth
Larger input load to drive
Larger area
Giga-samples: how do we get there?
Benjamin Hershberg High Performance ADCs for 5G 13 of 60
2 GS/sVIN100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/s
100 MS/sVIN
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Combine both strategies
◼ First: maximize channel speed
◼ Then: interleave as necessary
Giga-samples: how do we get there?
Benjamin Hershberg High Performance ADCs for 5G 14 of 60
2 GS/sVIN1 GS/s
1 GS/sVIN
Core mission statement:
Maximize per-channel speed!
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Pipelining
◼ Appears in all medium/high resolution giga-sample ADCs
◼ Break task into smaller pieces
◼ Pass incomplete result along for more processing
Minimize # of operations in critical timing path
◼ Sample
◼ Quantize
◼ Amplify
Pipelining
Benjamin Hershberg High Performance ADCs for 5G 15 of 60
Stage 2Stage 1 Stage 3 Stage 4 Backend
3 3 3 3 4
VIN
Time Alignment & Digital Error Correction12
DOUT
3b flash sub-ADC
3
T/H Σ x4
3b sub-DAC
VIN VRES
DOUT
Example 3b/stage Pipelined ADC
• 2b/stage of quantization• 1b/stage of redundancy (error correction)
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Case study: Deep Pipeline
Benjamin Hershberg High Performance ADCs for 5G 16 of 60
1.5b/stage Flash ADC Quantizer
☺ Fast! Minimum set of actions per stage
Many stages / residue amplifiers
[Wu, ISSCC 2016]
System 4 GS/s
Channel 1 GS/s
SNDR 56 dB
SFDR 68 dB
Power 300 mW
FoMW 146 fJ/cs
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Case study: Pipelined SAR
Benjamin Hershberg High Performance ADCs for 5G 17 of 60
SAR as a sub-ADC
☺ Fewer stages / amplifiers
☺ Power efficient sub-ADC
Slower channel speed
[Vaz, ISSCC 2017]
System 4 GS/s
Channel 500 MS/s
SNDR 57 dB
SFDR 67 dB
Power 513 mW
FoMW 214 fJ/cs
16nm
Area = 1mm2
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Fast frontend, slower backend
☺ Fast frontend minimizes interleave factor
☺ Interleaved SARs improve backend efficiency
Frontend amplifiers still power-hungry
Case study: Hybrid Pipeline
Benjamin Hershberg High Performance ADCs for 5G 18 of 60
[Brandolini, JSSC 2015]
System 5 GS/s
Channel 2.5 GS/s
SNDR 52 dB
SFDR 58 dB
Power 150 mW
FoMW 96 fJ/cs
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AMPLIFICATION: THE HIDDEN BOTTLENECK
Benjamin Hershberg High Performance ADCs for 5G 19 of 60
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Pipelining requires passing along analog residues
To go high speed, you need good amplifiers!
Amplification
Benjamin Hershberg High Performance ADCs for 5G 20 of 60
Stage 2Stage 1 Stage 3 Stage 4 Backend
3 3 3 3 4
VIN
Time Alignment & Digital Error Correction12
DOUT
3b flash sub-ADC
3
T/H Σ x4
3b sub-DAC
VIN VRES
DOUT
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Class-A opamps in nanoscale CMOS
Not enough voltage headroom
Poor efficiency / technology scaling
Requires a special high-voltage supply
Eliminates all hope of high efficiency
But lacking better options, this is still what many in industry use...
Case study: Industry Gigasample ADCs
Benjamin Hershberg High Performance ADCs for 5G 21 of 60
[Ali, JSSC 2014]
2.5V
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Wu, VLSI 2013
◼ 5.4GS/s
◼ 52dB SNDR
◼ 500mW
Brandolini, JSSC 2015
◼ 5GS/s
◼ 52dB SNDR
◼ 150mW
Wu, ISSCC 2016
◼ 4 GS/s
◼ 56dB SNDR
◼ 300mW
Case study: Industry Gigasample ADCs
Benjamin Hershberg High Performance ADCs for 5G 22 of 60
• All 3 ADCs use the same residue amplifier on 1.8V
• Core circuits on 1.4V/0.4V
[Wu, VLSI 2013]
Fs 5.4 GS/s
SNDR 52 dB
Power 500 mW
[Brandolini, JSSC 2015]
Fs 5 GS/s
SNDR 52 dB
Power 150 mW
[Wu, ISSCC 2016]
Fs 4 GS/s
SNDR 56 dB
Power 300 mW
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Wu, VLSI 2013
◼ 5.4GS/s
◼ 52dB SNDR
◼ 500mW
Wu, ISSCC 2016
◼ 4 GS/s
◼ 56dB SNDR
◼ 300mW
Brandolini, JSSC 2015
◼ 5GS/s
◼ 52dB SNDR
◼ 150mW
Case study: Industry Gigasample ADCs
Benjamin Hershberg High Performance ADCs for 5G 23 of 60
8 high-performance amps
2 high-performance amps
2 high-performance amps14 low-performance amps
[Wu, VLSI 2013]
Fs 5.4 GS/s
SNDR 52 dB
Power 500 mW
[Brandolini, JSSC 2015]
Fs 5 GS/s
SNDR 52 dB
Power 150 mW
[Wu, ISSCC 2016]
Fs 4 GS/s
SNDR 56 dB
Power 300 mW
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Amplification: The Hidden Bottleneck
Benjamin Hershberg High Performance ADCs for 5G 24 of 60
Architectural Freedom
Calibration Complexity
Power Efficiency
Linearity
Performance
Input Swing
High Voltage Supply
Amplifier Bottleneck
Architectural Freedom
Output Swing
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Class-A opamps will never be good in scaled CMOS
◼ Severely constrains ADC design freedoms
◼ 2010’s were the era of the (amplifier-less) SAR ADC
A new approach is needed!
Conclusions: Amplifier Bottleneck
Benjamin Hershberg High Performance ADCs for 5G 25 of 60
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EMERGING AMPLIFICATION SOLUTIONS
Benjamin Hershberg High Performance ADCs for 5G 26 of 60
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Open loop
Gm-C integrator
Gm-R amplifier
◼ Charge-pump based
Feedback
Ring amplifier
◼ Zero-crossing based circuit
◼ Charge-steering amplifier
◼ Digital amplifier
Emerging Amplification Solutions
Benjamin Hershberg High Performance ADCs for 5G 27 of 60
Found in state-of-the-art Gigasample ADCs
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Amplifier Wishlist
Benjamin Hershberg High Performance ADCs for 5G 28 of 60
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Basic idea: Integrate current GmVRES onto load capacitor
☺ Fast (open-loop)
☺ Fully dynamic (switchable)
☺ Inherent filtering (sinc)
☺ Good efficiency
Poor linearity
Small input swing
Small output swing
Sensitive to jitter
Sensitive to PVT
Gm-C integrator
Benjamin Hershberg High Performance ADCs for 5G 29 of 60
GmVRES
ΦA
VRES
ΦR
VOUT
CLGm
ΦA
tR tA
VO
UT
time
Gm · taCL
AV =
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Case Study: Gm-C Integrator
Benjamin Hershberg High Performance ADCs for 5G 30 of 60
Channel:
Gm-C:
[Vaz, ISSCC 2017]
System 4 GS/s
Channel 500 MS/s
SNDR 57 dB
SFDR 67 dB
Power 513 mW
FoMW 214 fJ/cs
Tunable integration time:
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Gm-R amplifier
Benjamin Hershberg High Performance ADCs for 5G 31 of 60
Basic idea: RC settle voltage GmVRESRL across load capacitor
☺ Even faster! (no pre-clearing)
☺ Fully dynamic (switchable)
☺ Good efficiency
Moderate PVT sensitivity
Poor linearity
Small input swing
Small output swing
tA
VO
UT
time
GmVRESVRES VOUT
CLGm
ΦA
RL
AV = Gm · RL
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Case study: Gm-R Amplifier
Benjamin Hershberg High Performance ADCs for 5G 32 of 60
[Jiang, ISSCC 2019]
System 1 GS/s
Channel 1 GS/s
SNDR 60 dB
SFDR 75 dB
Power 8 mW
FoMW 9 fJ/cs
Current SoTA for single-channel gigasample ADCs
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CLOAD
OUTmINp
feedback
VDZ
Ring Amplifier
Benjamin Hershberg High Performance ADCs for 5G 33 of 60
Basic idea: Start in a high efficiency but unstable state and then dynamically stabilize with large-signal feedback
[Hershberg, JSSC 2012]
☺ High efficiency
☺ High speed
☺ Wide output swing
☺ Excellent linearity
☺ Scales with digital
☺ Fully dynamic (switchable)
Moderate PVT sensitivity [Lagos, JSSC 2019]
[Lim, JSSC 2015 (1)]
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Ring Amplifier
Benjamin Hershberg High Performance ADCs for 5G 34 of 60
CLOAD
OUTmINp
feedback
VDZ
p1
p2
p3
p2
Transient, large signal paradigm
The AC view
◼ Make p1 & p2 as fast as possible
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Ring Amplifier
Benjamin Hershberg High Performance ADCs for 5G 35 of 60
CLOAD
OUTmINp
feedback
VDZ
p1
p2
p3
p2
Transient, large signal paradigm
The AC view
◼ Make p1 & p2 as fast as possible
◼ Dynamically reduce p3
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Ring Amplifier
Benjamin Hershberg High Performance ADCs for 5G 36 of 60
CLOAD
OUTmINp
feedback
VDZ
p1
p2
p3
p2
Transient, large signal paradigm
The AC view
◼ Make p1 & p2 as fast as possible
◼ Dynamically reduce p3
◼ ring oscillator → ring amplifier
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Ring Amplifier
Benjamin Hershberg High Performance ADCs for 5G 37 of 60
CLOAD
OUTmINp
feedback
VDZp3
VOV
VOV
Transient, large signal paradigm
The DC / transient view
◼ VOV initially maximum
Slew-rate at theoretical max. ☺
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Ring Amplifier
Benjamin Hershberg High Performance ADCs for 5G 38 of 60
Transient, large signal paradigm
The DC / transient view
◼ VOV initially maximum
Slew-rate at theoretical max. ☺
◼ VOV dynamically reduced to adjust P3
Reduces VDSAT → swing/linearity ☺
Increases ro → gain/linearity ☺
Reduces gm → noise filtering ☺
CLOAD
OUTmINp
feedback
VDZp3
VOV
VOV
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[Hershberg, ISSCC 2019 (1)]
System 3.2 GS/s
Channel 800 MS/s
SNDR 63 dB
SFDR 80 dB
Power 61.3 mW
FoMW 19 fJ/cs
Case study: Ring Amplifier
Benjamin Hershberg High Performance ADCs for 5G 39 of 60
VDD
DZP
EN
DZN
VSS
EN_i
EN_i
EN
EN
OUTm
INp
VDD
DZP
EN
DZN
VSS
EN_i
EN_i
EN
EN
OUTp
INm
EN
VDDEN
Vs2p2
Vs2m2
Vs2p1
Vs2m1
VDD
VSS
MCM2
OUTp
B1
CFB
CSMALLCBIG
ENCSENSE
EN_i
EN_iEN_i
Trapped Charge CMFB
Dz_nmos[7:0]7
VDD DZN
EN
Dz_pmos[7:0]7
VSS DZP
EN
Trapped-Charge Bias Control
CFBOUTm
CSENSE
MCM1
Order-of-magnitude improvement in SoTA
36 ringamps in system
◼ Bottleneck solved?
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Option 1: Design with extra margin
☺ Calibration free
Requires some sacrifice in speed
Still can achieve SoTA performance
◼ 3 stage ringamp [Lim, JSSC 2015 (2)]
◼ 4 stage ringamp [Lim, VLSI 2017]
Ringamp Robustness Techniques
Benjamin Hershberg High Performance ADCs for 5G 40 of 60
[Lim, JSSC 2015]
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Option 2: Use background tracking or calibration techniques
☺ Optimum performance
Extra analog/digital complexity
Ringamp Robustness Techniques
Benjamin Hershberg High Performance ADCs for 5G 41 of 60
AOL
β
+IN OUTX+ -
+‒
v/σ
PIP
ELINE
B
ACK
END
“bin” 1
“bin” N
estimator equations
𝐷 𝑉𝑥
𝐷 𝑉𝑥 𝐷 𝑉𝑜𝑢𝑡
bias control
VCM
v/σ factor estimation
1σ = 0.3 mV
𝑆𝐷𝑅
mean erfinv x
mean erfinv x
mean erfinv x
mean erfinv x
cal ADC
mux
demux
𝐴 𝑂𝐿
𝑆𝐷𝑅 𝑉𝑂𝑈𝑇 ,𝑉𝑋
𝐴𝑂𝐿 𝑉𝑂𝑈𝑇 ,𝑉𝑋
[Hershberg, ISSCC 2019 (1)]
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Open-loop where it makes sense
◼ E.g. for very fast amplification
Ringamps for everything else
◼ Any input swing, any output swing
◼ Any resolution, any speed
◼ All circuits: ADC, VGA, Filter, PLL, etc.
Conclusion: Emerging Amplification
Benjamin Hershberg High Performance ADCs for 5G 42 of 60
GmVRESVRES VOUT
CLGm
ΦA
RL
CLOAD
OUTmINp
feedback
VDZ
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DESIGNING FORRECONFIGURABILITY
Benjamin Hershberg High Performance ADCs for 5G 43 of 60
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Wide range of channel bandwidths and modulations:
5G Bandwidth Specs
◼ Channel: 50MHz, 100MHz, 200MHz, 400MHz
◼ Max. Aggregation: 800MHz
◼ Widest Band: 3.25GHz (24.25GHz – 27.50GHz)
◼ Agg. 28GHz Bands: 5.25GHz (24.25GHz – 29.50GHz)
5G Modulation Specs
◼ QPSK, 16 QAM, 64 QAM, 256 QAM
◼ Future: 1024 QAM
➔ A reconfigurable multi-standard ADC is a clear advantage
5G NR FR2 specs revisited
Benjamin Hershberg High Performance ADCs for 5G 44 of 60
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Run-time
Speed
◼ Resolution
Design-time
Architecture
ADC Reconfigurability
Benjamin Hershberg High Performance ADCs for 5G 45 of 60
= most relevant for 5G
Speed Reconfigurability
[Hershberg, ISSCC 2019 (2)]
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Motivation: constant power efficiency
2 ingredients required
◼ Event-driven control (clocking)
◼ Fully-dynamic power consumption
Fully-dynamic = no static power
“Next-gen” amplifiers support this
◼ Gm-C
◼ Gm-R
◼ Ringamp
Speed Reconfigurability
Benjamin Hershberg High Performance ADCs for 5G 46 of 60
Ringamp with power-gating function
[Lagos, JSSC 2019]
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Conventional: Synchronous 2-phase non-overlapping clock tree
◼ Simple & effective at lower speeds
◼ But many hidden drawbacks at high speed
With improvements in amplification tech., clocking becomes the new bottleneck
Event-Driven Control: Deep Pipeline
Benjamin Hershberg High Performance ADCs for 5G 47 of 60
Phase 1 delayed
Phase 2 delayed
Phase 1
Phase 2
cINpSTG1
INm
c
Local Clkgen
STG2
Local Clkgen
STG3
Local Clkgen
STG4
Local Clkgen
STG5
Local Clkgen
STG6
Local Clkgen
BACKEND
Local Clkgen
c
master clock
Global Clkgen
[Lagos, CICC 2017]
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Local “Stage Control Units” connected by inter-stage control busses
◼ Communication
◼ Driving local circuits
☺ Correct-by-construction
☺ Minimal global routing
☺ Interleaving advantages
☺ Less sampling jitter
☺ Faster (less timing overhead)
Event-Driven Control: Deep Pipeline
Benjamin Hershberg High Performance ADCs for 5G 48 of 60
[Hershberg, ISSCC 2019 (2)]
VCM
1.5bsub-ADC
DOUT[1:0]
subRingamp+
-Ringamp+
-
sub-ADC latch
sample REQ sample REQ
1.5bsub-DAC
track N
track early N
flush REQ
stagecontrol
unittrack early N+1 (ACK)track early N (ACK)
flush ACK
stagecontrol
unit
STAGE N+1STAGE N
VCM
STAGE N-1
amplify N
sub-ADC latch
flush ACKcINp STG1
1.5b
CU=64fF
STG21.5b
CU=32fF
c
master clock
BACKEND1.5b + 3b
CU=32fF
STG31.5b
CU=32fF
STG41.5b
CU=32fF
STG51.5b
CU=32fF
STG61.5b
CU=32fF
STG71.5b
CU=32fF
INm
c
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Internal “chain-reaction” of processing is independent of external clock rate
◼ 1MS/s same as 1GS/s
☺ Enables fully-dynamic operation
☺ Auto maximizes track time
☺ Removes many leakage issues
Event-Driven Control: Deep Pipeline
Benjamin Hershberg High Performance ADCs for 5G 49 of 60
[Hershberg, ISSCC 2019 (2)]
trackquantize
amplify track
trackquantize
amplify track
. . . .
. . . .
trackquantize
amplify
Conventional
clkmax
clkmax / 2
trackquantize
amplify track
trackquantize
amplify track
. . . .
. . . .
trackquantize
amplifyclkmax
clkmax / 2
Event-driven
Analog data enters Analog data exits
Analog data enters Analog data exits
window expands
constant
-
☺ More efficient (less power)
☺ Reconfigurable behavior
☺ No limit to # of clocks/phases
Must be careful about deadlocks
Validation effort increased
Event-Driven Control: Deep Pipeline
Benjamin Hershberg High Performance ADCs for 5G 50 of 60
[Hershberg, ISSCC 2019 (2)]
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** Sneak Peek! **
General-purpose solution
◼ Discrete-time comparator-based
[Kull, JSSC 2013]
◼ Can sub-divide into dirty/clean replicas for low-noise and high-accuracy
☺ Low power
☺ General purpose
Still requires some decap area
Fully Dynamic Reference Regulation
Benjamin Hershberg High Performance ADCs for 5G 51 of 60
c
c
master clock
INm
c
INp
c
VREFP ext. c
VCM ext. c
VREFM ext.
VREFP dirtyVREFP cleanVCMVREFM dirtyVREFM clean
reference regulator
BACKEND1.5b + 3b
CTOT=256fF
STG11.5b
CTOT=256fF
STG21.5b
CTOT=128fF
STG31.5b
CTOT=128fF
STG41.5b
CTOT=128fF
STG51.5b
CTOT=128fF
STG61.5b
CTOT=128fF
STG71.5b
CTOT=128fF
Deep pipeline with dirty/clean reference replicas:
VDD
precharge_i
CP
VSS
precharge
CM
Charge source / sink
CR
VREF_extprecharge
+
replica out
connect
connect_i
Discrete-time regulation circuit:
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Design-time circuit re-use
◼ Faster time-to-market
◼ Less manpower
Simple, low resolution stages
◼ Use “cheap” high performance amplifiers
◼ Can simply “chain” together using asynchronous, event-driven control protocols
Architecture Reconfigurability
Benjamin Hershberg High Performance ADCs for 5G 52 of 60
STG21.5b
CU = 128fF
STG31.5b
CU = 64fF
STG41.5b
CU = 32fF
BACKEND9b
CU = 32fF
Inventory of low-resolution, fully-dynamic building blocks
BACKEND9b
CU = 32fF
9
c
VINSTG31.5b
CU = 64fF
c
clk
2c
STG41.5b
CU = 32fF
2DOUT
13b ADC (x4)for Base-station Applications[Hershberg, ISSCC 2019 (1)]
STG11.5b
CU = 200fF
BACKEND9b
CU = 32fF
9
c
VIN STG21.5b
CU = 128fF
STG31.5b
CU = 64fF
c
clk
2 2 2c
STG11.5b
CU = 200fF
STG41.5b
CU = 32fF
2DOUT
11b ADCfor Mobile-terminal Applications[Hershberg, ISSCC 2019 (2)]
Easily adapted to many resolution &
speed requirements
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SUMMARY & CONCLUSION
Benjamin Hershberg High Performance ADCs for 5G 53 of 60
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Final Summary
Benjamin Hershberg High Performance ADCs for 5G 54 of 60
1 GS/s
1 GS/s
1 GS/s
1 GS/s
1 GS/s
VIN
For best performance at high speeds:
First maximize the per-channel speed...
...then interleave as necessary
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Final Summary
Benjamin Hershberg High Performance ADCs for 5G 55 of 60
1 GS/s
Pipelining can maximize the per-channel speed
BACKEND9b
CU = 32fF
9
c
VIN STG21.5b
CU = 128fF
STG31.5b
CU = 64fF
c
clk
2 2 2c
STG11.5b
CU = 200fF
STG41.5b
CU = 32fF
2DOUT
But it isamplifier intensive!
Luckily, new amplification techniques
are now available
CLOAD
OUTmINp
feedback
VDZ
Ringamp
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Final Summary
Benjamin Hershberg High Performance ADCs for 5G 56 of 60
ADC Reconfigurability
Run-time
Constant energy per conversion for multi-standard use Asynchronous-
event driven timing control
Fully dynamic power use
Design-time
Building block reuse for reduced
design effort
Enablers:
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Closing the Gap
Benjamin Hershberg High Performance ADCs for 5G 57 of 60
Industry SoTA R&D SoTA
Top Level
CH0
CH1
DOUT[N:0]
CH2
CH3
D0[N:0]
D1[N:0]
D2[N:0]
D3[N:0]
CLKIN
controller mux
BU
F
VINBUF
Vaz
ISSCC
2017
Devarajan
ISSCC
2017
Straayer
ISSCC
2016
Wu
ISSCC
2016
Ali
VLSI 2016
Architecture Pipe-SAR Pipeline Pipeline Pipeline Pipeline
Sampling rate [Gsps] 4 10 4 4 5
Technology [nm] 16 28 65 16 28
ENOB Nyquist [bit] 9.2 8.8 8.9 9.0 9.3
SFDR Nyquist [dB] 67.0 64 64.0 68.0 70
Power [mW] 513 2900 2214 300 2300
FoMWalden [fJ/c.step] 214 631 1130 145 709
FoMSchreier [dB] 153 147 145 154 148
Area [mm²] 1.04 20.2 11.0 0.34 14.4
Hershberg
ISSCC
2019
Architecture Pipeline
Sampling rate [Gsps] 3.2
Technology [nm] 16
ENOB Nyquist [bit] 10.0
SFDR Nyquist [dB] 73.3
Power [mW] 61
FoMWalden [fJ/c.step] 19
FoMSchreier [dB] 166
Area [mm²] 0.194
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References (1)
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3GPP, 2019 3GPP, “5G NR release 15”, 2019. [Online]. Available: https://www.3gpp.org/release-15
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