HIGH-K-INAS METAL-OXIDE-SEMICONDUCTOR CAPACITORS

FORMED BY ATOMIC-LAYER DEPOSITION

A Dissertation

Submitted to the Graduate School

of the University of Notre Dame

in Partial Fulfillment of the Requirements

for the Degree of

Doctor of Philosophy

by

Dana C. Wheeler

Alan Seabaugh, Director

Graduate Program in Electrical Engineering

Notre Dame, Indiana

April 2009

© Copyright by

DANA C. WHEELER

2009

All rights reserved

HIGH-K-INAS METAL-OXIDE-SEMICONDUCTOR CAPACITORS

FORMED BY ATOMIC-LAYER DEPOSITION

Abstract

by

Dana C. Wheeler

Atomic- layer deposition is used to grow HfO2 and Al2O3 thin films on InAs

substrates to form high-k-InAs metal-oxide-semiconductor capacitors. Devices are

formed using various substrate pretreatments, film growth temperatures and thicknesses,

contact metals, and post-metallization anneals. X-ray photoelectron spectroscopy,

transmission electron microscopy, and ellipsometry are used to physically characterize

the films, while current-voltage and impedance measurements are used for electrical

characterization. Hafnium dioxide films with equivalent silicon dioxide thicknesses as

low as 0.76 nm are reported with leakage current densities as low as 9.2 × 10-2 A/cm2 at

+1 V gate bias. Interface trap densities are measured by the Terman method to be in the

1013 cm-2-eV-1 range at midgap. TEM and XPS data suggest the high trap densities in

Dana C. Wheeler

the HfO2-InAs capacitors are associated with an interfacial layer likely composed of

native indium and arsenic oxides. XPS measurements indicate that these oxides are not

present after the Al2O3 ALD process, eliminating a source of Fermi- level pinning and

reducing the number of interface traps. The devices fabricated in this work are compared

to other III-V MOS work and International Technology Roadmap for Semiconductors

performance targets to assess the viability of metal-high-k-InAs MOS gate stacks.

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CONTENTS

FIGURES ............................................................................................................................iv

ACKNOWLEDGEMENTS ..............................................................................................xvi

CHAPTER 1: INTRODUCTION....................................................................................... 1 1.1 Historical background ....................................................................................... 1 1.2 Motivation......................................................................................................... 3 1.3 Prior art ............................................................................................................. 6 1.4 State of the art ................................................................................................... 7 1.5 Organization...................................................................................................... 8

CHAPTER 2: MODELING AND MEASUREMENT OF MOS CAPACITORS ........... 10 2.1 Basic MOS capacitor structure and operation ................................................ 10 2.2 MOS capacitance-voltage modeling ............................................................... 12 2.3 MOS current-voltage modeling ...................................................................... 31 2.4 Measurement of MOS capacitor impedance ................................................... 42

2.4.1 Impedance measurement connection configurations ............................. 43 2.4.2 Impedance measurement calibration...................................................... 48 2.4.3 Comparison of connection configurations and calibration procedures.. 49 2.4.4 Influence of PIA settings on impedance characteristics ........................ 57

2.5 Correction of measured impedance characteristics for series resistance ........ 65 2.6 Measurement of MOS capacitor leakage current ............................................ 76 2.7 Comparison of measured characteristics to prior art ...................................... 82

CHAPTER 3: HFO2-INAS MOS CAPACITORS............................................................ 84 3.1 Fabrication procedure and sample matrices.................................................... 84 3.2 Frequency dependence of metal-HfO2-InAs MOS capacitor C-V

characteristics ................................................................................................ 92 3.3 Temperature dependence of metal-HfO2-InAs MOS capacitor C-V

characteristics ................................................................................................ 98 3.4 Dependence of film thickness on metal-HfO2-InAs MOS capacitor properties

..................................................................................................................... 114 3.5 Influence of growth temperature on metal-HfO2-InAs MOS capacitor

properties ..................................................................................................... 129 3.6 Influence of PMA on metal-HfO2-InAs MOS capacitor properties ............. 134 3.7 Influence of pretreatment on metal-HfO2-InAs MOS capacitor properties .. 145 3.8 Influence of gate metal on metal-HfO2-InAs MOS capacitor properties ..... 148 3.9 Summary....................................................................................................... 151

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CHAPTER 4: BILAYER HFO2-AL2O3 INAS MOS CAPACITORS ........................... 154 4.1 Fabrication procedure and sample matrices.................................................. 154 4.2 Bilayer HfO 2-Al2O3-InAs MOS capacitors .................................................. 157

4.2.1 Leakage current and interface trap reduction by inclus ion of Al2O3 ... 157 4.2.2 Role of HCl and BHF pretreatments in higk-k-InAs device performance

............................................................................................................... 163 4.2.3 Role of interfacial growth temperature and precursor in higk-k-InAs

device performance................................................................................ 166 4.3 XPS studies of Al2O3 and HfO2 ALD processes .......................................... 170 4.4 Summary....................................................................................................... 171

CHAPTER 5: CONSIDERATIONS FOR HIGH-K-INAS MOS GATE STACKS ...... 173 5.1 Scaling considerations for metal-high-k-InAs MOS gate stacks .................. 174

5.1.1 High-performance gate dielectric leakage current ............................... 174 5.1.2 High-performance gate dielectric equivalent thickness....................... 179

5.2 Interface requirements for high-k-based MOS gate stacks ........................... 181 5.3 Summary....................................................................................................... 183

CHAPTER 6: CONCLUSION ....................................................................................... 184 6.1 Summary....................................................................................................... 184 6.2 Suggestions for future research..................................................................... 185

APPENDIX A: CONFERENCE ABSTRACTS ............................................................ 187

REFERENCES ............................................................................................................... 194

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FIGURES

Figure 2.1 Energy band diagrams for MOS capacitor (n-type semiconductor) in accumulation, flatband, depletion, and inversion regimes.................................... 11

Figure 2.2 Absolute value of the surface charge density at 300 K vs. semiconductor surface potential for Si doped 6.8 × 1016 cm-3: n-type (red), p-type (green), and intrinsic (blue). ...................................................................................................... 14

Figure 2.3 Modeled LF (red), HF (green), and DD (blue) C-V curves for an example metal-HfO2-n-Si MOS capacitor........................................................................... 15

Figure 2.4 Modeled LF (red), HF (green), and DD (blue) C-V curves for an example metal-HfO2-p-Si MOS capacitor........................................................................... 17

Figure 2.5 Modeled LF C-V curves for an example metal-HfO2-n-Si MOS capacitor with semiconductor doping concentrations of 6.8 × 1015 (red), × 1016 (green), and × 1017 (blue) cm-3. .................................................................................................... 18

Figure 2.6 Modeled LF and HF C-V curves for an example metal-HfO2-n-Si MOS capacitor at 77 (blue), 300 (green), and 373 (red) K............................................. 19

Figure 2.7 Modeled LF and HF C-V curves for an example metal-HfO2-n-Si MOS capacitor with EOTs of 3.9 (red), 7.8 (blue), and 15.6 (green) nm. Capacitor EOTs are modeled by varying oxide thickness (a) and dielectric constant (b). ... 20

Figure 2.8 Modeled LF C-V curves for an example metal-HfO2-n-Si MOS capacitor with flatband voltages of -1 (green), 0 (red), and +1 (blue) V. ..................................... 21

Figure 2.9 Modeled surface potential vs. gate voltage relationship for an example metal-HfO2-n-Si MOS capacitor with an interface trap density of 0 (red) and 1 × 1012 (blue) cm-2eV-1. ..................................................................................................... 24

Figure 2.10 Modeled LF and HF C-V curves for an example metal-HfO2-n-Si MOS capacitor with an interface trap density of 0 (red) and 1 × 1012 (blue) cm-2eV-1.. 25

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Figure 2.11 Modeled LF (red), HF (green), and THF (blue) C-V curves for an example metal-HfO2-n-Si MOS capacitor with an interface trap density of 1 × 1012 cm-2eV-

1. ............................................................................................................................ 26

Figure 2.12 Comparison of LF and HF C-V curves calculated using the simple model described earlier in this section (red lines) and the Vogel model (blue symbols) for an example metal-HfO2-n-Si MOS capacitor with a 100-nm-thick oxide layer................................................................................................................................ 28

Figure 2.13 Comparison of LF and HF C-V curves calculated using the simple model described earlier in this section (red lines) and the Vogel model (blue symbols) for an example metal-HfO2-n-Si MOS capacitor with a 2-nm-thick oxide layer. 29

Figure 2.14 Comparison of LF and HF C-V curves calculated using the simple model described earlier in this section (red lines) and the Vogel model (blue symbols) for an example metal-HfO2-n-InAs MOS capacitor with a 100-nm-thick oxide layer....................................................................................................................... 30

Figure 2.15 Comparison of LF and DD C-V curves from the simple model described earlier in this section (red lines) and LF and HF curves from the Vogel model (blue symbols) for an example metal-HfO2-n-InAs MOS capacitor with a 100-nm-thick oxide layer and NC = NV = ni

1/2..................................................................... 30

Figure 2.16 Flatband diagrams of Pd-HfO2-InAs (a) and Ti-HfO2-InAs (b) heterostructures. .................................................................................................... 31

Figure 2.17 Modeled room-temperature, accumulation-regime, direct tunneling J-V characteristics for a metal-HfO2-InAs heterostructure with oxide layer thicknesses of 2.5 (green), 5.0 (blue), and 7.5 (red) nm. .......................................................... 34

Figure 2.18 Modeled room-temperature, accumulation-regime, direct tunneling J-V characteristics for a metal-HfO2-InAs heterostructure with electron tunneling barrier heights of 1.8 (green), 2.1 (blue), and 2.4 (red) eV. .................................. 35

Figure 2.19 Modeled room-temperature, accumulation-regime, direct tunneling J-V characteristics for a metal-HfO2-InAs heterostructure with oxide tunneling effective masses of 0.14 (red), 0.2 (blue), and 0.4 (green) m0. ............................. 36

Figure 2.20 Modeled accumulation-regime, direct tunne ling J-V characteristics for a metal-HfO2-InAs heterostructure at 77 (blue), 300 (green), and 373 (red) K. ..... 37

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Figure 2.21 Modeled room-temperature, accumulation-regime, thermionic J-V characteristics for a metal-HfO2-InAs heterostructure with oxide barrier heights of 1.8 (green), 2.1 (blue), and 2.4 (red) eV. .............................................................. 38

Figure 2.22 Modeled room-temperature, accumulation-regime, thermionic J-V characteristics for a metal-HfO2-InAs heterostructure with semiconductor effective masses of 0.023 (red), 0.23 (blue), and 1 m0.......................................... 39

Figure 2.23 Modeled accumulation-regime, thermionic J-V characteristics for a metal-HfO2-InAs heterostructure at 77 (blue), 300 (green), and 373 (red) K................. 40

Figure 2.24 Modeled total accumulation-regime J-V characteristics for metal-HfO2-InAs heterostructures with oxide thicknesses of 5.0 (a) and 7.5 (b) nm at 77 (blue), 300 (green), and 373 (red) K........................................................................................ 41

Figure 2.25 Schematic diagrams of top-to-top (a) and top-to-chuck (b) measurement connections to metal-high-k-InAs MOS structures. The label HI indicates connections at the probe to both HIPOT and HICUR cables and LO connects similarly to both LOPOT and LOCUR cables. ..................................................... 44

Figure 2.26 Illustration of TTT measurement configuration (a) and plan-view optical micrograph of metal-high-k-InAs MOS device wafer showing probe placement in TTT measurement configuration (b). Graphic in (a) from [74]. ........................... 46

Figure 2.27 Large-area (~1 cm2) Au-Ti-HfO2-InAs MOS heterostructure leakage current as measured between the top contact and wafer backside. ................................... 46

Figure 2.28 Illustration of TTC measurement configuration. Graphic from [74]. ........... 47

Figure 2.29 Illustration of LT measurement configuration. ............................................. 48

Figure 2.30 Current-voltage characteristic of a surface-mount 50 O resistor used as a load standard for TTC and LT calibrations (red) plotted against an ideal 50 O resistor (black). .................................................................................................................. 50

Figure 2.31 Complex- impedance-frequency characteristic of 50 O load standard measured TTC using OS calibration and PC. ....................................................... 51

Figure 2.32 Measured TTC C-V characteristics of surface-mount 1000-pF capacitor (orange) and Au-Ti-HfO2-InAs heterostructures with HfO 2 layers grown using 30 (red), 40 (blue), and 50 (green) ALD cycles using OS (dashed) and OSL (solid) calibrations. The AC signal frequency is 1 MHz with an amplitude of 25 mV rms. PC is used for both calibrations. ........................................................................... 53

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Figure 2.33 Measured equivalent parallel capacitance and conductance versus frequency of an Al-SiO2-Si MOS capacitor using TTC connection, OSL calibration, and PC with floating- (red) and grounded- (blue) guard coaxial- to-triaxial adapters. The AC signal amplitude is 25 mV rms and the DC bias is 0 V. ................................. 54

Figure 2.34 Measured TTT (lines) and TTC (symbols) C-V characteristics of surface-mount 1000 pF capacitor (orange) and Au-Ti-HfO2-InAs heterostructures with HfO2 layers grown using 30 (red), 40 (blue), and 50 (green) ALD cycles. The AC signal frequency is 1 MHz with an amplitude of 25 mV rms. OSL calibration and PC are used for both TTT and TTC. ..................................................................... 55

Figure 2.35 Measured LT-connection-method C-V characteristics of surface-mount 1000 pF capacitor with OS (dashed) and OSL (solid) calibration. The AC signal frequency is 1 MHz with an amplitude of 25 mV rms. PC is used for both OS and OSL. ...................................................................................................................... 56

Figure 2.36 Measured capacitance versus time for a Au-Ti-HfO2-InAs MOS capacitor formed using 75 ALD cycles and a 200 °C growth temperature. The DC bias is fixed at +2 V. The measurement frequency is 10 kHz and signal amplitude is 25 mV rms.................................................................................................................. 58

Figure 2.37 Measured capacitance versus time for a Au-Ti-HfO2-InAs MOS capacitor formed using 75 ALD cycles and a 200 °C growth temperature with the DC bias fixed at +2 (red), +1 (orange), 0 (lime), -1 (green), and -2 (blue) V. The measurement frequency is 10 kHz and signal amplitude is 25 mV rms. .............. 59

Figure 2.38 Measured C-V curves for a Au-Ti-HfO2-InAs MOS capacitor formed using 50 ALD cycles and a 200 °C growth temperature with the DC bias swept from +2 to -2 V using sweep delays of 0, 0.02, 0.2, 2, 20, and 60 s. Two measurements using each sweep delay are performed in a random order. The measurement frequency is 10 kHz and signal amplitude is 25 mV rms. .................................... 60

Figure 2.39 Measured C-V curves for a Au-Ti-HfO2-InAs MOS capacitor formed using 75 ALD cycles and a 200 °C growth temperature. The DC bias is swept from +2 to -2 V using a sweep delay of 10 s and sweep rates of 0.75, 0.1, and 0.01 V/s and 1.2 V/hour (3.3 × 10-4 V/s). The measurement is taken at 10 kHz (a) and 1 MHz (b). ......................................................................................................................... 62

Figure 2.40 Measured 1 MHz TTC C-V characteristic of four different Au-Ti-HfO2-InAs MOS capacitors grown using 75 ALD cycles and a temperature of 200 °C on the same wafer. The measurements are taken over the course of ~5 hours. ............... 63

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Figure 2.41 Measured 1 MHz TTC C-V characteristic of two different Au-Ti-HfO2-InAs MOS capacitors grown using 75 ALD cycles and a temperature of 300 °C on the same wafer. The measurements are taken four weeks apart. ................................ 64

Figure 2.42 Two- (a) and three- (b) element circuit models used to interpret impedance measurements........................................................................................................ 66

Figure 2.43 Current-voltage measurement of 35 × 35 (red) and 85 × 85 (blue) µm2 Au-Pd contacts on InAs. The InAs is pretreated with a 30 s dip in HCl:H2O (1:1) prior to metal evaporation. Following evaporation, the contacts are annealed at 200 °C for 1 hour in an N2 ambient. ....................................................................................... 67

Figure 2.44 Ideal complex- impedance-frequency curve for a parallel capacitance-conductance circuit with (blue) and without (red) a 100 O series resistance. ...... 68

Figure 2.45 Theoretical measured capacitance- and conductance-frequency curves for an ideal parallel capacitance-conductance circuit with (blue) and without (red) a 100 O series resistance. ................................................................................................ 69

Figure 2.46 Capacitance- and conductance-voltage curves for Au-Ti-HfO2-InAs MOS capacitors grown using 75 (a) and 50 (b) ALD cycles and an HfO 2 growth temperature of 300 °C. The measurement is taken TTC using a 1 MHz signal. The measured curves are shown with series resistance corrections of 0 (red), 10 (blue), 50 (green), and 100 (orange) O............................................................................. 70

Figure 2.47 Measured complex- impedance-frequency curves for Au-Ti-HfO2-InAs MOS capacitors with 35 × 35 (a) and 85 × 85 (b) µm2 metal contacts grown on the same wafer using 50 ALD cycles and a growth temperature of 300 °C and with no backside contact. The frequency sweeps are performed at -1 (blue), -0.5 (lime), 0 (red), +0.5 (orange), and +1 (green) VDC. The symbols are a theoretical complex-impedance-frequency curve using a three-element model with CP = 190 pF, G = 1.1 × 10-5 S, and RS = 150 O. ................................................................................ 72

Figure 2.48 Measured complex- impedance-frequency curves for Au-Ti-HfO2-InAs MOS capacitors with 35 × 35 (a) and 85 × 85 (b) µm2 metal contacts grown on the same wafer using 50 ALD cycles and a growth temperature of 300 °C and with a Ti-Au backside contact. The frequency sweeps are performed at -1 (blue), -0.5 (lime), 0 (red), +0.5 (orange), and +1 (green) VDC. ........................................................... 74

Figure 2.49 Measured capacitance (per unit area) vs. voltage for Au-Ti-HfO2-InAs MOS capacitors grown using 50 ALD cycles and a growth temperature of 300 °C with 35 × 35 (open symbols) and 85 × 85 (solid symbols) µm2 metal contacts with (red) and without (blue) Ti-Au backside contacts. The measurement is performed at 1 MHz. ............................................................................................................... 75

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Figure 2.50 Open-circuit TTC current-voltage measurement using W probe. ................. 77

Figure 2.51 Short-circuit TTC current-voltage measurement using W probe. ................. 78

Figure 2.52 Current-voltage characteristic of Au-Ti-HfO2-InAs MOS capacitor grown using 150 ALD cycles and a 250 °C growth temperature. The sweep is taken from +3 to -3 V and back using medium integration, which results in a 0.18 V/s sweep rate......................................................................................................................... 79

Figure 2.53 Current-voltage characteristic of Au-Ti-HfO2-InAs MOS capacitor grown using 75 ALD cycles and a 300 °C growth temperature plotted on a linear (blue) and logarithmic (red) scale. The sweep is taken from 0 to +3 V and back and from 0 to -3 V and back using medium integration, which results in a 0.15 V/s sweep rate......................................................................................................................... 80

Figure 2.54 Current-voltage characteristics of three different Au-Ti-HfO2-InAs MOS devices grown using 75 ALD cycles and a 300 °C growth temperature showing breakdown event (red) and one device after breakdown event (blue). The sweeps are taken from 0 to +5 V. ...................................................................................... 81

Figure 2.55 Capacitance-voltage curves from this work (blue) and [59] (red) measured at 10 kHz, 100 kHz, and 1 MHz. Devices from this work are Au-Ti-HfO2-InAs structures grown using 75 ALD cycles and a 200 °C growth temperature........... 83

Figure 3.1 Capacitance-voltage characteristics of annealed InAs-HfO2 MOS capacitor wafer 7a, grown at 200 °C with 125 ALD cycles measured quasi-statically (orange) and with 1 kHz (red) and 1 MHz (blue) AC signals. ............................. 93

Figure 3.2 Quasi-static (red) and 1 MHz (blue) C-V curves and their derivatives with respect to gate voltage for wafer 7a, an annealed Au-Ti-HfO2-InAs MOS capacitor wafer grown at 200 °C with 125 ALD cycles. ...................................... 95

Figure 3.3 Maserjian method plot to determine COX for HfO2-InAs MOS capacitor wafer 7a. The measured data is from a 1 MHz C-V characteristic. The red line is fit to the last 20 data points while the blue line is fit to the last 40 data points. ............ 96

Figure 3.4 Kar method plot to determine COX for HfO2-InAs MOS capacitor wafer 7a. The measured data is from a QS C-V characteristic. The red line is fit to the last 20 data points while and the blue line is fit to the last 40 data points. ................. 97

Figure 3.5 Capacitance-voltage characteristics of HfO 2-InAs wafer 3n, grown at 300 °C for 75 cycles, measured at 10 kHz (a), 100 kHz (b), and 1 MHz (c) at temperatures ranging from 223 to 373 K. ............................................................. 99

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Figure 3.6 Minimum capacitance (red, left axis) and hysteresis voltage shift (blue, right axis) plotted vs. measurement temperature for HfO 2-InAs MOS capacitor wafer 3n measured at 10 kHz, 100 kHz, and 1 MHz. ................................................... 100

Figure 3.7 Theoretical and measured minimum capacitance vs. temperature. Theoretical values are calculated from (3.4) for doping densities ranging from 2 × 1016 to 2 × 1019 cm-3 using a COX of 3.1 µF/cm2, calculated from the Kar method applied to the 10 kHz, 373 K data of HfO 2-InAs MOS capacitor wafer 3n. Measured values are the minimum capacitances of wafer 3n at 1 MHz. ........................................ 102

Figure 3.8 Interface trap density, DIT, vs. position in bandgap, EC – ET, for HfO2-InAs MOS capacitor wafer 3n calculated using (3.5) – (3.9) and the 1 MHz minimum capacitance measured using temperatures ranging from 223 to 373 K. ............. 105

Figure 3.9 Room (red) and liquid nitrogen (blue) temperature C-V curves of annealed Au-Ti-HfO2-InAs MOS capacitor from wafer 2a, grown at 200 °C for 75 cycles, measured at 10 kHz............................................................................................. 106

Figure 3.10 Surface potential vs. gate voltage calculated for HfO 2-InAs MOS capacitor wafer 2a from (3.11) using the 10 kHz, room temperature C-V measurement... 108

Figure 3.11 Interface trap density vs. position in bandgap for wafer 2a, calculated using the HF-LF method............................................................................................... 108

Figure 3.12 Theoretical THF capacitance vs. surface potential for a metal-oxide-InAs MOS capacitor at 77 K using different models for depletion capacitance. ........ 110

Figure 3.13 Theoretical capacitance-surface-potential (a) and measured capacitance-gate-bias (b) plots for wafer 2a showing determination of the flatband voltage [VFB = VG(VS = 0)]. ......................................................................................................... 111

Figure 3.14 Surface potential vs. gate bias. The interface trap density as well as the flatband voltage may be obtained from this plot. ............................................... 111

Figure 3.15 Interface trap density vs. position in bandgap for HfO 2-InAs MOS capacitor wafer 2a calculated using the Terman method.................................................... 112

Figure 3.16 Capacitance-voltage curves with and without illumination for HfO 2-InAs MOS capacitor wafer 2a and a HfO 2-a-Si-GaAs MOS capacitor from [95]. ..... 114

Figure 3.17 TEM micrographs of unannealed HfO 2-InAs MOS capacitor wafer 6n. The substrate is pretreated with HCl (37%). The HfO 2 is grown using 50 ALD cycles and a temperature of 200 °C. Images taken by Tom Kosel. ............................... 115

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Figure 3.18 Indium 3d XPS spectra of HfO 2-InAs heterostructures grown using 25 (red) and 50 (blue) ALD cycles at a temperature of 250 °C (wafers X2 and X8). The samples are pretreated with HF. The table inset contains the HfO 2 film thickness estimates calculated from the XPS signals based on signal normalization by the background signal and the photon flux. .............................................................. 117

Figure 3.19 Hafnium dioxide film thickness on InAs versus number of ALD growth cycles, wafers E1, E2, E3, X2, X8, and 6n. Film thicknesses are measured with XPS, ellipsometry, and TEM. The table inset contains the thicknesses calculated from the linear fit of the data. ............................................................................. 118

Figure 3.20 Capacitance-voltage characteristics of unannealed Au-Ti-HfO2-InAs MOS capacitors grown at 200 (a) and 300 (b) °C with ALD cycles ranging from 30 to 125 measured at 1 MHz. ..................................................................................... 119

Figure 3.21 Capacitance-voltage characteristics of unannealed Au-Ti-HfO2-InAs MOS capacitors grown at 200 °C with 50, 75, and 125 ALD cycles measured at 10 kHz.............................................................................................................................. 121

Figure 3.22 Capacitance equivalent thickness versus physical thickness of unannealed Au-Ti-HfO2-InAs MOS capacitors grown at 200 °C with 50, 75, and 125 ALD cycles measured at 10 kHz and +1.9 VDC. ........................................................ 121

Figure 3.23 Relative dielectric constant of HfO2 calculated using CET measurements taken at 10 kHz and different gate biases on Au-Ti-HfO2-InAs MOS capacitors grown at 200 °C using 50, 75, and 125 ALD cycles........................................... 122

Figure 3.24 Current-density-voltage characteristics of unannealed Au-Ti-HfO2-InAs MOS capacitors grown at 200 (a) and 300 (b) °C with ALD cycles ranging from 30 to 125.............................................................................................................. 124

Figure 3.25 Direct tunneling model plots for unannealed Au-Ti-HfO2-InAs MOS capacitors grown at 200 (a) and 300 (b) °C with ALD cycles ranging from 30 to 125....................................................................................................................... 126

Figure 3.26 Breakdown voltage (measured at room temperature and 100 °C) vs. film thickness for Au-Ti-HfO2-InAs MOS capacitors grown at 300 °C using 30, 40, and 50 ALD cycles. The breakdown field is calculated at each measurement temperature from the slope of the linear fit to the data. ...................................... 128

Figure 3.27 Equivalent breakdown field vs. film growth temperature for unannealed Au-Ti-HfO2-InAs wafers 8tn, 9tn, 10tn, and 13tn, grown using 50 ALD cycles. .... 129

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Figure 3.28 Capacitance-voltage characteristics of unannealed Au-Ti-HfO2-InAs MOS capacitors grown using 75 (a) and 50 (b) ALD cycles and growth temperatures ranging from 100 to 350 °C measured at 1 MHz. ............................................... 130

Figure 3.29 Current-density-voltage characteristics of unannealed Au-Ti-HfO2-InAs MOS capacitors grown using 75 (a) and 50 (b) ALD cycles and growth temperatures ranging from 100 to 350 °C........................................................... 132

Figure 3.30 Arsenic (a) and indium (b) 3d XPS spectra for unannealed HfO 2-InAs wafers X2, X5, and X6, pretreated with HF and grown using 25 ALD cycles. ............. 133

Figure 3.31 Capacitance-voltage characteristics of Au-Ti-HfO2-InAs MOS capacitors grown using 75 (a) and 50 (b) ALD cycles and growth temperatures ranging from 100 to 350 °C measured at 1 MHz before (solid lines) and after (dashed lines) PMA. The annealed, 75-cycle wafers in (a) receive a 400 °C, 2 minute, N2 PMA. The 50-cycle wafers in (b) receive a 200 °C, 1 hour, N2 PMA. ......................... 135

Figure 3.32 Bidirectional capacitance-voltage characteristics of Au-Ti-HfO2-InAs MOS capacitors grown at 300 °C using 75 (a) and 50 (b) ALD cycles measured at 1 MHz before (solid lines) and after (dashed lines) PMA. The 75-cycle, annealed wafer in (a) receives a 400 °C, 2 minute, N2 PMA. The 50-cycle wafer in (b) receives a 200 °C, 1 hour, N2 PMA. ................................................................... 136

Figure 3.33 Capacitance equivalent thickness versus physical thickness of Au-Ti-HfO2-InAs MOS capacitors grown at 200 °C with 50, 75, and 125 ALD cycles measured at 10 kHz and +1.9 VDC with (red) and without (blue) a 400 °C, 2 minute, N2 PMA.................................................................................................. 137

Figure 3.34 Current-voltage characteristics of HfO 2-InAs wafer 8p, grown at 80 °C using 50 cycles, before and after PMA at 200 °C for 1 hour. The current is reduced an order of magnitude without a significant increase in the CET. .......................... 138

Figure 3.35 Current-voltage characteristics of HfO 2-InAs MOS capacitor wafers 11t, 12t, and 13t, grown at 300 °C using 30, 40, and 50 cycles, respectively, before and after PMA at 200 °C for 1 hour in N2. ................................................................ 139

Figure 3.36 Direct tunneling model plot for annealed Au-Ti-HfO2-InAs wafers 11ta, 12ta, and 13ta, grown using 300 °C and 30, 40, and 50 cycles, respectively, and annealed at 200 °C for 1 hour in N2.................................................................... 140

Figure 3.37 Current-voltage measurements of HfO 2-InAs MOS capacitor wafer 8t, grown at 80 °C for 50 cycles, during PMA. The thermal and measurement history is diagramed in (a) and the J-V curves are shown in (b). ....................................... 141

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Figure 3.38 Current-voltage measurements of HfO 2-InAs MOS capacitor wafer 8t, grown at 80 °C for 50 cycles, during 1 hour, 200 °C PMA in N2. The thermal and measurement history is diagramed in (a) and the J-V curves are shown in (b). . 142

Figure 3.39 Current-voltage measurements of HfO 2-InAs MOS capacitor wafer 8t, grown at 80 °C for 50 cycles, during a momentary 200 °C thermal cycle in N2. The thermal and measurement history is diagramed in (a) and the J-V curves are shown in (b). ....................................................................................................... 143

Figure 3.40 Current-voltage measurements of HfO 2-InAs MOS capacitor wafer 13t, grown at 300 °C for 50 cycles, during a momentary 100 °C thermal cycle in N2. The thermal and measurement history is diagramed in (a) and the J-V curves are shown in (b). ....................................................................................................... 144

Figure 3.41 Capacitance-voltage at 1 MHz (a) and current-density-voltage (b) characteristics of unannealed Au-Ti-HfO2-InAs MOS wafers 2n, 4n, and 5n, grown at 200 °C using 75 cycles and HCl, (NH4)2S, and BHF pretreatments, respectively. ........................................................................................................ 146

Figure 3.42 Capacitance-voltage characteristics of unannealed Au-Ti-HfO2-InAs MOS wafers 2n, 4n, and 5n, grown at 200 °C using 75 cycles and HCl, (NH4)2S, and BHF pretreatments, respectively, measured at 10 kHz at 300 (solid lines) and 77 (dashed lines) K. ................................................................................................. 147

Figure 3.43 Interface trap density versus position in bandgap for unannealed Au-Ti-HfO2-InAs MOS wafers 2n, 4n, and 5n, grown at 200 °C using 75 cycles and HCl, (NH4)2S, and BHF pretreatments, respectively. The interface trap density is calculated by applying the Terman method to measurements taken at 10 kHz and 77 K..................................................................................................................... 148

Figure 3.44 Capacitance versus gate voltage (a) and gate voltage minus work function (b) for unannealed metal-HfO2-InAs wafers 13tn and 13pn, grown at 300 °C using 50 cycles with Au-Ti (blue) and Au-Pd (red) contacts. ........................................... 150

Figure 4.1 Capacitance-voltage characteristic of wafers 8pn and 14pn, HfO2-InAs (red) and HfO2-Al2O3-InAs (blue) MOS capacitors, measured at 1 MHz. ................. 158

Figure 4.2 Current-density-voltage characteristics of wafers 8pn and 14pn, HfO 2-InAs (red) and HfO 2-Al2O3-InAs (blue) MOS capacitors. .......................................... 159

Figure 4.3 Capacitance-voltage characteristic of wafers 8pa and 14 pa, HfO 2-InAs (red) and HfO2-Al2O3-InAs (blue) MOS capacitors, measured at 1 MHz after 200 °C, 1 hour, N2 PMA. .................................................................................................... 159

xiv

Figure 4.4 Current-density-voltage characteristics of wafers 8pa and 14 pa, HfO 2-InAs (red) and HfO 2-Al2O3-InAs (blue) MOS capacitors, measured after 200 °C, 1 hour, N2 PMA. .................................................................................................... 160

Figure 4.5 Bidirectional C-V sweeps of wafers 8p and 14p, HfO 2-InAs (red) and HfO 2-Al2O3-InAs (blue) MOS capacitors, at 1 MHz before (a) and after (b) PMA. ... 161

Figure 4.6 Capacitance-voltage curves of wafers 8pa and 14pa, HfO 2-InAs (red) and HfO2-Al2O3-InAs (blue) MOS capacitors, taken at 10 kHz at LN2 temperature.162

Figure 4.7 Interface trap density versus position in bandgap for wafers 8pa and 14pa, HfO2-InAs (red) and HfO 2-Al2O3-InAs (blue) MOS capacitors, as measured by the low temperature Terman method. ................................................................. 163

Figure 4.8 Room (a) and low (b) temperature 10 kHz C-V curves of wafers 2n and 5n, 200 °C, 50-cycle HfO 2 devices with HCl and BHF InAs pretreatments, respectively. ........................................................................................................ 165

Figure 4.9 Interface trap dens ity versus position in bandgap as measured by the low-temperature Terman method for wafers 2n and 5n, 200 °C, 50-cycle HfO2 devices with HCl and BHF InAs pretreatments, respectively. ........................................ 166

Figure 4.10 Interface trap density versus position in bandgap as measured by the low-temperature Terman method for wafers 8pa and 9pa, 50-cycle HfO 2-InAs capacitors grown at 80 and 250 °C, respectively. ............................................... 167

Figure 4.11 Capacitance-voltage curves of wafers 14p and 15p measured at 10 kHz and 1 MHz before (a) and after (b) 200 °C, 1 hour, N2 PMA. Wafer 14p was grown with 10 cycles of Al2O3 at 300 °C followed by 50 cycles of HfO 2 grown at 100 °C. Wafer 15p was grown with 10 cycles of HfO 2 at 300 °C followed by 50 cycles of HfO2 grown at 100 °C......................................................................................... 169

Figure 4.12 Arsenic (a) and indium (b) 3d XPS spectra for wafers X10, X11, and X12, as-is InAs (red), InAs with ALD-grown HfO2 (blue), and InAs with ALD-grown Al2O3 (green), respectively. ................................................................................ 171

Figure 5.1 Leakage current density measured at VG = +1 V vs. CET measured at 10 kHz and VG = +1 V for all high-k-InAs MOS capacitor heterostructures fabricated in this work (red) and ITRS targets for high-performance, bulk, metal-gate MOSFETs for years 2009 – 2016 (LG = 27 – 14 nm) (blue) from [11]. ............. 175

Figure 5.2 Leakage current density vs. CET or EOT for this work and other MOS work. Citations and structure detail are given in Table 5.1. ......................................... 177

xv

Figure 5.3 ITRS gate dielectric EOT requirement vs. physical gate length for high-performance, metal-gate bulk (red), fully-depleted silicon-on- insulator (blue), and multi-gate (green) MOSFETs from [11]. ............................................................ 179

Figure 5.4 EOT vs. physical HfO 2 thickness. EOT is calculated with (solid lines) and without (dashed lines) unintentional interlayer (IL) thickness for pre- (blue) and post- (red) PMA devices. IL thickness and dielectric constant for pre- and post-PMA devices calculated from wafers 2, 6, and 7, Au-Ti-HfO2-InAs devices grown using 200 °C and 50, 75, and 125 cycles, respectively, shown in Figure 3.33. PMA is at 400 °C for 2 min. in N2...................................................................... 180

Figure 5.5 ITRS total interface charge requirement vs. physical gate length for MOSFET gate dielectrics from [11]. All charge is assumed to be at the gate-dielectric-semiconductor interface (i.e. no bulk oxide charge). .......................................... 181

Figure 5.6 Interface trap density versus position in bandgap as measured by the low-temperature Terman method for unannealed wafer 2n, Au-Ti-HfO2-InAs grown at 200 °C with 50 cycles and HCl pretreatment. The trap density is integrated over the bandgap to calculate the total interface charge density. ................................ 182

xvi

ACKNOWLEDGEMENTS

I would like to thank Dr. Alan Seabaugh. It has been a pleasure to work under his

direction throughout my undergraduate and graduate education. It is with his

encouragement that I first began conducting scientific research, and for that, I am in his

debt. I hope that we continue to collaborate when my time here at Notre Dame is done.

I would like to thank Drs. Fay, Kosel, and Snider for serving on my defense

committee and for guidance and useful discussions throughout my graduate career. I

thank Dr. Doug Hall for serving as advisor for my master’s thesis and for the freedom he

granted me to pursue the related research.

My thanks are also owed to Pat Base, Tracy Cabello, Heidi Deethardt, Leona

Strickland, and Roberta White for administrative assistance. I also thank Keith Darr,

Mark Richmond, Mike Thomas, and Mike Young for their excellent work maintaining

the lab facilities.

I would like to thank all of my fellow graduate students and friends throughout

my time here, and particularly, Jeff Bean, Brian Dunn, Tomas Estrada, Hubert George,

Vishwanath Joshi, Robin Joyce, Yeqing Lu, Guangle Zhou, Aaron Prager, John Simon,

and Ze Zhang. A special thanks is due the members of the Seabaugh Group: Sajid

Kabeer, Surajit Sutar, Tim Vasen, Wu Bin, and Qin Zhang; I have enjoyed working and

developing friendships with them all.

xvii

I would like to thank all the members of my family for support throughout the

years. It has been one of the great joys in my life to watch my younger siblings, Angie

and Matt, grow into intelligent and thoughtful human beings; I hope that I had something

to do with that. I thank my father, Glen Wheeler, for the long drives to hockey practice

every week, during which I provided an endless barrage of questions about all manner of

topics; I am certain that his answers made me who I am today. Lastly, I thank my mother,

Fanny Wheeler. It is because of her twenty-five years of service to the Electrical

Engineering Department that I was able to attend this university; it is a gift that will stay

with me for the rest of my life and that I can only hope to repay by sharing this

accomplishment with her.

1

CHAPTER 1:

INTRODUCTION

Over the last fifty years the number of components on an integrated circuit (IC)

has exponentially increased, resulting in new generations of digital processors that

perform more operations per second than their predecessors. To continue to abide by

Moore’s Law, which describes this trend, the transistor constituents of ICs are made

smaller and faster. The incremental improvements in transistor performance are the result

of years of effort from thousands of researchers the world over, with each breakthrough

adding more life to the Si-based IC, the workhorse of the digital IC industry.

While the end of Si scaling has been predicted before, limitations based on

fundamental physics seem to pose insurmountable barriers [1]. These barriers and recent

changes in transistor design and fabrication provide opportunities for new materials to

replace or augment silicon technology.

1.1 Historical background

Well before the invention of the point-contact transistor by John Bardeen and

Walter Brattain in 1947 [2], a transistor based on the field-effect was proposed [3].

However, this proposal went largely unnoticed until attorneys at Bell Laboratories

discovered it while preparing to file a patent on behalf of William Shockley, who also

sought to make a field-effect transistor (FET) [4]. And while the field-effect had been

2

known and studied for some time, the early attempts of Shockley and others at Bell Labs

to demonstrate the effect experimentally were unsuccessful in that the effect was far

weaker than predicted by the prevailing theory. In response to these failures, Bardeen

developed a theoretical model based on surface states that explained why the observed

field effect was weaker than expected [5].

Bardeen realized that charges present on the surface of a semiconductor cancel the

effect of charges placed on the metal electrode situated above the semiconductor surface.

With a clean or “free” semiconductor surface, the electrode charges all contribute to the

modulation of the bulk semiconductor carrier density. However, with a contaminated

surface, in order to maintain charge neutrality, some of the electrode charge must be used

to balance surface charges. It was surface states that limited the observed

transconductance in field effect experiments.

Armed with cleaner surfaces and Bardeen’s theory, Shockley and Pearson

demonstrated an appreciable field effect in copper oxide, silicon, and germanium thin

films that were separated from a metal electrode by fused quartz and estimated the

density of surface states based on the results [6]. By including a thin dielectric insulator

between the electrode and semiconductor, Shockley and Pearson were able to

reproducibly apply the high electric fields necessary to see the field effect. It became

clear that a practical transistor based on this effect would also require a small separation

between the electrode or “gate” and the semiconductor or “channel.”

It was also realized that in addition to small gate-channel separation, an insulated-

gate FET (IGFET) would require a gate insulator that could withstand high fields without

being physically damaged. The insulators also needed to exhibit low loss (low leakage

3

current) and form an interface with the semiconductor channel that was low in surface

states. These challenges proved to be so great that it wasn’t until 1959, when Atalla

proposed thermally-grown SiO 2 on Si, that a suitable insulator-semiconductor

combination was suggested [7].

At the 1960 Device Research Conference, Kahng and Atalla reported the first

metal-oxide-semiconductor FET (MOSFET) [8]. The SiO2-Si system was so successful

that SiO2-Si MOSFETs soon became the dominate device in the semiconductor industry.

Sixteen years after their introduction, SiO 2-Si MOSFETs surpassed one billion dollars in

annual sales in the US alone [9]. Over the next four and a half decades, SiO 2-Si MOSFET

technology was continuously improved, and in the domain of digital logic integrated

circuits (ICs), was never seriously challenged by any other material system. In 2007, Intel

[10] announced HfO 2 had replaced SiO 2 in its digital IC technology, marking perhaps the

biggest change to the commercial MOSFET in the history of the industry.

1.2 Motivation

The International Technology Roadmap for Semiconductors (ITRS) sets the

performance targets for complementary MOS (CMOS) technology. In the current

projection, high-performance, metal-gate, bulk MOSFETs will require gate insulators

with an equivalent oxide thickness (EOT) of 0.5 nm that exhibit less than 1.4 kA/cm2 in

leakage current density by the year 2016 (which corresponds to a 14 nm physical gate

length) [11]. At this thickness, direct tunneling plays a significant role in leakage current.

Brar et al. [12] measured the oxide thickness dependence of the current-voltage (I-V)

characteristics of the Al-SiO2-n-Si heterostructure for SiO 2 thicknesses from 1.65 nm to

4

3.51 nm and showed these characteristics fit well to a simple direct tunneling model. The

1.65-nm-thick oxide structure yielded a tunneling current density of 4 A/cm2 at a bias of

0.5 V, which would meet the 1.4 kA/cm2 specification, however, extrapolation of Brar’s

result to a 0.5 nm oxide thickness would result in a tunneling current density of almost

200 kA/cm2, far above the 1.4 kA/cm2 requirement.

While the leakage current requirement sets a limit on the minimum SiO2 barrier

thickness, the increasing static power dissipation due to leakage current is motivating

research into new dielectrics and alternative MOSFET channels. To increase the oxide

thickness without degrading capacitance, a gate dielectric material with a higher

permittivity than SiO 2 can be utilized. So-called high-k (high dielectric constant)

materials, like HfO 2, allow the physical oxide thickness to increase by up to 6.4×, based

on the fact that the relative dielectric constant of HfO 2 is around 25, 6.4× higher than

SiO2 (3.9), while still maintaining the same capacitance as an SiO 2 dielectric which is

6.4× thinner [13].

With the introduction of the 45 nm technology node, HfO 2 has been added to the

gate stack. With the maturation of atomic layer deposition (ALD) techniques and new

gate dielectrics, it is timely to explore these dielectrics on III-V channel materials. III-V

materials are of interest because they feature electron mobilities much higher than Si, as

shown in Table 1.1 and offer the possibility for higher electron velocities and higher

speed.

5

TABLE 1.1

SEMICONDUCTORS FOR ALTERNATIVE-CHANNEL MOSFETS

µn (cm2/Vs)

µp (cm2/Vs)

Si 1350 480

Ge 3900 1900

InGaAs 12,600 400 InAs 40,000 500

InSb 80,000 850

GaSb 3000 1000

All values from Brennan and Brown [14] except those for InSb from Sze [15].

The work described in this thesis involved a collaboration between the University

of Notre Dame and Lund University, Sweden. The collaboration was motivated by

investigations of low-subthreshold swing tunnel transistors (TFETs) [16, 17] and InAs-

on-SOI (silicon-on- insulator) MOSFETs [18, 19] at Notre Dame and InAs vertical

nanowire FETs [20, 21] at Lund, both of which stand to benefit from the development of

a low-leakage, high-k, low-interface-state-density gate dielectric on InAs. In this work,

gate dielectrics on InAs are evaluated through the characterization of InAs-based MOS

capacitors.

The MOS capacitor is an indispensable tool in the evaluation of gate oxides and

their interfaces with semiconductors. The usefulness of the MOS capacitor comes from

its simple structure and fabrication procedure. The analysis of MOS capacitors is also

6

simplified relative to its MOSFET counterparts as the result of its one-dimensional

nature. From the electrical characterization of MOS capacitors, MOS system properties

relevant to FET device performance, such as gate dielectric leakage current density,

capacitance, and interface state density, are determined.

1.3 Prior art

Soon after the introduction of the SiO 2-Si MOSFET, researchers from the Radio

Corporation of America (RCA) published the first report of a SiO2-GaAs MOSFET in

1965 [22]. The effective channel mobility of these early GaAs MOSFETs exceeded what

was then obtained in Si MOSFETs with the same geometry by over 3×: 640 cm2 /Vs for

the GaAs MOSFET vs. 200 cm2 /Vs for the Si MOSFET [22]. Unlike the Si MOSFETs,

these GaAs MOSFETs had deposited rather than native SiO 2. It was soon realized that

the high density of interface traps at the SiO 2-GaAs interface limited the

transconductance of the device.

Two years later RCA reported a Si3N4-GaAs MOSFET that represented a marked

improvement over its SiO2-based predecessor, featuring effective channel mobilities as

high as 3000 cm2/Vs. At the time, it seemed GaAs was on its way to replacing Si in the

commercial IC market. Researchers at RCA optimistically stated, “The time, talent, and

money lavished on gallium arsenide for more than a decade is about to pay off in a field

effect transistor that is far superior to its counterparts made of silicon.” [23]

Of course, this anticipated revolution in microelectronics never happened. The

invention of the high-electron-mobility transistor (HEMT) in 1980 [24] did provide a

commercial application for GaAs transistors, leading to use in cell phones, high-speed

7

communications, and radar, among other things, that now comprise 2% of the

semiconductor market [25]. However, over the last four decades, interest in III-V

MOSFETs waxed and waned. Many materials and deposition techniques were studied

including pyrolytically-deposited SiON [26] and Al2O3 [27] as well as highly-resistive

AlGaAs [28] and GaAs [29] deposited by molecular-beam-epitaxy (MBE). Inspired by

the success of Si and its native oxide, a number of groups investigated the native oxides

of the III-Vs, using thermal oxidation [30], wet-chemical anodization [31, 32], and

plasma- [33] and laser- [34] assisted oxidation. In parallel to the work on GaAs were the

investigations of insulators on other III-V materials including InAs [35-39], InP [40-43],

and InSb [44]. By the mid-1980s, most III-V transistor research focused on HEMT

devices and interest in III-V MOS faded.

1.4 State of the art

New gate insulator deposition techniques that came about in the mid-1990s to

early-2000s coupled with the desire for higher velocity channels has renewed interest in

III-V MOSFET research. Passlack et al. use in situ electron-beam evaporated

Ga2O3(Gd2O3) on MBE-deposited GaAs films to yield MOS gate stacks with low

interface trap density. The films are created in a multi-chamber MBE system that allows

samples to be transferred from channel-growth to insulator-growth chambers without

breaking vacuum. The technique produces both GaAs [45] and InGaAs [46]

enhancement-mode MOSFETs, among other devices.

At Notre Dame, Zhang [47] and Cao [48] fabricated depletion-mode GaAs

MOSFETs with record cutoff frequencies using a wet-thermally-oxidized, MBE-

8

deposited InAlP layer on GaAs to create the gate stack. The large bandgap of oxidized

InAlP provides a low leakage gate insulator, while the use of wet-thermal oxidation

enables a flexible, low-cost fabrication procedure [49, 50].

While in-situ-deposited and wet-thermally-oxidized gate insulators yield

promising devices results, both techniques lack the self- limiting oxide growth offered by

the ALD technique. ALD is used by Intel for high-k gate dielectric deposition in its 45

nm technology [10] and is presently the most heavily- investigated III-V gate insulator

deposition technique. Atomic-layer deposition has been in use since the 1980s [51], but

only since 2001, beginning with the work of Ye and Wilk, has ALD been used for III-V

MOS gate stacks [52]. Sparked by the initial device results of Ye et al. [53, 54], ALD-

gate-insulator-III-V MOS stacks remain an active area of research. Atomic- layer

deposition is used for the study of high-k films on GaAs [55], InGaAs [56], InAs [57],

and GaN [58]. Kim et al. have published a brief report on ALD-high-k films on n- and p-

type GaAs, InGaAs, InAs, and InSb [59]. In this work, the ALD technique is used to

deposit HfO2 and Al2O3 films on InAs.1

1.5 Organization

In this thesis, metal-high-k-InAs MOS capacitors, with high-k films deposited by

ALD are evaluated for their potential as gate insulators in InAs-based MOSFETs.

Chapter 2 discusses the basic structure and physics of MOS capacitors as well as the

measurement equipment and procedures used for characterization. Chapter 3 presents the

1 See Appendix A for conference abstracts.

9

results of metal-HfO2-InAs MOS capacitors, examining the bias, frequency, and

temperature dependence of the devices and determining device properties such as leakage

current, physical and electrical equivalent thickness, and interface trap density, among

others. Chapter 4 presents the results of metal-HfO2-Al2O3-InAs nanolaminate MOS

structures. In Chapter 5, the experimental results of Chapters 3 and 4 are used to assess

metal-high-k-InAs MOS gate stacks through comparison to ITRS performance targets.

Chapter 6 summarizes the work and suggests directions for future research.

10

CHAPTER 2:

MODELING AND MEASUREMENT OF MOS CAPACITORS

In this chapter, the electrical behavior of MOS capacitors is explored using

analytic models to calculate capacitance-voltage (C-V) and current-density-voltage (J-V)

characteristics. The resulting features of the characteristics are described and model

parameters are adjusted to show how these features relate to physical device properties. A

description of the measurement of device C-V and J-V characteristics is given, detailing

equipment setup, calibration, and use. Measurement parameters are described and varied

to show how they influence measured characteristics.

2.1 Basic MOS capacitor structure and operation

An MOS capacitor consists of a stack of metal, oxide, and semiconductor layers.

Often in practice, MOS stacks are formed vertically on semiconductor substrates by

blanket depositing (or thermally growing) an oxide layer and placing metal contacts on

top of the oxide. The metal contact serves as one electrode while the backside of the

substrate serves as the other and may be covered with metal (a backside contact) to form

an ohmic contact and reduce series resistance.

Depending on the bias applied across the electrodes, the capacitor can be in one of

four operating regimes. Figure 2.1 shows the energy band diagrams for each of these

regimes for an n-type semiconductor. For an n-type device, if the gate voltage (the

voltage applied to the metal contact), VG, is greater than the flatband voltage, VFB, then

11

the device is in accumulation, which corresponds to the accumulation of majority carriers

at the oxide-semiconductor interface. When VG is lowered to equal VFB, then the device is

in flatband, which corresponds to no net charge in the semiconductor. As the gate bias is

lowered below the flatband voltage, the device goes into depletion/weak inversion, where

majority carriers are pushed away from the oxide-semiconductor interface, forming a

depletion layer that continues to grow until the gate voltage reaches the threshold voltage,

VT. At VT and below, a sheet of minority carriers, called an inversion layer, at the oxide-

semiconductor interface prevents the depletion layer from expanding further.

M O S

Ene

rgy

EF

accumulation(V

G > V

FB)

Position

EC

EV

EF

qVG

M O S

Ene

rgy

Position

EF

flatband(V

G = V

FB)

EC

EV

EF

qVFB

~~ΦM ~~ Χ

S

vacuumlevel

Ene

rgy

EF

Position

depletion(V

G < V

FB)

EC

EV

EF

EF

inversion(V

G < V

T)

EC

EV

EF

Ene

rgy

Position

qVS

EiqV

BqVT

Figure 2.1 Energy band diagrams for MOS capacitor (n-type semiconductor) in accumulation, flatband, depletion, and inversion regimes.

12

The flatband voltage is defined as the gate voltage at which the energy bands in

the semiconductor are flat and in an ideal structure (i.e. no oxide or interface charges) is

given by

FCSMFB EE?FqV +−−= , (2.1)

where q is the electron charge 1, FM is the metal workfunction, ? s is the semiconductor

electron affinity, EC is the semiconductor conduction band energy, and EF is the Fermi

level. The threshold voltage is defined as the gate voltage at which the semiconductor

enters strong inversion, which is usually defined as when the semiconductor surface

potential, VS, reaches a magnitude twice that of the semiconductor bulk potential, VB. For

an n-type device, the threshold voltage and bulk potential are given by [60]

OXSBDBFBT CVqNVVV /)4(2 2/1ε−+= and (2.2)

)/ln()/( iDBB nNqTkV −= , (2.3)

where ND is the n-type semiconductor doping density, eS is the semiconductor dielectric

constant, COX is the capacitance (per unit area) of the oxide, kB is Boltzmann’s constant, T

is the absolute device temperature, and ni is the semiconductor intrinsic carrier

concentration.

2.2 MOS capacitance-voltage modeling

The low-frequency capacitance of an MOS capacitor can be modeled with a

simple circuit consisting of two capacitors connected in series. One capacitor, COX,

1 In this thesis, q represents the magnitude of the electron charge (i.e. q is a positive number, 1.602 × 10-19 C).

13

represents the capacitance (per unit area) of the oxide and is equal to eOX/tOX, where eOX is

the dielectric constant of the oxide and tOX is the thickness of the oxide. The second

capacitor, CS, represents the capacitance of the semiconductor and is dependent on bias.

For an ideal device (i.e. no oxide or interface charges and no series resistance), the

measured capacitance per unit area, CM, is

111

−

+=

SOXM CC

C . (2.4)

The semiconductor capacitance (per unit area) is given by the derivative of the

surface charge density in the semiconductor, QS, with respect to the semiconductor

surface potential, VS. The surface charge density is related to the surface potential by the

Poisson equation. Combining this relation with the Fermi-Dirac distribution of carriers in

the semiconductor yields2

×= )/(2 DBSS qLTkQ ε

[ ] [ ] 2/100 1//exp()/(1/)/exp( −+−+−− TkqVTkVnpTkqVTkqV BSBSnnBSBS

(2.5)

for an n-type semiconductor, where LD is the Debye length, and pn0 and nn0 are the

equilibrium hole and electron concentrations in the semiconductor bulk, respectively.

Equation (2.5) is plotted for Si in Figure 2.2.

2 See [61] for full derivation.

14

10-12

10-8

10-4

100

104

108

-3 -2 -1 0 1 2 3

Sur

face

Cha

rge

Den

sity

(C

/cm

2 )

Surface Potential (V)

N = -6.8 × 1016 cm-3

1.0 × 1010 (ni )

+6.8 × 1016T = 300 KSi:

εS = 11.7

Figure 2.2 Absolute value of the surface charge density at 300 K vs. semiconductor surface potential for Si doped 6.8 × 1016 cm-3 : n-type (red), p-type (green), and intrinsic (blue).

The accumulation, flatband, depletion, and inversion regimes can be understood

from Figure 2.2. Using the n-type case (red) as an example, the device is in accumulation

at +2V. As the surface potential is decreased, the accumulation charge (comprised of

majority, n-type carriers) drops exponentially until flatband is reached at 0 V. As the

surface potential becomes negative, majority electrons are repelled, leaving a depletion

layer comprised of ionized impurities. As the sur face potential is further decreased, this

depletion layer continues to expand until the inversion threshold is reached at

approximately -1 V. Thermally generated minority holes now dominate the surface

charge and increase exponentially with surface potential. The dependence of charge on

surface potential is reversed for a p-type semiconductor.

The capacitance per unit area in the semiconductor is found using

S

SS dV

dQC = . (2.6)

15

It is then important to relate the applied gate bias to the semiconductor surface potential.

This is achieved with the relation

FBSOXG VVVV ++= , (2.7)

where VOX is the voltage drop across the oxide and is given by

OX

SOX C

QV = . (2.8)

With these definitions, the equilibrium (low-frequency) C-V curve may now be plotted

parametrically using surface potential as the variable. Figure 2.3 is this C-V plot and what

can be expected as a function of measurement condition at low-frequency (LF), high-

frequency (HF), or, as will be discussed, in deep depletion (DD). Here, the curves are for

an ideal (no interface charges and VFB = 0) metal-HfO2-n-type-Si MOS capacitor.

0

0.05

0.1

0.15

0.2

0.25

-4 -2 0 2 4

Cap

acita

nce

(µF/

cm2)

Gate Voltage (V)

COX

HfO2-n-Si

T = 300 Kε

S = 11.7

ni = 1.0 × 1010 cm-3

ND = 6.8 × 1016 cm-3

εOX

= 25

tOX

= 100 nm

low frequency(LF)

high frequency(HF)

deep depletion(DD)

Figure 2.3 Modeled LF (red), HF (green), and DD (blue) C-V curves for an example metal-HfO2-n-Si MOS capacitor.

Which of the modeled C-V characteristics in Figure 2.3 is observed is dependent

upon the measurement parameters. Capacitance-voltage curves are typically measured by

16

slowly ramping the applied direct current (DC) bias across a device while also applying a

small alternating current (AC) signal and measuring the differential capacitance. This

differential capacitance is then plotted versus the applied DC bias to obtain a C-V

characteristic. Depending on the speed of the DC bias ramp and the frequency of the AC

signal, different C-V profiles can be obtained.

The variations in the different types of C-V curves all occur in the inversion

regime, where minority carriers are responsible for the semiconductor capacitance. If the

DC ramp rate and AC signal frequency are low enough to allow minority carriers in the

device to remain in equilibrium, the LF curve is observed. If the AC signal frequency is

increased to the point where minority carrier generation lags behind the signal, then they

are not able to contribute to the differential capacitance and the semiconductor

capacitance is due only to the depletion layer. And while the minority carriers are not in

equilibrium with the AC signal, they are in equilibrium with the DC signal and fix the

depletion layer width at the onset of strong inversion, causing the overall measured

capacitance to saturate, and give rise to the HF curve. If the DC ramp rate is also

increased, and the minority carriers are not allowed to reach equilibrium with the DC

bias, then they are unable to fix the depletion layer width. The depletion layer continues

to expand, reducing the measured capacitance and resulting in the DD curve.

The HF and DD curves can be approximated by setting the semiconductor

capacitance equal to the depletion layer capacitance in the depletion regime,

wC S

Sε

= , (2.9)

where w is the depletion layer width and is given by

[ ] 2/1)/(2 DSS qNVw ε= . (2.10)

17

To approximate the HF curve, the depletion layer width is fixed when the surface

potential equals twice the bulk potential. For the DD curve, w is allowed to increase as

the device goes into inversion.

Equipped with a model for C-V characteristics, the model parameters may be

varied to see how the physical properties of MOS devices influence the measured curves.

Figure 2.4 is a plot of LF, HF, and DD C-V curves for a p-type MOS capacitor. Since

only the sign of the doping concentration was changed from the device modeled in Figure

2.3, the resulting curves are a mirror image of the n-type device. However, as will be seen

later, differences in conduction and valence band densities of states can influence this

symmetry and are not accounted for in this simple model.

0

0.05

0.1

0.15

0.2

0.25

-4 -2 0 2 4

Cap

acita

nce

(µF/

cm2)

Gate Voltage (V)

COX

HfO2-n-Si

T = 300 Kε

S = 11.7

ni = 1.0 × 1010 cm-3

NA = 6.8 × 1016 cm-3

εOX

= 25

tOX

= 100 nm

LF

HF

DD

Figure 2.4 Modeled LF (red), HF (green), and DD (blue) C-V curves for an example metal-HfO2-p-Si MOS capacitor.

Figure 2.5 shows how the semiconductor doping concentration influences the LF

C-V curve. Increasing the doping serves to stretch-out the curve and increase the

minimum capacitance. These effects can be understood in terms of the depletion layer

18

width, given by (2.10). As ND is increased, the rate of change of w with respect to VS

decreases. Since depletion capacitance is (inversely) proportional to depletion width, the

overall measured capacitance rate of change with respect to VS is also reduced. The

minimum capacitance is set by the maximum depletion width (which is reached at VS =

2VB). Since maximum depletion width is inversely proportional to doping concentration

and minimum capacitance is inversely proportional to maximum depletion width, the

minimum capacitance is directly proportional to doping concentration.

0

0.05

0.1

0.15

0.2

0.25

-4 -2 0 2 4 6

Cap

acita

nce

(µF/

cm2)

Gate Voltage (V)

COX

HfO2-n-Si

T = 300 Kε

S = 11.7

ni = 1.0 × 1010 cm-3

εOX

= 25

tOX

= 100 nm

low frequency

ND = 6.8 × 1015 cm-3

6.8 × 1016

6.8 × 1017

Figure 2.5 Modeled LF C-V curves for an example metal-HfO2-n-Si MOS capacitor with semiconductor doping concentrations of 6.8 × 1015 (red), × 1016 (green), and × 1017 (blue) cm-3.

Figure 2.6 models the LF and HF curves for an example metal-HfO2-n-Si device

at 77 (liquid nitrogen temperature), 300 (room temperature), and 373 (100 °C) Kelvin. In

this model, temperature changes are represented by a change in the intrinsic carrier

concentration as well as the temperature parameter. As seen in the Figure 2.6 table inset,

intrinsic carrier concentration increases with increased temperature. Increased intrinsic

carrier concentration has a similar effect to increased doping concentration in that it

19

stretches the C-V curve. From (2.5) it can be seen that the rate of change of charge in the

semiconductor is reduced with respect to surface potential when the temperature is

increased, which also gives rise to a stretch-out effect. It should be noted that minority

carrier generation times also increase with temperature so the measurement frequency at

which devices transition from low- to high-frequency behavior changes with temperature.

This model assumes low- and high-frequency conditions are met when calculating each

curve. However, in practice, these conditions will be temperature-dependent and at a

fixed measurement frequency, the inversion-regime capacitance will exhibit temperature-

dependence.

0

0.05

0.1

0.15

0.2

0.25

-4 -2 0 2 4

Cap

acita

nce

(µF

/cm

2 )

Gate Voltage (V)

COX

HfO2-n-Si

εS = 11.7

εOX

= 25

tOX

= 100 nm

373 K300 K77 K

HF

LF

1.0E+10

300 K

1.2E+121.6E-20ni (cm-3)

373 K77 KSi

1.0E+10

300 K

1.2E+121.6E-20ni (cm-3)

373 K77 KSi

Figure 2.6 Modeled LF and HF C-V curves for an example metal-HfO2-n-Si MOS capacitor at 77 (blue), 300 (green), and 373 (red) K.

Figure 2.7 contains LF curves for varied oxide thicknesses (a) and dielectric

constants (b). From the two plots, it can be seen that lowering the oxide thickness has the

same effect as increasing the oxide dielectric constant. This is because the oxide is

represented only by its capacitance, COX, and is equal to eOX/tOX. This equivalence is used

to define a parameter which can also be used to represent the oxide layer, the equivalent

20

oxide thickness (EOT). An oxide layer’s EOT is defined as the silicon dioxide layer

thickness that would achieve the same capacitance as the high-k dielectric,

OX

SiOOXt

εε

2EOT = , (2.11)

where2SiOε is the dielectric constant of silicon dioxide (3.9e0).

0

0.2

0.4

0.6

0.8

1

-4 -2 0 2 4

Cap

acita

nce

(µF/

cm2 )

Gate Voltage (V)

tOX

= 25 nm

HF

LF

50 nm

100 nm

HfO2-n-Si

T = 300 Kε

S = 11.7

ni = 1.0 × 1010 cm-3

ND = 6.8 × 1016 cm-3

εOX

= 25

(a)

0

0.2

0.4

0.6

0.8

1

-4 -2 0 2 4

Cap

acita

nce

(µF/

cm2 )

Gate Voltage (V)

εOX

= 100

HF

LF

50

25

HfO2-n-Si

T = 300 Kε

S = 11.7

ni = 1.0 × 1010 cm-3

ND = 6.8 × 1016 cm-3

tOX

= 100 nm

(b)

Figure 2.7 Modeled LF and HF C-V curves for an example metal-HfO2-n-Si MOS capacitor with EOTs of 3.9 (red), 7.8 (blue), and 15.6 (green) nm. Capacitor EOTs are modeled by varying oxide thickness (a) and dielectric constant (b).

21

In all of the C-V curves shown thus far the flatband voltage has been set to zero,

meaning that the metal and semiconductor Fermi levels line up such that no band bending

occurs in the semiconductor at zero bias. In practice, this is rarely the case. From (2.7)

and Figure 2.8 the effect of a non-zero flatband voltage can be seen. The introduction of a

flatband voltage shifts the entire C-V curve towards increased negative voltage for

negative VFB and towards increased positive voltage for positive VFB for both n- and p-

type devices.

0

0.05

0.1

0.15

0.2

0.25

-6 -4 -2 0 2 4 6

Cap

acita

nce

(µF

/cm

2 )

Gate Voltage (V)

COX

HfO2-n-Si

T = 300 Kε

S = 11.7

ni = 1.0 × 1010 cm-3

εOX

= 25

tOX

= 100 nm

low frequency0 VV

FB = -1 V +1 V

Figure 2.8 Modeled LF C-V curves for an example metal-HfO2-n-Si MOS capacitor with flatband voltages of -1 (green), 0 (red), and +1 (blue) V.

Fixed charge at the oxide-semiconductor interface has a similar effect to the C-V

curve because it modifies the flatband voltage. Fixed charge is so-called because (unlike

interface trap charge) it is unable to change its charge state. A fixed charge density, Q0,

present at the oxide-semiconductor interface modifies the flatband voltage given by

OXidealFBFB C

QVV 0

, −= (2.12)

22

where VFB,ideal is the flatband voltage without oxide charge. From (2.12) it can be seen

that positive oxide charge shifts the C-V curve towards increased negative bias and

negative oxide charge shifts the curve towards increased positive bias.

Measurement history can also shift C-V characteristics; this phenomenon is

known as hysteresis. After a C-V measurement is performed, charge built up in traps can

remain until the next measurement is performed. Bidirectional C-V sweeps (in which the

DC bias is swept from one bias to another and back) are used to measure hysteresis.

Because the voltage shift, ? Vhyst, between the curves from each direction is a related to

the amount of charge built up in traps, it is used as a figure-or-merit in MOS

characterization.

Interface traps are states that exist within the semiconductor band gap and are able

to change their charge state with gate bias. When the semiconductor Fermi level energy is

brought above a trap’s energy level, the trap becomes filled. Since interface trap charge,

QIT, changes with surface potential, it contributes a capacitance, CIT, as well as modifies

the gate-bias-surface-potential relationship. Using charge balance as a starting point, this

modification may be handled quantitatively after [62]. The charge on the gate is balanced

by charge in interface traps and depletion charge in the semiconductor,

)()()( SSSITSGOX VQVQVVC −−=− , (2.13)

where QIT and QS are functions of VS. By taking the derivative of VG with respect to VS,

one may obtain

[ ] SSSSITOXOX

G dVVCVCCC

dV )()(1

++= , (2.14)

where CIT and CS are functions of VS and are given by

23

S

ITSIT dV

dQVC −=)( and (2.15)

S

SSS dV

dQVC −=)( . (2.16)

The interface trap charge per unit energy is related to the density of interface

states by

)( SITIT VqDQ = (2.17)

where DIT is the density of interface states per unit energy which is a function of surface

potential, VS. In III-V interfaces, the interface trap distribution (on a logarithmic scale) is

parabolic in energy, while Si interfaces typically have a U-shaped distribution; the

minimum density in both cases typically occurs near midgap [52]. Here, for simplicity,

the interface trap density profile is modeled as flat (unchanging with energy). While the

density of traps does not change with VS, their occupancy does, so a flat interface trap

profile contributes a constant capacitance (density) connected in parallel with the

semiconductor capacitance and is equal to qDIT. With the interface trap capacitance

known, (2.14) may be integrated to obtain the dependence of VS on VG including the

effect of interface traps.3 Figure 2.9 plots surface potential versus gate voltage for an

example MOS capacitor with no interface traps (red) and with a constant interface trap

density of 1 × 1012 cm-2eV-1 (blue).

3 The integral is taken from VS = 0 to VS with VFB as the integration constant. Interface traps will also contribute a shift to VFB, but for simplicity, the flatband voltage is fixed to zero in this model.

24

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

-6 -5 -4 -3 -2 -1 0 1

Sur

face

Pot

entia

l (V

)

Gate Voltage (V)

HfO2-n-Si

T = 300 Kε

S = 11.7

ni = 1.0 × 1010 cm-3

εOX

= 25

tOX

= 100 nm

VFB

= 0 V

DIT = 1 × 1012 cm-2eV-1

DIT = 0

Figure 2.9 Modeled surface potential vs. gate voltage relationship for an example metal-HfO2-n-Si MOS capacitor with an interface trap density of 0 (red) and 1 × 1012 (blue) cm-2eV-1.

From the figure it can be seen that interface traps stretch out the VS-VG relation,

which also stretches out the C-V curve. The presence of interface traps increases the gate

voltage needed to achieve a given surface potential because charges on the gate electrode

need to neutralize both interface charges and charges in the semiconductor. In extreme

cases, the VS-VG relation becomes so stretched-out that the surface potential does not

change at all with gate bias. This is known as “Fermi- level pinning” and is frequently

encountered in III-V-MOS devices [63]. In addition to the stretch-out, at low frequency,

interface traps contribute a capacitance. The measured LF capacitance (density) now

becomes

111

−

+

+=ITSOX

M qDCCC . (2.18)

At high frequency, minority carriers do not contribute to the capacitance, however,

interface traps can respond to frequencies up to 100 MHz in Si [62], and therefore, do

25

contribute and the measured HF capacitance is also given by (2.18), but as already

discussed, in the inversion regime, CS is the depletion capacitance. The LF and HF curves

of an example MOS capacitor with and without interface traps are shown in Figure 2.10.

0

0.05

0.1

0.15

0.2

0.25

-6 -4 -2 0 2 4

Cap

acita

nce

(µF/

cm2)

Gate Voltage (V)

COX

HfO2-n-Si

T = 300 Kε

S = 11.7

ni = 1.0 × 1010 cm-3

ND = 6.8 × 1016 cm-3

εOX

= 25

tOX

= 100 nm

HF

LF

LF

HF

DIT

= 1 × 1012

DIT

= 0 cm-2eV-1

Figure 2.10 Modeled LF and HF C-V curves for an example metal-HfO2-n-Si MOS capacitor with an interface trap density of 0 (red) and 1 × 1012 (blue) cm-2eV-1.

The contribution of the interface trap capacitance raises the minimum capacitance

of the device at low and high frequencies. A “true” high frequency (THF) curve may be

obtained if the measurement frequency is high enough (or measurement temperature low

enough, as shown later) to prevent interface traps from responding to the measurement

signal. A THF curve is modeled using (2.4), however, since interface traps maintain

equilibrium with the DC bias, the stretch-out along the voltage axis remains. Figure 2.11

is a plot of LF, HF, and THF C-V curves for an example MOS capacitor with an interface

trap density of 1 × 1012 cm-2eV-1.

26

0

0.05

0.1

0.15

0.2

0.25

-6 -4 -2 0 2 4

Cap

acita

nce

(µF/

cm2)

Gate Voltage (V)

COX

HfO2-n-Si

T = 300 Kε

S = 11.7

ni = 1.0 × 1010 cm-3

ND = 6.8 × 1016 cm-3

εOX

= 25

tOX

= 100 nm

LF

HF

true high frequency(THF)

DIT

= 1 ×1012 cm-2eV-1

Figure 2.11 Modeled LF (red), HF (green), and THF (blue) C-V curves for an example metal-HfO2-n-Si MOS capacitor with an interface trap density of 1 × 1012 cm-2eV-1.

While this simple, analytic model is a powerful pedagogical tool, establishing the

relationship between physical device properties and measured electrical characteristics, it

does not include quantum-mechanical (QM) effects, such as quantization in the inversion

or accumulation layers, that become important for thin-oxide and III-V-based MOS

devices. A device model that does take these QM effects into account is being developed

by Eric Vogel4 [64]. Vogel’s model contains an analytic correction to the classical MOS

model to account for surface quantization. This method, as opposed to numerical

solutions of the Schrödinger and Poisson equations, is less physically-sound but is much

simpler and requires less computational effort. Vogel has demonstrated the validity of his

model by showing agreement with numerical solutions over a range of oxide thicknesses

and semiconductor doping concentrations [64].

4 Formerly of the National Institute of Standards and Technology (NIST); presently with the University of Texas at Dallas

27

As oxide thickness decreases, oxide capacitance increases. As the oxide

capacitance increases, the semiconductor capacitance plays a larger role in the measured

MOS capacitance. The high surface electric field present in an MOS device in

accumulation or inversion forms a narrow potential well in which the accumulation or

inversion charge layer exists. This confinement leads to a quantization of the allowed

energy levels for carriers in these charge sheets. In an electron inversion or accumulation

layer, the ground state is above the conduction band edge, which effectively increases the

semiconductor bandgap, shifts the centroid of the charge sheet away from the oxide-

semiconductor interface, and reduces the accumulation or inversion semiconductor

capacitance. In an MOS device with a thick oxide layer, this is a negligible effect, since,

even with quantization, the semiconductor capacitance remains much higher than the

oxide capacitance. Figure 2.12, a comparison of the previously-described model (simple

model) and the Vogel model, demonstrates this fact, showing excellent agreement

between the two models for an example device with a 100-nm-thick oxide.

28

0

0.05

0.1

0.15

0.2

0.25

-4 -2 0 2 4 6

Cap

acita

nce

(µF

/cm

2 )

Gate Voltage (V)

COX

εS = 11.7

ND = 6.8 × 1016 cm- 3

εOX

= 25

tOX

= 100 nm

VFB

= +0.12 V

LF

HF

line - simple modelsymbols - Vogel model

Ti-HfO2-n-Si

1.0E+10ni (cm-3)

1.8E+19NV (cm-3)

3.2E+19

1.12

300 K

NC

(cm-3)

EG (eV)

Si

1.0E+10ni (cm-3)

1.8E+19NV (cm-3)

3.2E+19

1.12

300 K

NC

(cm-3)

EG (eV)

Si

Figure 2.12 Comparison of LF and HF C-V curves calculated using the simple model described earlier in this section (red lines) and the Vogel model (blue symbols) for an example metal-HfO2-n-Si MOS capacitor with a 100-nm-thick oxide layer.

When the oxide thickness is reduced to 2 nm, however, the effect of surface

quantization can be seen. Figure 2.13 compares the simple and Vogel models at LF and

HF for an example device with a 2-nm-thick oxide layer. The Vogel model (which

accounts for surface quantization) predicts the LF capacitance in accumulation and

inversion and the HF capacitance in accumulation to be significantly lower than that

predicted by the simple model, which saturates to the oxide capacitance.

29

0

2

4

6

8

10

12

-4 -2 0 2 4

Cap

acita

nce

(µF/

cm2 )

Gate Voltage (V)

COX

εS = 11.7

ND = 6.8 × 1016 cm-3

εOX

= 25

tOX

= 2 nm

VFB

= +0.12 V

LF

HF

simple modelVogel model

Ti-HfO2-n-Si

1.0E+10ni(cm-3)

1.8E+19NV (cm- 3)

3.2E+19

1.12

300 K

NC (cm-3)

EG (eV)

Si

1.0E+10ni(cm-3)

1.8E+19NV (cm- 3)

3.2E+19

1.12

300 K

NC (cm-3)

EG (eV)

Si

Figure 2.13 Comparison of LF and HF C-V curves calculated using the simple model described earlier in this section (red lines) and the Vogel model (blue symbols) for an example metal-HfO2-n-Si MOS capacitor with a 2-nm-thick oxide layer.

In a semiconductor with a low conduction or valence band effective density of

states, such as InAs, deviations from the simple model are seen even with a 100-nm-thick

oxide layer. Figure 2.14 compares the simple and Vogel models at LF and HF for an

example Ti-HfO2-n-InAs device with a 100-nm-thick oxide layer. The Vogel model

calculates electron and hole carrier densities using the conduction and valence band

density of states, respectively, as opposed to the simple model, which uses the intrinsic

carrier concentration for both electrons and holes. As a result, for InAs, the Vogel model

predicts an asymmetry in the LF inversion and accumulation capacitance saturation levels

not anticipated by the simple model. To demonstrate the dependence of the capacitance

saturation levels predicted by the Vogel model on the effective density of states, LF and

HF curves using equal conduction and valence band density of states are shown in Figure

2.15; the LF inversion and accumulation capacitance saturation levels are equal.

30

0

0.05

0.1

0.15

0.2

0.25

-4 -2 0 2 4

Cap

acita

nce

(µF/

cm2)

Gate Voltage (V)

COX

ND = 6.8 × 1016 cm-3

εOX

= 25

tOX

= 100 nm

LF

HF

line - simple theorysymbols - Vogel simulation

Ti-HfO2-n-InAs

1.3E+15n i (cm-3)

6.6E+18NV (cm-3)

8.7E+16

0.354

300 K

NC

(cm-3)

EG (eV)

InAs

1.3E+15n i (cm-3)

6.6E+18NV (cm-3)

8.7E+16

0.354

300 K

NC

(cm-3)

EG (eV)

InAs

εS = 12.3

VFB

= -0.61 V

Figure 2.14 Comparison of LF and HF C-V curves calculated using the simple model described earlier in this section (red lines) and the Vogel model (blue symbols) for an example metal-HfO2-n-InAs MOS capacitor with a 100-nm-thick oxide layer.

0

0.05

0.1

0.15

0.2

0.25

-4 -2 0 2 4

Cap

acita

nce

(µF/

cm2)

Gate Voltage (V)

COX

ND = 6.8 × 1016 cm-3

εOX

= 25

tOX

= 100 nm

LF

HF/DD

line - simple theorysymbols - Vogel simulation

Ti-HfO2-n-InAs

εS = 12.3

VFB

= -0.61 V

1.3E+15ni (cm-3)

1.2E+18NV (cm-3)

1.2E+18

0.354

300 K

NC (cm-3)

EG (eV)

InAs

1.3E+15ni (cm-3)

1.2E+18NV (cm-3)

1.2E+18

0.354

300 K

NC (cm-3)

EG (eV)

InAs

Figure 2.15 Comparison of LF and DD C-V curves from the simple model described earlier in this section (red lines) and LF and HF curves from the Vogel model (blue symbols) for an example metal-HfO2-n-InAs MOS capacitor with a 100-nm-thick oxide layer and NC = NV = ni

1/2.

31

2.3 MOS current-voltage modeling

When a bias is applied across an MOS capacitor, current flows through the oxide

layer. This leakage current can arise from several mechanisms including thermionic

emission [65], Frenkel-Poole (F-P) conduction [66], Fowler-Nordheim (F-N) tunneling

[67], and direct tunneling [12]. In this section, analytic models for direct tunneling and

thermionic emission are used to predict the contribution of each to the leakage current of

MOS capacitors fabricated in this work and to examine how physical parameters affect

I-V characteristics.

In ultrathin-oxide (4 nm or less) Si MOS capacitors, leakage current is dominated

by direct tunneling at room temperature when the applied bias is less than the metal-to-

oxide barrier height, φB [12]. Above φB, leakage current is best described by F-N

tunneling [67]. The barrier height of a device is found from its energy band diagram and

depends on the carrier type and bias polarity. Energy band diagrams at the flatband

condition for two MOS stacks fabricated in this work, Pd-HfO2-InAs and Ti-HfO2-InAs,

are shown in Figure 2.16.

Pd HfO2 InAsF M:

5.12 eV

2.4 eV

3.2 eVEG: 0.35 eV? : 4.9 eV

(a)

Ti HfO2 InAsF M:

4.33 eVEG: 0.35 eV?: 4.9 eV

2.4 eV

3.2 eV

(b)

Figure 2.16 Flatband diagrams of Pd-HfO2-InAs (a) and Ti-HfO2-InAs (b) heterostructures.

32

The diagrams in Figure 2.16 are calculated using the metal workfunctions of Pd

and Ti (5.12 and 4.33 eV, respectively), InAs electron affinity (4.9 eV), and HfO 2-InAs

conduction (? EC) and valence (? EV) band offsets (2.4 and 3.2 eV, respectively [68]). The

diagrams assume no charge at the oxide-semiconductor interface and that the metal

workfunctions on HfO2 are unchanged from their values in vacuum. Electrons tunneling

from the metal to the InAs conduction band see a barrier equal to

MSCB F?E +−∆=φ , (2.19)

while holes tunneling from the InAs valence band to the metal see a barrier equal to

VB E∆=φ . (2.20)

For positive gate bias, electrons tunneling from the InAs conduction band to the metal see

a barrier equal to

CB E∆=φ , (2.21)

while no holes exist in the metal to tunnel to the InAs.

For both Ti and Pd in positive and negative gate bias, electrons have a lower

tunneling barrier than the holes and thus, contribute most to the tunneling current. Table

2.1 lists the electron tunneling barrier heights for Ti- and Pd-HfO2-InAs heterostructures

in positive and negative gate bias. From Table 2.1 (and Figure 2.16), it can be seen that

the Pd-based heterostructure is the most symmetric. Given this, one expects the Pd-HfO2-

InAs J-V characteristic to be more symmetric, while the Ti-HfO2-InAs J-V should exhibit

increased current in the negative bias over positive bias.

33

TABLE 2.1

ELECTRON TUNNELING BARRIER HEIGHTS FOR TITANIUM- AND

PALLADIUM-HFO2-INAS MOS HETEROSTRUCTURES

φB

(eV) Pd-HfO2-InAs Ti-HfO2-InAs

VG < 0 2.62 1.83

VG > 0 2.4 2.4

The semi-empirical, ultrathin-oxide, direct tunneling model of Lee and Hu [69] is

used to calculate I-V curves for metal-HfO2-InAs-based MOS capacitors. To simplify the

calculation, the flatband voltage is set equal to zero and the accumulation bias (VG > 0) is

considered. Electron tunneling from the conduction band is assumed to be the dominant

tunneling mechanism. The model parameters are varied and the results plotted to

demonstrate their effect on the J-V characteristics.

After [69], the direct tunneling current density, J, is given by

−−−=

2/32/3*2

11/3

)(28exp),,,(

8 B

OX

OXOX

BOXBOXOXG

BOX

VtVhq

qmtVVC

hq

Jφ

φπφ

φεπ, (2.22)

where h is Planck's constant and *OXm is the tunneling effective mass in the oxide. The

correction factor, C, is given by

SOX

G

B

OX

B

BOX

BBOXOXG Q

tVVV

tVVC

−

+

−=

φφφ

φφ 11

20exp),,,( , (2.23)

34

where QS is the charge in the semiconductor, calculated from (2.5). The only fitting

parameters in this simplified version of the model are the effective tunneling mass of the

oxide and the barrier height. Figure 2.17 is a plot of room-temperature, accumulation-

regime J-V characteristics for metal-HfO2-InAs heterostructures with oxide layer

thicknesses of 2.5, 5.0, and 7.5 nm calculated using (2.22) and (2.23). The barrier height

is set equal to the HfO 2-InAs conduction band offset, 2.4 eV, and the effective tunneling

mass is set to 0.14m0 after [70]. The substrate doping is 2 × 1016 cm-3 n-type.

10-13

10-9

10-5

10-1

103

0 0.5 1 1.5 2 2.5 3

Dire

ct T

unne

ling

Cur

rent

(A/c

m2 )

Gate Voltage (V)

T = 300 Kφ

B = 2.4 eV

mOX

* = 0.14m0

ND = 2 × 1016 cm-3

tOX

= 2.5 nm

5.0 nm

7.5 nm

metal-HfO2-InAs

Figure 2.17 Modeled room-temperature, accumulation-regime, direct tunneling J-V characteristics for a metal-HfO2-InAs heterostructure with oxide layer thicknesses of 2.5 (green), 5.0 (blue), and 7.5 (red) nm.

Direct tunneling current shows a large sensitivity to oxide thickness and as a

result, can be used to measure the thickness of the oxide layer in MOS gate stacks when

the barrier height and tunneling mass are known [69]. The equipment used to measure the

device characteristics in this work (described in Section 2.6) has an open-circuit current

sensitivity on the order of 200 fA. The largest metal contact area for devices in this work

is 7.2 × 10-5 cm-2 (85 × 85 µm2), therefore, the lowest detectable current density is on the

35

order of 3 × 10-9 A/cm2. In terms of this practical limitation, direct tunneling current in

the metal-InAs-HfO2 system does not become significant until the oxide thickness is

scaled below 7.5 nm.

Figure 2.18 plots the J-V curves for metal-HfO2-InAs heterostructures with a

fixed thickness of 5.0 nm, a tunneling mass of 0.14m0, and barrier heights of 1.8, 2.1, and

2.4 eV. For a given oxide thickness and tunneling mass, the barrier height affects the

curvature of the J-V characteristic, with decreased barrier height resulting in an increased

slope. This increase is most pronounced near zero bias and levels off as the bias is

increased. From the modeled characteristics, it is shown that with an oxide thickness of

5.0 nm, the direct tunneling component of leakage current will be above the measurement

noise level over the range of anticipated barrier heights for the devices in this work.

10-10

10-6

10-2

0 0.5 1 1.5 2 2.5 3

Dire

ct T

unne

ling

Cur

rent

(A/c

m2 )

Gate Voltage (V)

T = 300 KtOX

= 5.0 nm

mOX

* = 0.14m0

ND = 2 × 1016 cm-3

φB = 1.8 eV

2.12.4

metal-HfO2-InAs

Figure 2.18 Modeled room-temperature, accumulation-regime, direct tunneling J-V characteristics for a metal-HfO2-InAs heterostructure with electron tunneling barrier heights of 1.8 (green), 2.1 (blue), and 2.4 (red) eV.

36

Values for the oxide effective tunneling mass range from 0.14 – 0.17 m0 for HfO2

[70, 71] to 0.41m0 for jet-vapor-deposited (JVD) Si3N4 [71]. Figure 2.19 plots metal-

HfO2-InAs J-V curves for tunneling masses of 0.14, 0.2, and 0.4 m0, with a fixed oxide

thickness of 5.0 nm and barrier height of 2.4 eV. From the plot tunneling mass is seen to

affect both the curvature and magnitude of the J-V characteristic. Based on this model,

the HfO2 films in this work should exhibit detectable levels of direct tunneling if the

tunneling mass is near the reported values.

10-13

10-9

10-5

10-1

0 0.5 1 1.5 2 2.5 3

Dire

ct T

unne

ling

Cur

rent

(A

/cm

2 )

Gate Voltage (V)

T = 300 Kφ

B = 2.4 eV

tOX

= 5.0 nm

ND = 2 × 1016 cm-3

mOX

* = 0.4m0

0.2

0.14metal-HfO2-InAs

Figure 2.19 Modeled room-temperature, accumulation-regime, direct tunneling J-V characteristics for a metal-HfO2-InAs heterostructure with oxide tunneling effective masses of 0.14 (red), 0.2 (blue), and 0.4 (green) m0.

As in the simple C-V model described in the previous section, temperature

influences the direct tunneling model through the intrinsic semiconductor carrier

concentration as well as the temperature parameter. By adjusting both accordingly, J-V

curves for a metal-HfO2-InAs heterostructure with an oxide thickness of 5.0 nm, barrier

height of 2.4 eV, and effective tunneling mass of 0.14m0 are predicted for liquid nitrogen

37

(77 K), room (300 K), and 100 °C (373 K) temperatures and shown in Figure 2.20. Direct

tunneling exhibits only weak dependence on temperature. Temperature dependence

measurements can be used to distinguish direct tunneling from other leakage mechanisms

in MOS heterostructures.

10-13

10-9

10-5

10-1

0 0.5 1 1.5 2 2.5 3

Dire

ct T

unne

ling

Cur

rent

(A

/cm

2 )

Gate Voltage (V)

φB = 2.4 eV

tOX

= 5.0 nm

mOX

* = 0.14m0

ND = 2 × 1016 cm- 3

373 K300 K77 K

metal-HfO2-InAs

1.3E+15

300 K

6.1E+155.4E+3n i (cm-3)

373 K77 KInAs

1.3E+15

300 K

6.1E+155.4E+3n i (cm-3)

373 K77 KInAs

Figure 2.20 Modeled accumulation-regime, direct tunneling J-V characteristics for a metal-HfO2-InAs heterostructure at 77 (blue), 300 (green), and 373 (red) K.

Thermionic emission can contribute to leakage in MOS heterostructures with

ultrathin films, especially at elevated temperature [65]. The thermionic emission current

over the oxide barrier in an MOS heterostructure can be modeled by

−

−= 1expexp2*

TkqV

Tkq

TAJB

OX

B

Bφ , (2.24)

where A* is the Richardson coefficient, given by

3

2** 4

hkqm

A Bnπ= , (2.25)

38

where *nm is the electron effective mass in the semiconductor. This is a simple model that

does not include an empirical modification to the Richardson coefficient or the ideality

factor, n. The only adjustable device parameters in this model are the barrier height and

semiconductor effective mass. However, the model is still useful for predicting how

physical parameters influence the J-V characteristics. Figure 2.21 shows predicted room-

temperature, thermionic J-V curves for an electron effective mass of 0.023m0 (the value

for the InAs G-valley [72]) and barrier heights of 1.8, 2.1, and 2.4 eV. Here, unlike the

direct tunneling and C-V models, the entire gate voltage is assumed to drop across the

oxide (VG = VOX). From (2.24) and Figure 2.21, the slope of the J-V is independent of

barrier height and is set by kBT/q. Lowering the barrier height increases the current

exponentially for a given gate bias. In this ideal, simplified case, thermionic emission

becomes comparable to direct tunneling current in the 1 – 2 V range.

10-13

10-9

10-5

10-1

0 1 2 3

Ther

mio

nic

Cur

rent

(A

/cm

2 )

Gate Voltage (V)

T = 300 Km

n* = 0.023m

0

metal-HfO2-InAs

φB = 2.4 eV1.8 2.1

Figure 2.21 Modeled room-temperature, accumulation-regime, thermionic J-V characteristics for a metal-HfO2-InAs heterostructure with oxide barrier heights of 1.8 (green), 2.1 (blue), and 2.4 (red) eV.

39

The other adjustable device parameter in the model, semiconductor effective

mass, is shown to have a similar influence on the J-V characteristic as the barrier height

in Figure 2.22. Like barrier height, changing the effective mass shifts the J-V curve while

maintaining a constant slope (set by kBT/q). However, the shift is smaller, as thermionic

current is linearly dependent on effective mass and exponentially dependent on barrier

height.

10-13

10-9

10-5

10-1

0 1 2 3

Ther

mio

nic

Cur

rent

(A

/cm

2 )

Gate Voltage (V)

T = 300 Kφ

B = 2.4 eV

metal-HfO2-InAs

mn* = 0.023m

0

0.23m0

m0

Figure 2.22 Modeled room-temperature, accumulation-regime, thermionic J-V characteristics for a metal-HfO2-InAs heterostructure with semiconductor effective masses of 0.023 (red), 0.23 (blue), and 1 m0.

As seen in (2.24), thermionic emission has components that exhibit exponential

and square dependence on temperature. As seen in Figure 2.23, which plots thermionic

current for a 2.4 eV barrier and 0.023m0 effective mass at 77, 300, and 373 K,

temperature influences both the magnitude and slope of the J-V curve. The magnitude

exhibits a T2-dependence while the slope is modified through kBT/q. This temperature

dependence is in stark contrast to the predicted temperature dependence of direct

tunneling current and can be used to distinguish between the two mechanisms.

40

10-13

10-9

10-5

10-1

0 1 2 3

Ther

mio

nic

Cur

rent

(A

/cm

2 )

Gate Voltage (V)

mn* = 0.023m

0

φB = 2.4 eV

InAs-HfO2-InAs

T = 373 K

300 K 77 K

Figure 2.23 Modeled accumulation-regime, thermionic J-V characteristics for a metal-HfO2-InAs heterostructure at 77 (blue), 300 (green), and 373 (red) K.

The direct tunneling and thermionic emission models can be combined to predict

the temperature dependence of metal-HfO2-InAs heterostructures. Figure 2.24 contains

the predicted total leakage current of metal-HfO2-InAs heterostructures with oxide

thicknesses of 5.0 (a) and 7.5 (b) nm. To increase accuracy, the VG-VOX relationship

calculated from the direct tunneling and C-V models was incorporated into the calculation

of thermionic current. A semiconductor effective mass of 0.023m0, oxide barrier height of

2.4 eV, oxide effective tunneling mass of 0.14m0, semiconductor doping concentration of

2 × 1016 cm-3, and intrinsic semiconductor carrier densities shown in the Figure 2.24 table

insets are used for the model.

41

10-13

10-9

10-5

10-1

0 1 2 3

Leak

age

Cur

rent

(A/c

m2 )

Gate Voltage (V)

metal-HfO2-InAs

T = 373 K300 K77 K

1.3E+15

300 K

6.1E+155.4E+3ni (cm -3)

373 K77 KInAs

1.3E+15

300 K

6.1E+155.4E+3ni (cm -3)

373 K77 KInAs

mn* = 0.023m

0

φB = 2.4 eV

mOX

* = 0.14m0

ND = 2 × 1016 cm- 3

tOX

= 5.0 nm

(a)

10-13

10-9

10-5

10-1

0 1 2 3Gate Voltage (V)

metal-HfO2-InAs

T = 373 K

300 K

77 K

mn* = 0.023m

0

φB = 2.4 eV

mOX

* = 0.14m0

ND = 2 × 1016 cm-3

tOX

= 7.5 nm

1.3E+15

300 K

6.1E+155.4E+3n i (cm-3)

373 K77 KInAs

1.3E+15

300 K

6.1E+155.4E+3n i (cm-3)

373 K77 KInAs

Leak

age

Cur

rent

(A/c

m2 )

(b)

Figure 2.24 Modeled total accumulation-regime J-V characteristics for metal-HfO2-InAs heterostructures with oxide thicknesses of 5.0 (a) and 7.5 (b) nm at 77 (blue), 300 (green), and 373 (red) K.

The model predicts that as the oxide layer thickness is increased, the contribution

of thermionic emission becomes apparent at lower gate biases. The onset of thermionic

current creates a kink in the J-V characteristics, above which leakage current becomes

more sensitive to temperature. It should be noted, however, that in this simulation the

42

kink appears near the measurement equipment noise level and may not be observed in

practice.

2.4 Measurement of MOS capacitor impedance

Impedance-voltage and impedance-frequency measurements are taken on metal-

high-k-InAs capacitors using an Agilent 4294A precision impedance analyzer (PIA)

connected to a Cascade Microtech probe station. The 4294A uses the auto-balancing

bridge (ABB) method to measure the complex impedance of the device under test (DUT)

at frequencies from 40 Hz to 110 MHz, AC oscillation levels from 5 mV to 1 V rms, and

DC biases from 0 to ±40 V [73]. The system features a 4-terminal-pair (4TP)

configuration that allows Kelvin measurements to be used, eliminating the effect of lead

cable resistance. The Cascade probe station features an enclosure that provides thermal

and electromagnetic isolation from the environment and device wafer cooling and heating

(-50 – 200 °C) through a closed- loop, wafer-chuck-temperature control system.

The ABB method uses an operational amplifier (op amp) to create a “virtual

ground” at the low-potential terminal (LOPOT) of the DUT. Also connected to the

LOPOT is a range resistor through which the same current as the DUT flows. In this

configuration, the op amp serves as a current-voltage converter; the measurement of

voltage across the range resistor allows one to calculate the current through the DUT. A

voltage measurement at the high-potential terminal (HIPOT) of the DUT gives the

voltage across the DUT. With the voltage and current through the DUT known, the

impedance is calculated. Since an AC signal as well as a DC bias is applied to the DUT,

the measured impedance is a vector (complex) quantity. In the 4294A, this complex

43

impedance is separated into real and imaginary (or 0° and 90°) components by digital

processing.

The complex impedance may be represented in a number of ways including:

impedance magnitude (|Z|) and phase (?), reactance (X) and resistance (R), equivalent

parallel capacitance (CP) and conductance (G), or equivalent series capacitance (CS) and

resistance (RS). In an ideal measurement with a lossless capacitor and perfect calibration

(effects of stray capacitances associated with probes, cabling, and other measurement

equipment completely eliminated), the equivalent parallel or series capacitance is equal to

the actual DUT capacitance. In practice however, as shown later, capacitor leakage

current and calibration errors cause deviations from the ideal case and must be taken into

consideration when interpreting measurement results.

Given the sensitivity of measured MOS device characteristics to equipment setup

and calibration, care is taken to ensure that measurement results (and the quantities

calculated from them) accurately represent the DUT and are free of measurement

artifacts. The configuration of the measurement equipment is described and variations of

procedures, settings, and the resulting characteristics are reviewed to establish the

accuracy of measurements presented in this work.

2.4.1 Impedance measurement connection configurations

The PIA has four bayonet Neill-Concelman (BNC) input terminals: HIPOT,

LOPOT, high-current (HICUR), and low-current (LOCUR). In this configuration,

separate force and sense terminal pairs allows the DUT to be measured in a Kelvin

configuration, similar to four-point-probe resistivity measurements. The two electrodes of

vertical MOS devices are connected to the PIA input terminals typically in one of two

44

ways: to two top surface contacts with designation top-to-top (TTT) or from one top

surface contact to the wafer backside contact on the wafer chuck designated top-to-chuck

(TTC).The two connection methods are shown schematically in Figure 2.25. In both

methods, unless otherwise specified, measurements are taken in the dark to avoid

photogeneration in the semiconductor. The probe station used in these measurements is

the Cascade Summit 11000 series with a top hat to block room light and enable a nitrogen

purge to remove room air.

metalhigh-kInAs

probe to HI

top-to-top (TTT)

LO

metal

LO

HI

InAs

top-to-chuck (TTC)

high-k

(a) (b)

Figure 2.25 Schematic diagrams of top-to-top (a) and top-to-chuck (b) measurement connections to metal-high-k-InAs MOS structures. The label HI indicates connections at the probe to both HIPOT and HICUR cables and LO connects similarly to both LOPOT and LOCUR cables.

In the TTT configuration, a 1-m BNC-SSMC coaxial cable (Cascade part # 105-

540) is connected to each of the input terminals. The HIPOT and HICUR cables are

connected directly (no intermediate cables or connections between the input terminals

and the probe) to one probe (Cascade DCP 100 or HTR series) and the LOPOT and

LOCUR cables are connected to another. Since the potential and current terminals are

connected near each of the probes tips, the effect of most of the cable resistance is

eliminated. With the potential and current terminals connected, the measurement is

45

treated as a two-terminal measurement and the inputs are hereafter referred to simply as

HI and LO. At the probe station, the probes are placed over the wafer chuck such that the

probe tips are less than 1 cm apart. Precise positioning of the probes is achieved with the

probe station’s micrometers. The probe positions are adjusted such that when the stage

(the platform on which the probe micrometers rest) is lowered toward the wafer chuck,

the probes establish an electrical connection to the terminals of the DUT. It is important

that the probe position remain unchanged between device measurements, as the PIA

calibration zeros out parasitic impedances and therefore is specific to each probe

arrangement. At the probes, a guard short cable (Cascade part # 123-625) connects the

outer shields of the high and low terminals.

Figure 2.26 shows how probes are placed for a TTT measurement. Since the

connections to HI and LO are made with probes located on the top surface of the wafer,

the MOS capacitor must either have a topside ohmic contact to the semiconductor or, in

some cases, a connection to the semiconductor via a large-area MOS capacitor whose

impedance is resistive and much lower than the impedance of the DUT. This behavior is

confirmed by measuring the leakage current of the large-area device. Figure 2.27 is the I-

V characteristic of a Au-Ti-HfO2-InAs MOS heterostructure measured between the large-

area, top-side contact and wafer backside (a TTC measurement). The HfO 2 of this

structure is grown with 150 ALD cycles. Since this is the most ALD cycles used for

devices in this work, it represents a worst-case scenario for TTT series resistance. Over

the range of -1 to +1 V, the I-V behavior is symmetric and can be approximated by a

series resistance of ~75 O.

46

waferchuck

probestage

guard shortHI LO

large-area device

device grid

HI

LO

(a) (b)

Figure 2.26 Illustration of TTT measurement configuration (a) and plan-view optical micrograph of metal-high-k-InAs MOS device wafer showing probe placement in TTT measurement configuration (b). Graphic in (a) from [74].

-0.08

-0.04

0

0.04

0.08

-4 -2 0 2 4

Leak

age

Cur

rent

(A)

Gate Voltage (V)

Au-Ti-HfO2-InAs

BHF pretreatment250 °C growth temperature

150 ALD cycles11.9 nm HfO

2 as measured by ellipsometry

large-area device (~1 cm2)

R(V = ±1 V) ~ 75 Ω

large-area MOS leakage measured between top contact and wafer backside

ideal 75 Ω

Figure 2.27 Large-area (~1 cm2) Au-Ti-HfO2-InAs MOS heterostructure leakage current as measured between the top contact and wafer backside.

In the TTC measurement configuration, the LOPOT and LOCUR terminals of the

PIA are connected via 1 m coaxial cables to a grounded connecting plate where the

ground attaches to the body of the probe station. The transition from BNC-to-triaxial

47

cable is made at the connecting plate. The BNC-to-triaxial adapters come in two

varieties: grounded- and floating-guard. The grounded-guard adapter connects the shield

(outer conductor) of the coaxial cable to the guard (middle conductor) of the triaxial input

of the probe station connection plate as well as the shield The floating-guard adapter does

not connect the shield of the coaxial cable to the triaxial shield. The triaxial cables

connect to SMA connectors of the probe micrometers, which are connected to the SSMC

ports of the probe. The HOPOT and HICUR terminals are connected via coaxial cables

with triaxial adapters to the two chuck bias input ports of the probe station. Connection of

the high input to the chuck (as opposed to the probe) prevents stray current flowing

between the chuck and earth ground from influencing the measured impedance. While

the high terminal is connected to the substrate backside, all quoted values of DC bias in

this thesis, termed “gate voltage,” are given with respect to the top surface contact and

ground. An illustration of the TTC measurement configuration is shown in Figure 2.28.

waferchuck

probestage

HI

LO

Figure 2.28 Illustration of TTC measurement configuration. Graphic from [74].

A third connection method for low-temperature (LT) measurements is used which

combines aspects of the TTT and TTC configurations. For LT measurements, device

wafers are mounted with conductive adhesive (silver paint) to a stainless steel block. The

48

block is placed in a Petri dish and the TTT cabling scheme is used to connect two probes

to the PIA. However, rather than through a large-area device, a device backside

connection is established through connection of the high probe to the stainless steel. The

stainless steel serves as a cold finger and is cooled by filling the Petri dish with liquid

nitrogen. The LT connection configuration is illustrated in Figure 2.29.

wafer chuck

LO

stainless steel

DUT

HI

liquidnitrogenPyrex

Figure 2.29 Illustration of LT measurement configuration.

2.4.2 Impedance measurement calibration

For an accurate characterization of the DUT, stray capacitances (that exist

between the cables and probes and nearby conductors or between the chuck and earth

ground) and lead inductances due to cables are removed from the measured impedance

through equipment calibration. The measurement of known impedance standards allows

one to characterize the impedance associated with the measurement setup. The

impedance standards are measured over the same frequency range as the DUT, since

stray impedance is frequency-dependent. With the impedance due to the setup known, the

measured impedance of a DUT is corrected to reflect the impedance of only the DUT,

without parasitics.

One of two calibration procedures are used with the PIA: open-short (OS) or

open-short- load (OSL). In OS calibration, the open- and short-circuit impedances of the

49

setup are measured. In OSL calibration, a load standard (usually a 50 O resistor) is

measured in addition to open and short standards. For TTT calibration, Cascade provides

an impedance standard substrate (ISS) that contains OSL standards as well as a capacitor

standard that allows the measurement accuracy to be checked after calibration. For TTC

calibration, open and short measurements are performed with the top probe raised just

above the device and contacted directly to the wafer chuck, respectively. Cascade does

not provide resistance or capacitance standards for the TTC configuration; however,

surface-mount resistors and capacitors are readily made into suitable standards.

The PIA also offers an additional calibration referred to as phase compensation

(PC). Phase compensation accounts for the signal phase shift that occurs as a result of the

non-zero electrical length, the product of the transmission line propagation constant and

physical length of the cabling between the zero-plane input terminals of the PIA and the

DUT. The phase shift due to non-zero cable length is important when the wavelength of

the measurement signal is comparable to the cable length. The free-space wavelength of a

1 MHz signal is 300 m. Since the cables used are on the order of 1 m, the phase shift

correction is not large at 1 MHz, affecting accuracy in the fourth decimal place. For 10

MHz with a wavelength of 30 m, measurement is off by a little more than 2% without

PC, For the measurements reported, PC is used as a matter of good practice.

2.4.3 Comparison of connection configurations and calibration procedures

The TTT, TTC, and LT measurement configurations using OS, OSL, and PC are

compared in this section using measurements on reference capacitors of varying

impedances. The results illustrate the effect of connection and calibration procedures on

device characterization. Surface-mount 50 O resistors and 1000 pF capacitors are

50

modified to enable use as a DUT in TTT, TTC, and LT configurations. Figure 2.30 is the

I-V characteristic of one of the 50 O load standards plotted against an ideal 50 O device.

The standard shows excellent agreement with the ideal case.

-0.1

-0.05

0

0.05

0.1

-4 -2 0 2 4

Cur

rent

(A

)

Voltage (V)

50 Ω load standard #1ideal 50 Ω

Figure 2.30 Current-voltage characteristic of a surface-mount 50 O resistor used as a load standard for TTC and LT calibrations (red) plotted against an ideal 50 O resistor (black).

Figure 2.31 is the complex-impedance-frequency characteristic of the 50

Ω standard of Figure 2.30 measured TTC using OS calibration and PC. The fact that the

magnitude of the impedance does not agree with the I-V data is not cause for concern, as

the purpose of the standard is to provide a reference point for subsequent measurements.

The phase angle is nearly zero over most of the measured frequency range, indicative of a

purely resistive impedance. The impedance behavior is continuous in frequency up to just

above 1 MHz, showing that the 50 Ω standard provides a good reference up to this

frequency.

51

-20

0

20

40

60

80

100

-180

-90

0

90

180

102 103 104 105 106 107

|Z| (

Ω) θ (°)

f (Hz)

50 Ω load standardOS calibration

phase comp.: 4TP-2m25 mV osc. level, 0 VDC

Figure 2.31 Complex- impedance-frequency characteristic of 50 O load standard measured TTC using OS calibration and PC.

A surface-mount 1000 pF capacitor and Au-Ti-HfO2-InAs heterostructures with

films grown using 30, 40, and 50 ALD cycles are measured TTC with OS and OSL

calibrations and PC to determine the influence of calibration method on measured device

characteristics as a function of DUT impedance. The varied number of ALD cycles used

in the formation of the MOS heterostructures provides an impedance that scales with

HfO2 film thickness. Decreasing film thickness increases the capacitance and

conductance of an MOS device, both of which serve to decrease the impedance.

Examining measurement results as a function of DUT impedance is important because

the accuracy of the ABB technique is dependent upon the impedance being measured.

Figure 2.32 contains the measured TTC C-V curves of the surface-mount

capacitor and the MOS heterostructures using OS and OSL calibrations. The

measurement frequency is 1 MHz, the signal amplitude is 25 mV rms, and PC is used.

The capacitance plotted is the equivalent parallel capacitance, CP, computed by the PIA

52

from the complex impedance. The measured capacitance of the 1000-pF capacitor is

constant across the entire DC bias range and is within the manufacturer tolerance of

±10% for both OS and OSL calibrations. The unusual C-V characteristic of the 30-ALD-

cycle heterostructure is due to large leakage through the device due to direct tunneling

which causes the ABB measurement circuit to become unbalanced and give inaccurate

readings.

The figure inset is the percentage diffe rence between the measured capacitances

(calculated at the maximum capacitance value) for each device plotted versus device

impedance (also calculated at the maximum capacitance value). Over the entire

impedance range measured (160 – 560 O), the capacitance varies by only 5 – 7 %

between OS and OSL calibrations. For device impedances of interest in this work, load

calibration does not introduce a significant change to the measured capacitance for the

TTC connection at 1 MHz.

53

0

2 10-10

4 10-10

6 10-10

8 10-10

1 10-9

-1 0 1

CP (F

)

Gate Voltage (V)

1000 pF capacitor

dashed - OSsolid - OSL

85 × 85 µm2HCl pretreatment

300 °C growth temperature200 °C, 1 hour, N

2 PMA

30 ALD cycles4050

Au-Ti-HfO2-InAs:

0

1

2

3

4

5

6

7

100 200 300 400 500 600

CP C

hang

e (%

)

Impedance (Ω)

% change in measured capacitanceby adding load calibration versus

device impedance

1 MHz, 25 mV osc.grounded guard TTC, 2 m PC

Figure 2.32 Measured TTC C-V characteristics of surface-mount 1000-pF capacitor (orange) and Au-Ti-HfO2-InAs heterostructures with HfO 2 layers grown using 30 (red), 40 (blue), and 50 (green) ALD cycles using OS (dashed) and OSL (solid) calibrations. The AC signal frequency is 1 MHz with an amplitude of 25 mV rms. PC is used for both calibrations.

In a TTC measurement, the 1 m coaxial cables connected to the input terminals of

the PIA are connected to the connecting plate of the probe station with either floating- or

grounded-guard coaxial-to-triaxial adapters. Figure 2.33 is the equivalent parallel

capacitance and absolute value of the conductance versus frequency of an Al-SiO2-Si

MOS capacitor using floating- and grounded-guard adapters. The SiO2 film is grown by

rapid thermal oxidation and is 2.2 nm thick. The Si is doped n-type. The geometric

capacitance (assuming a SiO 2 dielectric constant of 3.9e0) is 277 pF. The OSL calibration

is performed using floating-guard adapters. The system is not recalibrated when the

grounded-guard measurement is made. Even without recalibration, no differences are

observed in the capacitance or conductance over the entire frequency range.

54

0

1 10-10

2 10-10

3 10-10

10-9

10-7

10-5

10-3

102 103 104 105 106 107

CP (

F) |G

| (S)

f (Hz)

floating guardgrounded guard

150 µm diameter

Al-2.2 nm SiO2-n-Si

25 mV osc., 0 VDC TTC, 2 m PC

OSL calibration

Figure 2.33 Measured equivalent parallel capacitance and conductance versus frequency of an Al-SiO2-Si MOS capacitor using TTC connection, OSL calibration, and PC with floating- (red) and grounded- (blue) guard coaxial-to-triaxial adapters. The AC signal amplitude is 25 mV rms and the DC bias is 0 V.

Figure 2.34 contains the measured C-V curves of the 1000 pF surface-mount

capacitor and the 30-, 40-, and 50-ALD-cycle Au-Ti-HfO2-InAs MOS heterostructures

using TTT and TTC connections. The measurement frequency is 1 MHz, the signal

amplitude is 25 mV rms, and OSL and PC are used for calibration. The capacitance

plotted is the equivalent parallel capacitance. The measured capacitance of the 1000 pF

capacitor is within the manufacturer tolerance for both connection methods and shows no

bias dependence. For the MOS device with the 50-ALD-cycle HfO 2 film (the device with

the highest impedance), there is excellent agreement between the TTT and TTC

measurements (< 2% difference). However, as DUT impedance decreases (capacitance

increases), the discrepancy between the TTT- and TTC-measured curves increases.

Differences between measured C-V characteristics are not necessarily indicative of one

connection method’s superiority over another, but could be related to the series resistance

55

associated with each connection; the TTT series resistance is related to the resistance of

the large-area MOS capacitor through which the connection to the semiconductor is

made, while the TTC series resistance is related to the resistance of the semiconductor

bulk and backside contact. The correction of measured C-V curves for series resistance is

discussed in Section 2.5. The TTT and TTC curves of the 40-cycle device and the 1000

pF capacitor differ by about 7%. As with the calibration comparison, the large leakage of

the 30-cycle device gives rise to an unusual characteristic and an increased sensitivity to

measurement procedure. The data of Figure 2.34 can be used to conclude that, for low-

leakage devices, the TTT and TTC connection methods, if properly calibrated, give

comparable results.

0

2 10-10

4 10-10

6 10-10

8 10-10

1 10-9

-1 0 1

CP (

F)

Gate Voltage (V)

1000 pF capacitor1 MHz, 25 mV osc.

OSL calibrationgrounded gaurd

TTT: 1 m PC TTC: 2 m PC

85 × 85 µm2

lines - TTTsymbols - TTC

HCl pretreatment300 °C growth temperature

200 °C, 1 hour, N2 PMA

30 ALD cycles4050

Au-Ti-HfO2-InAs:

Figure 2.34 Measured TTT (lines) and TTC (symbols) C-V characteristics of surface-mount 1000 pF capacitor (orange) and Au-Ti-HfO2-InAs heterostructures with HfO 2 layers grown using 30 (red), 40 (blue), and 50 (green) ALD cycles. The AC signal frequency is 1 MHz with an amplitude of 25 mV rms. OSL calibration and PC are used for both TTT and TTC.

A 1000 pF surface-mount capacitor with one lead in contact with the stainless

steel block used for low-temperature measurements is connected to the PIA using the LT

56

connection configuration, Figure 2.29, and measured at room temperature using OS and

OSL calibrations. Figure 2.35 is the equivalent parallel capacitance of the device plotted

versus voltage. The open calibration is performed with the probes lifted up from the

stainless steel block, the short calibration is performed with both probes in contact with

the block, and load calibration is performed with a surface-mount 50 O resistor mounted

like the capacitor to the block. As with the TTT and TTC connection methods, the

measured capacitance of the capacitor is within the manufacturer tolerance for both OS

and OSL calibration procedures and exhibits no bias dependence.

0

2 10-10

4 10-10

6 10-10

8 10-10

1 10-9

-2 0 2Gate Voltage (V)

1000 pF capacitor

dashed - OSsolid - OSLC

P (

F) 1 MHz, 25 mV osc.LT connection method

grounded gaurd2 m PC

Figure 2.35 Measured LT-connection-method C-V characteristics of surface-mount 1000 pF capacitor with OS (dashed) and OSL (solid) calibration. The AC signal frequency is 1 MHz with an amplitude of 25 mV rms. PC is used for both OS and OSL.

In summary, using surface-mount 50 O resistors and 1000 pF capacitors, a Si

MOS capacitor, and InAs MOS capacitors, the measurement configurations and

calibration options used in this work were explored experimentally to establish the kind

of uncertainty that can arise in these measurements even with calibration. The measured

57

capacitance differs by ~7% between different connections and calibration procedures.

The choice of coaxial- to-triaxial adapter type is shown to have a negligible impact on

measured capacitance over a wide frequency range for measured capacitances in the

range of hundreds of picofarads.

2.4.4 Influence of PIA settings on impedance characteristics

There are a number of adjustable parameters available on the PIA. The

measurement parameters relevant to MOS characterization are adjusted and

measurements are performed to determine the sensitivity of results to these parameters.

The sweep delay is the amount of time the DUT is held at the starting

measurement conditions before a DC bias or frequency sweep is made. A sweep delay

gives the DUT time to reach equilibrium conditions before measurements are recorded.

For a capacitor measurement, the sudden application of a DC bias (as can occur at the

beginning a C-V measurement) results in a disruption of the equilibrium that takes time to

reestablish; during this time the apparent capacitance of the DUT will change.

Figure 2.36 plots the measured equivalent capacitance as a function of time at a

fixed gate bias of +2 V for a Au-Ti-HfO2-InAs MOS capacitor formed using 75 ALD

cycles and a growth temperature of 200 °C. The measurement is performed TTC at 10

kHz with a 25 mV rms signal. At time t = 0, the measured capacitance is at its maximum

value. Over the course of 60 s, the measured capacitance decays to 96% of its initial

value. Assuming a device series resistance of 75 O and a capacitance of 150 pF, the RC

time constant is only 11 ns, so displacement current is ruled out as a contributor to this

effect. The measurement is taken in accumulation so minority carrier response is also

ruled out. Interface traps, however, can have time constants on the order of seconds or

58

more [75] and are likely responsible for the prolonged decay of the measured device

capacitance over time. A technique known as “prebiasing,” whereby a device is held at a

bias prior to the start of a sweep, may be used to bring devices into a quasiequilibrium;

this time can be long, e,g, twenty minutes for GaAs MOS [75].

153

154

155

156

157

158

159

160

0 10 20 30 40 50 60

Cap

acita

nce

(pF)

time (s)

Au-Ti-HfO2-InAs

HCl pretreatment200 °C growth temperature

75 ALD cycles400 °C, 2 min., N

2 PMA

TTC, OS, PC10 kHz, 25 mV osc.

BW 4, pt. avg. 40 s sweep delay

VG = +2 VDC

85 × 85 µm2

Figure 2.36 Measured capacitance versus time for a Au-Ti-HfO2-InAs MOS capacitor formed using 75 ALD cycles and a 200 °C growth temperature. The DC bias is fixed at +2 V. The measurement frequency is 10 kHz and signal amplitude is 25 mV rms.

Figure 2.37 shows the capacitance-time behavior of the same device at additional

DC biases. The percentage change in capacitance over 60 s scales with absolute gate bias.

At -2 VDC, the capacitance drops to 92% of its initial value while at 0 VDC, the

capacitance remains at 100% of its initial value. The larger gate biases bend the bands of

the InAs to a greater extent, and therefore, a longer time is required to reach equilibrium.

Since the device measured has a non-zero flatband voltage, the gate-voltage-surface-

potent ial relationship is not symmetric about VG = 0. A given magnitude of gate bias will

59

result in a greater amount of band bending for one polarity versus another and could

explain why at -1 and -2 VDC, the capacitance change is greater than at +1 and +2 VDC.

100

110

120

130

140

150

160

0 10 20 30 40 50 60

Cap

acita

nce

(pF

)

time (s)

Au-Ti-HfO2-InAs

HCl pretreatment200 °C growth temperature

75 ALD cycles400 °C, 2 min., N

2 PMA

TTC, OS, PC10 kHz, 25 mV osc.

BW 4, pt. avg. 40 s sweep delay

VG = +2 VDC

+1

-2

0

-1

85 × 85 µm2

Figure 2.37 Measured capacitance versus time for a Au-Ti-HfO2-InAs MOS capacitor formed using 75 ALD cycles and a 200 °C growth temperature with the DC bias fixed at +2 (red), +1 (orange), 0 (lime), -1 (green), and -2 (blue) V. The measurement frequency is 10 kHz and signal amplitude is 25 mV rms.

Figure 2.38 is the 10 kHz measured C-V curve for the device using sweep delays

of 0, 0.02, 0.2, 2, 20, and 60 s. The DC bias is swept from +2 to -2 V. To test for the

existence of a hysteresis effect, two measurements are performed using each sweep delay

in a random order. From the plot, it can be seen that the capacitance is dependent upon

the sweep delay and not the order in which the sweeps are taken. Consistent with the

capacitance-time data, the measured capacitance at +2 VDC decreases with time. The

measured capacitance using 0 and 60 s sweep delays differs by 6% at +2 V. After the

sweep delay, the DC bias is swept toward -2 V at a rate of ~1 V/s. In general, curves

acquired with the different sweep rates converge as the sweep progresses. By the time the

60

sweep reaches -2 V (about 4 s after the sweep start), the 0- and 60-s values differ by only

1%.

90

110

130

150

170

-2 -1 0 1 2

Cap

acita

nce

(pF

)

Gate Voltage (V)

0 s delay20 ms

200 ms2 s

20 s60 s

~1 V/s sweep

sweeps done twice each inrandom order

Au-Ti-HfO2-InAs

HCl pretreatment200 °C growth temperature

75 ALD cycles400 °C, 2 min., N

2 PMA

TTC, OS, PC10 kHz, 25 mV osc.

85 × 85 µm2

Figure 2.38 Measured C-V curves for a Au-Ti-HfO2-InAs MOS capacitor formed using 50 ALD cycles and a 200 °C growth temperature with the DC bias swept from +2 to -2 V using sweep delays of 0, 0.02, 0.2, 2, 20, and 60 s. Two measurements using each sweep delay are performed in a random order. The measurement frequency is 10 kHz and signal amplitude is 25 mV rms.

In Ti-GdGaO-GaAs MOS heterostructures, dependence of the measured 1 MHz

C-V characteristic on DC bias sweep rate is observed by Passlack [76]. In accumulation,

the slope and magnitude of the capacitance decreases with decreasing DC sweep rate.

Passlack uses sweep rates as low as 9.2 × 10-4 V/s to measure C-V characteristics of Ti-

GdGaO-GaAs MOS devices, and makes no claim that even this achieves an equilibrium

measurement.

Figure 2.39 contains 10 kHz (a) and 1 MHz (b) TTC C-V curves measured on Au-

Ti-HfO2-InAs capacitors grown using 75 ALD cycles and a 300 °C growth temperature

with DC bias sweep rates of 0.75, 0.1, and 0.01 V/s and 1.2 V/hour (3.3 × 10-4 V/s). The

61

DC bias is swept from +2 to -2 V and back (except for the 1.2 V/hour sweep which was

swept in only one direction). The different sweep rates are achieved by adjusting the

“point delay,” which is the amount of time that the PIA dwells at a particular value of DC

bias before continuing to the next measurement point. Point delays ranging from 10 ms to

30 s are used to achieve the sweep rates. The sweep rate is calculated by timing the

measurement with a stopwatch.

In contrast to the results of Passlack [76], only a slight increase in slope in the C-

V curve is observed when the sweep rate is increased. At +1.5 V, the difference between

measured capacitance using 0.75 V/s and 1.2 V/hour is only 6% at 10 kHz and only 4%

at 1 MHz. Using similar bias (+1 – +4 V), roughly a factor of two difference in

capacitance is observed using sweep rates of 0.92 V/s and 9.2 × 10-4 V/s in [76]. While

the slope of the characteristic is only slightly influenced by sweep rate, a shift of the

entire curve towards lower capacitance is observed for the 1.2 V/hour sweep rate at both

10 kHz and 1 MHz. The shift could be related to the capacitance decay observed in

Figure 2.37.

The bidirectional sweep hysteresis measured at 10 kHz is 0.34, 0.28, and 0.28 V

using 0.75, 0.1, and 0.01 V/s sweep rates, respectively, a change of 20% between 0.75

and 0.1 V/s rates. A similar, 20% change is observed using 1 MHz. Higher hysteresis is

expected at higher sweep rates, as traps that contribute to the voltage shift have less time

to unload charge.

62

0

50

100

150

200

-2 -1 0 1 2

Cap

acita

nce

(pF

)

Gate Voltage (V)

0.75 V/s (10 ms point delay)0.1 V/s (100 ms)

0.01 V/s (1 s)1.2 V/hr (30 s)

Au-Ti-HfO2-InAs

HCl pretreatment300 °C growth temperature

75 ALD cycles

TTC, OS, PC25 mV osc.

BW 1, pt. avg. off10 s sweep delay

85 × 85 µm2

10 kHz

(a)

0

50

100

150

200

-2 -1 0 1 2Voltage (V)

0.75 V/s (10 ms point delay)0.1 V/s (100 ms)

0.01 V/s (1 s)1.2 V/hr (30 s)

Au-Ti-HfO2-InAs

HCl pretreatment300 °C growth temperature

75 ALD cycles

TTC, OS, PC25 mV osc.

BW 1, pt. avg. off10 s sweep delay

85 × 85 µm2

1 MHz

Cap

acita

nce

(pF

)

(b)

Figure 2.39 Measured C-V curves for a Au-Ti-HfO2-InAs MOS capacitor formed using 75 ALD cycles and a 200 °C growth temperature. The DC bias is swept from +2 to -2 V using a sweep delay of 10 s and sweep rates of 0.75, 0.1, and 0.01 V/s and 1.2 V/hour (3.3 × 10-4 V/s). The measurement is taken at 10 kHz (a) and 1 MHz (b).

Along with examining the effect of specific equipment settings, tests of

repeatability are performed to ensure that measurements taken at different times can be

considered together when interpreting results. The C-V characteristic in Figure 2.40 is

63

representative of the device wafers and measurement settings used in this work. The

measurement is taken with a 25 mV rms signal at 1 MHz, using TTC connection with OS

and PC calibration. The DC bias is swept from accumulation to inversion at ~0.5 V/s

with no sweep delay. Four different devices are measured on the same wafer. The

uniformity exhibited by devices on this wafer (within 6% at +2 VDC), is typical of

wafers used in this work. The measurements are taken over the course of five hours,

which represents an average amount of time for a single measurement session.

70

80

90

100

110

120

130

140

-3 -2 -1 0 1 2 3

Cap

acita

nce

(pF

)

Gate Voltage (V)

first measurements (time zero)last measurement (~five hours later)

Au-Ti-HfO2-InAs

HCl pretreatment200 °C growth temperature

75 ALD cycles

TTC, OS, PC1 MHz, 25 mV osc.

BW 4, pt. avg. 40 s sweep delay

85 × 85 µm2

measurements from differentdevices on the same wafer

Figure 2.40 Measured 1 MHz TTC C-V characteristic of four different Au-Ti-HfO2-InAs MOS capacitors grown using 75 ALD cycles and a temperature of 200 °C on the same wafer. The measurements are taken over the course of ~5 hours.

Measurements of different devices on the same wafer taken four weeks apart are

shown in Figure 2.41. The measurement uses the same, typical settings shown in the

previous figure. The devices on the wafer are grown using 75 ALD cycles and a growth

temperature of 300 °C. Despite the time lapse, during which the probe station and PIA

are reconfigured and used by several different people, and the fact that different devices

64

are measured, the resulting capacitance differs by only 4% at +2 V and 10% at -2 V. The

voltage at which the minimum capacitance occurs differs by 0.2 V. This time lapse

represents an extreme in this work, as all results that are directly compared to each other

are taken during the same measurement session.

0

50

100

150

200

-2 -1 0 1 2Gate Voltage (V)

Au-Ti-HfO2-InAs

HCl pretreatment300 °C growth temperature

75 ALD cycles

TTC, OS, PC25 mV osc.~ 0.5 V/s

85 × 85 µm2

1 MHz

Cap

acita

nce

(pF

)measurement of two different devices on

same wafer taken four weeks apart

Figure 2.41 Measured 1 MHz TTC C-V characteristic of two different Au-Ti-HfO2-InAs MOS capacitors grown using 75 ALD cycles and a temperature of 300 °C on the same wafer. The measurements are taken four weeks apart.

In summary, the response of InAs MOS capacitors to time and slew rate settings

have been shown. Measurement uniformity, repeatability, and stability are also

documented. Capacitance is shown to decrease ~6% by using a 60 s sweep delay. A

similar decrease is observed when slowing the DC bias sweep rate from 0.75 V/s to 1.2

V/hour. In contrast to Ti-GdGaO-GaAs MOS devices [76], the slope of the C-V curve for

Au-Ti-HfO2-InAs devices is shown to change only slightly when the sweep rate is

changed. Measurements of different devices on the same wafer taken over the course of a

typical measurement session agree to within 6%.

65

2.5 Correction of measured impedance characteristics for series resistance

In the PIA, the complex impedance can be displayed using a number of equivalent

representations. A common representation is equivalent parallel capacitance-conductance

(CP-G). The equivalent circuit used to compute CP-G is shown in Figure 2.42(a). From

the circuit, the magnitude, |Z|, and phase, ?, of the impedance is given by

( )22

1

PCGZ

ω+= and (2.26)

−

=GCPω

θ arctan , (2.27)

where ? is the angular frequency of the measurement signal, given by 2pf. Solving (2.26)

and (2.27) for CP and G results in the equations used to convert a measured complex

impedance into an equivalent parallel capacitance and conductance for a given frequency,

1tan

11

2+

=

θω Z

CP and (2.28)

1tan

12 +

=θZ

G . (2.29)

When the connection to the DUT has a significant series resistance (relative to the

DUT impedance), the two-element circuit of Figure 2.42(a) fails to represent the

measured impedance. When (2.28) and (2.29), which are based on the two-element

circuit, are used to compute an equivalent parallel capacitance-conductance, the series

resistance causes a discrepancy between the measured CP-G and the actual DUT CP-G.

Figure 2.42(b) is a three-element circuit that includes a series resistance with the parallel

capacitance-conductance of the DUT. Including series resistance, the impedance relations

now become

66

( ) ( )

2

22

2

22

++

++=

P

P

PS

CGC

CGG

RZω

ωω

and (2.30)

[ ]

++

−=

GCGRC

PS

P22 )(

arctanωω

θ . (2.31)

In the case of RS = 0, (2.30) and (2.31) become (2.26) and (2.27), respectively.

CP 1/GCP 1/G

CP 1/G

RS

CP 1/G

RS

(a) (b)

Figure 2.42 Two- (a) and three- (b) element circuit models used to interpret impedance measurements.

The series resistance for a TTC connection is measured using Au-Pd-InAs devices

and shown in Figure 2.43; the resistance shows some curvature with a resistance of

approximately 75 O. This resistance is similar in magnitude and curvature to the series

resistance of Au-Pd contacts to InAs in the TTT measurement shown in Figure 2.27.

Despite the 5.9× difference in device area, the currents flowing through (and the

associated resistances) differ by only 10%. For the devices studied in this work, the series

resistance is independent of device area.

67

-0.015

-0.01

-0.005

0

0.005

0.01

0.015

-1 0 1

Cur

rent

(A)

Gate Voltage (V)

Au-Pd-InAsHCl pretreatment

no HfO2 film

200 °C, 1 hour, N2 PMA

35 × 35 µm2 contact85 × 85

RS = 84 Ω

93 Ω

Figure 2.43 Current-voltage measurement of 35 × 35 (red) and 85 × 85 (blue) µm2 Au-Pd contacts on InAs. The InAs is pretreated with a 30 s dip in HCl:H2O (1:1) prior to metal evaporation. Following evaporation, the contacts are annealed at 200 °C for 1 hour in an N2 ambient.

Figure 2.44 predicts how a 100-O series resistance changes the complex-

impedance-frequency curve of an ideal, parallel CP-G circuit. The capacitance used in the

circuit is the ideal oxide capacitance of an 85 × 85 µm2 device assuming an oxide

thickness of 2.5 nm and a dielectric constant of 25e0 (639 pF). The conductance used is

assumed to be constant and chosen to be the expected tunneling conductance of a 2.5 nm

metal-HfO2-InAs MOS structure, Figure 2.17, at 1 V gate bias (2 × 10-3 S). From Figure

2.44, the series resistance increases the total impedance of the circuit. At high frequency,

as the impedance of the capacitor drops, the series resistor contributes more to the total

circuit impedance, causing the overall character of the circuit to be more resistive and

leading to an increase in the phase of the impedance towards 0°.

68

101

102

103

-180

-90

0

90

180

103 104 105 106 107

|Z| (

Ω) θ (°)

f (Hz)

ideal impedance of a parallelcapacitance-conductancecircuit with and without a100 Ω series resistance

RS = 0 Ω 100 Ω

RS

639 pF 2E-3 S

Figure 2.44 Ideal complex- impedance-frequency curve for a parallel capacitance-conductance circuit with (blue) and without (red) a 100 O series resistance.

Figure 2.45 is the equivalent-capacitance-conductance-frequency curve computed

using the circuit of Figure 2.44 with and without the series resistance. In the ideal case

(with no series resistance), the measured capacitance and conductance is constant in

frequency and equal to the ideal values. However, with series resistance, the equivalent

capacitance differs by 31% from the ideal value at low frequency; this difference

increases towards higher frequencies and reaches 38% at 1 MHz. The measured

conductance is underestimated by 16% at low frequency and overestimated by 25% at 1

MHz when series resistance is included. Series resistance can introduce significant errors

in the analysis of MOS devices.

69

3 10-10

4 10-10

5 10-10

6 10-10

10-3

10-2

103 104 105 106 107

CP (F

) G (S

)

f (Hz)

RS = 0 Ω

100 Ω

RS

639 pF 2E-3 S

Figure 2.45 Theoretical measured capacitance- and conductance-frequency curves for an ideal parallel capacitance-conductance circuit with (blue) and without (red) a 100 O series resistance.

If the series resistance is known, the measured capacitance, CM, and conductance,

GM, may be corrected using relations derived from (2.28) – (2.31),

22 )()1( SMSM

MC RCRG

CC

ω+−= and (2.32)

1

2

−−

=SM

MSCMC RG

GRCCG

ω, (2.33)

where CC and GC are the corrected capacitance and conductance, respectively. Figure

2.46 explores the correction dependence of C-V characteristics for Au-Ti-HfO2-InAs

MOS capacitors assuming a series resistance ranging from 0 to 100 O.

70

6 10-11

1 10-10

1.4 10-10

1.8 10-10

-1 10-4

-5 10-5

0

5 10-5

1 10-4

-3 -2 -1 0 1 2 3

CC (

F) G

C (S)

Gate Voltage (V)

RS = 0 Ω

10 Ω

50 Ω

100 Ω

Au-Ti-HfO2-InAs

HCl pretreatment300 °C growth temperature

75 ALD cycles

1 MHz

(a)

6.5 10-11

7.5 10-11

8.5 10-11

9.5 10-11

2 10-4

4 10-4

6 10-4

8 10-4

-1.5 -1 -0.5 0 0.5 1 1.5

CC (

F) G

C (S)

Gate Voltage (V)

RS = 0 Ω

10 Ω50 Ω

100 Ω

Au-Ti-HfO2-InAs

HCl pretreatment300 °C growth temperature

50 ALD cycles

1 MHz

(b)

Figure 2.46 Capacitance- and conductance-voltage curves for Au-Ti-HfO2-InAs MOS capacitors grown using 75 (a) and 50 (b) ALD cycles and an HfO2 growth temperature of 300 °C. The measurement is taken TTC using a 1 MHz signal. The measured curves are shown with series resistance corrections of 0 (red), 10 (blue), 50 (green), and 100 (orange) O.

Depending on the device impedance, the series resistance correction has a greater

impact on either the capacitance or the conductance. For the thicker, 75-cycle film, the

71

conductance is about an order of magnitude lower than the 50-cycle film; the series

resistance results in a substantial correction to the conductance while the capacitance is

unchanged. In the 50-cycle film, the series resistance changes the capacitance while the

conductance is only slightly changed. For the thicker films used in this work (= 75 ALD

cycles), series resistance is most important when considering the device conductance. For

the thinner films (< 75 ALD cycles), series resistance is most important when considering

the device capacitance.

While series resistance in the experimental geometry used here is independent of

device contact size, the capacitance (and the associated impedance) is strongly area-

dependent. Large-area devices, which have larger capacitance and lower impedance than

smaller devices, are more sensitive to series resistance. The complex impedance is

measured as a function of frequency to determine the influence of series resistance in

small- (35 × 35 µm2) and large- (85 × 85 µm2) area devices fabricated on the same wafer.

Figure 2.47 contains the Z-f curves for small (a) and large (b) devices grown using a

growth temperature of 300 °C and 50 ALD cycles at DC biases ranging from -1 to +1 V.

The influence of series resistance can most clearly be seen in the phase of the

large contact impedance. Around 200 kHz, the capacitor impedance starts to decrease; the

series resistance begins to contribute more to the impedance and the phase increases

towards 0°. The symbols in Figure 2.47(b) are a three-element model fit to the 0 VDC

data; the fit uses CP = 190 pF, G = 1.1 × 10-5 S, and RS = 150 O. The small-contact device

shows no significant increase in phase with frequency; even at 1 MHz, the capacitance

dominates the impedance.

72

101

102

103

104

105

106

107

-80

-40

0

40

80

103 104 105 106 107

|Z| (

Ω) θ (°)

-1 to +1 V

0±0.5

-1+1

35 × 35 µm2 - no backside contact

Au-Ti-HfO2-InAs

HCl pretreatment300 °C growth temperature

50 ALD cycles

f (Hz)

TTC, OS, PC25 mV osc.

(a)

100

101

102

103

104

105

-80

-40

0

40

80

103 104 105 106 107

|Z| (

Ω) θ (°)

0 V-0.5

-1/+0.5+1

0 V -0.5-1

+0.5

+1

f (Hz)

85 × 85 µm2

no backside contact

symbols - model fitC

P = 190 pF, G = 1.1E-5 S, R

S = 150 Ω

(b)

Figure 2.47 Measured complex-impedance-frequency curves for Au-Ti-HfO2-InAs MOS capacitors with 35 × 35 (a) and 85 × 85 (b) µm2 metal contacts grown on the same wafer using 50 ALD cycles and a growth temperature of 300 °C and with no backside contact. The frequency sweeps are performed at -1 (blue), -0.5 (lime), 0 (red), +0.5 (orange), and +1 (green) VDC. The symbols are a theoretical complex- impedance-frequency curve using a three-element model with CP = 190 pF, G = 1.1 × 10-5 S, and RS = 150 O.

73

Although the effect of series resistance in the large devices may be removed

mathematically, a more robust alternative is to remove the series resistance physically.

This is achieved with a backside contact. Backside contacts are placed on the device

wafers after formation of the MOS capacitor arrays. The frontside is protected with

photoresist while the backside is exposed to a 30 s dip in HCl:H2O (1:1) which etches the

InAs and cleans the backside surface. Following the etch, 5 nm of Ti is evaporated on the

backside followed by 150 nm of Au. Finally, the frontside PR is removed in acetone.

Figure 2.48 contains the Z-f curves for the devices of Figure 2.47 after backside contact

deposition. It is clear in both small- and large-area device curves that the series resistance

does not play a role in the measured impedance over the frequency range measured when

backside contacts are present.

The effect of reducing the series resistance with a backside contact is also seen in

Figure 2.49, which contains C-V curves taken on small- (open symbols) and large- (solid

symbols) area devices on the same wafer before (blue) and after (red) backside contact

deposition. The capacitance plotted is the measured equivalent parallel capacitance (with

no series resistance correction) normalized by the device area (specific capacitance).

Before the backside contact is placed on the device wafer, there is a 2.7× difference in the

specific capacitance of the small- and large-area devices. After backside contact

formation, the specific capacitance differs by only 1.1×.

74

101

102

103

104

105

106

107

-80

-40

0

40

80

103 104 105 106 107

|Z| (

Ω) θ (°)

f (Hz)

-1 to +1 V

0,±0.5-1+1

35 × 35 µm2 - Ti-Au backside contact

Au-Ti-HfO2-InAs

HCl pretreatment300 °C growth temperature

50 ALD cycles

TTC, OS, PC25 mV osc.

(a)

100

101

102

103

104

105

106

-80

-40

0

40

80

103 104 105 106 107

|Z| (

Ω) θ (°)

f (Hz)

0 V

+0.5-0.5

+1

0 V ±0.5 +1

85 × 85 µm2

Ti-Au backside contact

(b)

Figure 2.48 Measured complex-impedance-frequency curves for Au-Ti-HfO2-InAs MOS capacitors with 35 × 35 (a) and 85 × 85 (b) µm2 metal contacts grown on the same wafer using 50 ALD cycles and a growth temperature of 300 °C and with a Ti-Au backside contact. The frequency sweeps are performed at -1 (blue), -0.5 (lime), 0 (red), +0.5 (orange), and +1 (green) VDC.

75

0

1

2

3

4

5

-1 0 1

Cap

acita

nce

(µF/

cm2)

Gate Voltage (V)

open - 35 × 35 µm2

CP-G model

1 MHz

no backside contactTi-Au backside contact

HCl pretreatment300 °C growth temperature

50 ALD cycles

TTC, OS, PC25 mV osc.

2.7×

1.1×

Au-Ti-HfO2-InAs

solid - 85 × 85 µm2

Figure 2.49 Measured capacitance (per unit area) vs. voltage for Au-Ti-HfO2-InAs MOS capacitors grown using 50 ALD cycles and a growth temperature of 300 °C with 35 × 35 (open symbols) and 85 × 85 (solid symbols) µm2 metal contacts with (red) and without (blue) Ti-Au backside contacts. The measurement is performed at 1 MHz.

The influence of series resistance on measured impedance is modeled and shown

to have a significant impact on the equivalent parallel capacitance and conductance. The

series resistance associated with TTC measurements on devices used in this work is

independent of device area and has a greater impact on large-area devices than small-area

devices. The measured capacitance and conductance may be corrected mathematically.

Depending on the specific values of measured capacitance and conductance, the

correction due to series resistance has a greater influence on either capacitance or

conductance. For devices in this work grown using 75 or more ALD cycles, series

resistance influences the conductance more, while the capacitance is influenced more in

devices with thinner oxides. Backside contacts are placed on device wafers to reduce

series resistance. The reduction in series resistance due to backside contacts is confirmed

with impedance-frequency measurements.

76

2.6 Measurement of MOS capacitor leakage current

Current-voltage characteristics are measured with an Agilent 4155B

semiconductor parameter analyzer (SPA) using the same probe station used for

impedance characterization. The SPA has four high-resolution source/monitor units

(SMUs), each of which can be operated in one of three modes: voltage source/current

monitor, current source/voltage monitor, or source common. The SMUs have voltage and

current source/monitor ranges of ±100 V and ±100 mA, respectively, with a maximum

output power of 2 W. The minimum current measurement range is 10 pA with 1 fA

resolution.

In this work, device leakage is measured TTC, with one SPA SMU operated in

source common mode and connected via triaxial cable to the wafer chuck bias port and

another operated in voltage source/current monitor mode and connected to a tungsten

probe with a tip diameter of 2.4 µm. Current-voltage characteristics are obtained by

sweeping the applied voltage over a given range in a stepwise fashion. Both the voltage

range and step size are explicitly set in the SPA settings. At each step, several

measurement samples are taken and averaged together. The amount of time spent

sampling at each step is determined by the measurement range and the integration setting.

The integration setting may be set to short, medium, or long integration times.

The minimum measurable leakage current is set by the background noise of the

system. This is measured by performing an open-circuit (probe not in contact with

anything) I-V sweep, an example of which is shown in Figure 2.50. In the figure, the

open-circuit current has a range of about ±200 fA. The open-circuit current varies from

77

day to day and is checked before each measurement session to ensure that it does not

approach expected DUT currents.

-4 10-13

-2 10-13

0

2 10-13

4 10-13

-6 -4 -2 0 2 4 6

Cur

rent

(A)

Voltage (V)

measurement of current with probe up

TTC, W probeAgilent 4155B SPAmedium integration

-5 to +5 V sweep, 50 mV step

Figure 2.50 Open-circuit TTC current-voltage measurement using W probe.

A short-circuit I-V characteristic is measured by placing the probe in direct

contact with the wafer chuck. The resulting I-V curve, an example of which is shown in

Figure 2.51, gives a measure of the resistance due to the measurement equipment,

including probe, cabling, and wafer chuck resistances. Ohmic behavior is seen in the

figure and the resistance calculated from the slope of the I-V is 3 O. A short-circuit

measurement is taken before each measurement session to confirm that the equipment is

connected properly and is not contributing a significant resistance to the measurement.

78

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

-0.4 -0.2 0 0.2 0.4

Cur

rent

(A)

Voltage (V)

measurement of current with probein contact with wafer chuck

TTC, W probeAgilent 4155B SPAmedium integration

-5 to +5 V sweep, 50 mV step

compliance limit

R = 3.0 Ω

Figure 2.51 Short-circuit TTC current-voltage measurement using W probe.

For the current-voltage characterization of capacitors, the voltage sweep rate and

starting voltage are important measurement parameters that significantly influence the

resulting characteristics. If the DUT is modeled using a parallel capacitance, C, and

resistance, R, as in Figure 2.42(a), then the current, I, flowing through the device is given

by

RV

dtdV

CI += , (2.34)

where V is the voltage applied to the DUT and dV/dt is the voltage sweep rate. Analysis

of (2.34) reveals that a double voltage sweep, that is, a sweep that traverses a given bias

range in both directions, when applied to a capacitor, results in a “loop” I-V

characteristic, known as a hysteresis loop. From a hysteresis loop, both the equivalent

parallel capacitance and resistance (or conductance) are calculated if the sweep rate is

known. Also implied by this analysis is the fact that current flows through the DUT at

zero bias if the voltage sweeps through (as opposed to starts from) zero.

79

Figure 2.52 shows the hysteresis loop of a Au-Ti-HfO2-InAs MOS capacitor

grown using 150 ALD cycles and a growth temperature of 250° C. The sweep is taken

from +3 to -3 and then back to +3 V using the medium integration setting, which at this

measurement range and step size, corresponds to a sweep rate of 0.18 V/s. From the slope

of the top and bottom sides of the hysteresis loop, the parallel conductance of the DUT is

2 × 10-13 S. From the average of the zero-bias current and the sweep rate, the parallel

capacitance is 6 pF. The expected geometric capacitance of the device is ~20 pF. It

should be noted, however, that since both the capacitance and conductance of this MOS

device are bias-dependent, analysis based on (2.34) should be used for only rough, order-

of-magnitude estimation.

-4 10-12

-2 10-12

0

2 10-12

4 10-12

-3 -2 -1 0 1 2 3

Cur

rent

(A

)

Gate Voltage (V)

G = 2 × 10-13 S

C = 6 pF

TTC, W probeAgilent 4155B SPA

medium integration (0.18 V/s)double sweep, 30 mV step

35 × 35 µm2Au-Ti-HfO2-InAs

BHF pretreatment250 °C growth temperature

150 ALD cycles

+3 to -3 Vand back

Figure 2.52 Current-voltage characteristic of Au-Ti-HfO2-InAs MOS capacitor grown using 150 ALD cycles and a 250 °C growth temperature. The sweep is taken from +3 to -3 V and back using medium integration, which results in a 0.18 V/s sweep rate.

From (2.34), the measured current through a capacitor is comprised of

displacement and conduction current components. Of interest in MOS device

80

characterization is the conduction current, because it is the conduction current that is

responsible for the off-state, static power dissipation in a MOSFET. Double voltage

sweeps originating from zero bias are used to ensure that the contribution of displacement

current to the overall measured current is minimal. By comparing I-V data taken

immediately before and after a sign change in dV/dt, as occurs when a voltage sweep

changes directions, the effect of the displacement current is observed. For the device and

sweep in Figure 2.52, this effect is clearly visible, as the current drops from ~2 pA at -3

V to ~-1 pA by -2 V. When the sweep originates at zero bias and is performed at a

sufficiently-slow rate, as in Figure 2.53, there is no such drop in current when the sweep

direction is changed.

-2 10-7

-1 10-7

0

1 10-7

2 10-7

10-13

10-11

10-9

10-7

-3 -2 -1 0 1 2 3

Cur

rent

(A)

Gate Voltage (V)

Au-Ti-HfO2-InAs

HCl pretreatment300 °C growth temperature

75 ALD cycles

TTC, W probeAgilent 4155B SPA

medium integration (0.15 V/s)double sweeps, 25 mV step

0 to ±3 V85 × 85 µm2

Figure 2.53 Current-voltage characteristic of Au-Ti-HfO2-InAs MOS capacitor grown using 75 ALD cycles and a 300 °C growth temperature plotted on a linear (blue) and logarithmic (red) scale. The sweep is taken from 0 to +3 V and back and from 0 to -3 V and back using medium integration, which results in a 0.15 V/s sweep rate.

In addition to measuring conduction, current-voltage sweeps are also used to

observe and measure destructive dielectric breakdown. Breakdown measurements in this

81

work are performed by ramping the gate voltage applied to a device from zero to a

voltage at which the breakdown field of the oxide is exceeded. When the breakdown field

is exceeded, the device behavior is irreversibly changed and exhibits much higher

conductance. Figure 2.54 contains the breakdown measurements of three different

devices on the same wafer grown using 75 ALD cycles and a 300 °C growth temperature

and one of the devices after the breakdown event. The sweeps are taken from 0 to +5 V.

In the figure, all three devices breakdown at ~3 V, after which the current increases by

several orders of magnitude. After a device experiences breakdown, it behaves like a

short, exhibiting much higher leakage current than before breakdown.

10-13

10-11

10-9

10-7

10-5

10-3

10-1

0 1 2 3 4Gate Voltage (V)

Cur

rent

(A)

TTC, W probeAgilent 4155B SPAmedium integration

single sweep, 50 mV step85 × 85 µm2

Au-Ti-HfO2-InAs

HCl pretreatment300 °C growth temperature

75 ALD cycles

0 to +5 V

compliance limit

3 different devicesbreakdown

1 device after breakdown

Figure 2.54 Current-voltage characteristics of three different Au-Ti-HfO2-InAs MOS devices grown using 75 ALD cycles and a 300 °C growth temperature showing breakdown event (red) and one device after breakdown event (blue). The sweeps are taken from 0 to +5 V.

The measurement equipment and setup for MOS current-voltage characterization

is described. The noise associated with the system is determined with an open-circuit

measurement to be in the range of ±200 fA. The short-circuit resistance due to the

82

tungsten probe, cabling, and wafer chuck is 3 O. The voltage sweep rate and starting

voltage have a significant effect on the measured current-voltage characteristic. A

hysteresis loop is observed when a capacitor is measured with a double voltage sweep

that originates at a non-zero bias and conductive current is observed when the sweep

originates at zero. Breakdown measurements are performed by ramping gate voltage from

zero to a voltage at which oxide breakdown field is exceeded.

2.7 Comparison of measured characteristics to prior art

Device measurements from this work are compared to similar prior art for

benchmarking and as an overall check of the measurement process. At the time of this

writing, Web of Science [77] and Engineering Village [78] searches using the terms “inas

hfo2” and “indium arsenide hafnium dioxide” returned only one experimental report of

HfO2-InAs-based MOS devices that does not involve collaborators in this work. The

report appears in Applied Physics Letters and contains C-V characteristics of HfO 2-based

MOS capacitors on n- and p-type GaAs, In0.53Ga0.47As, InAs, and InSb with and without

a Ge passivation layer [59].

Figure 2.55 contains 10 kHz, 100 kHz, and 1 MHz C-V curves of metal-HfO2-

n-InAs MOS capacitors from Kim et al. [59] and from this work. The HfO2 films from

Kim et al. are ~10 nm thick and are deposited by DC sputtering in an Ar background

using the modulation technique. The InAs substrate is doped either 2 × 1016 or 3 × 1017

cm-3 n-type and pretreated with HF and (NH4)2S prior to HfO2 film growth. Following

growth, the film is annealed at 360 °C for 60 s. A TaN layer is deposited by DC

sputtering for metal gate contacts and AuGe-Ni-Au is used for a backside contact.

83

Following metal deposition, wafers are annealed at 360 °C for 30 s. The device from this

work is from wafer 2n, a Au-Ti-HfO2-n-InAs structure with an HfO 2 layer grown using a

temperature of 200 °C and 75 ALD cycles. The wafer is pretreated with HCl. Despite the

differences in the processing conditions between the two devices, similar features in the

C-V behavior are observed, namely inversion and accumulation capacitance frequency

dispersion and stretch-out along the voltage axis.

0

0.5

1

1.5

2

-2 -1 0 1 2

Cap

acita

nce

(µF/

cm2 )

Gate Voltage (V)

This work:Au-Ti-HfO

2-n-InAs

HCl pretreatment200 °C growth temperature75 ALD cycles (~5.7 nm)

no PMA

Kim et al.

this work

10 kHz, 100 kHz, 1 MHz

10 kHz, 100 kHz, 1 MHzKim et al.:

TaN-HfO2-n-InAs

HF + (NH4)

2S pretreatment

~10 nm HfO2 by DC sputtering

360 °C, 60 s post-deposition anneal360 °C, 30 s PMA

Figure 2.55 Capacitance-voltage curves from this work (blue) and [59] (red) measured at 10 kHz, 100 kHz, and 1 MHz. Devices from this work are Au-Ti-HfO2-InAs structures grown using 75 ALD cycles and a 200 °C growth temperature.

84

CHAPTER 3:

HFO2-INAS MOS CAPACITORS

Two matrices (26 wafers) of metal-HfO2-InAs MOS heterostructures were formed

with experimental variations in oxide growth temperature, semiconductor wet chemical

pretreatment, oxide thickness, gate contact metal, and post-metallization anneal. The

devices were characterized using C-V, J-V, XPS, ellipsometry, and TEM.

3.1 Fabrication procedure and sample matrices

High-k-InAs MOS wafers were fabricated in Professor Lars-Erik Wernersson’s

research group (Division of Solid State Physics, Department of Physics, Lund

University). The collaboration started as the result of a two-month stay at Lund by the

author in the fall of 2006. Metal-high-k-InAs MOS heterostructures with oxide films

grown by ALD on bulk InAs substrates were taken back to Notre Dame for

characterization. Two additional matrices of device wafers followed to further explore

substrate growth temperature, pre-deposition chemical treatment, film thickness, gate

metal, post-metallization anneal treatment, and high-k materials. At Lund, additional

structures were prepared and characterization by ellipsometry and XPS.

Capacitors were fabricated on bulk InAs substrates with an n-type doping of

~2 × 1016 cm-3. Prior to film growth, the substrates were cleaved into pieces

approximately 1 cm2 in area; these pieces are herein referred to as “wafers.” Each wafer

85

was exposed to one of three wet chemical treatments. Following pretreatment, the wafers

were loaded into a Savannah 100 ALD system from Cambridge Nanotech (Cambridge,

MA). After oxide deposition, metal contacts were evaporated on the films through a

stencil mask. For the first set of wafers, Table 3.1, two wafers were fabricated for each of

the film deposition conditions used; one of them received a PMA while the other did not.

For the second set of wafers, two wafers for each condition were also made; each using

different contact metals. Four variables were explored: substrate pretreatment, oxide

growth temperature, oxide film thickness, and PMA. Three wet chemical treatments were

explored: buffered oxide etch containing 5% hydrofluoric acid (BHF) for 1 minute,

ammonium sulfide [(NH4)2S] diluted 10:1 with deionized water (DI) at 40 °C for 2

minutes, and 37% hydrochloric acid (HCl) in DI for 1 minute. After pretreatment,

samples were rinsed in DI for 20 s and immediately loaded into the ALD chamber.

Tetrakis(dimethylamido)hafnium(IV) [TDMA-Hf, Hf(NMe2)4] was used as the hafnium

precursor while water vapor was used as the oxygen precursor. The amide precursors

have an advantage over other ALD metal precursors in that they are liquid under typical

ALD pressure and temperature conditions and as a result, vaporize more reproducibly

than solid precursors and do not leave particulates on the substrate [79].

86

TABLE 3.1

MATRIX OF METAL-HFO2-INAS OXIDE PREPARATION DEPENDENCES IN THE

FIRST WAFER SET

Pretreatment Growth temperature (°C) Growth cycles

Wafer (NH4)2S HCl BHF 100 200 300 50 75 125

1 × × × 2 × × × 3 × × × 4 × × × 5 × × × 6 × × × 7 × × ×

Two wafers for each deposition were prepared; one receiving a 400 °C, 2 minute PMA in N2, the other receiving no PMA.. Annealed wafers are labeled “a” (e.g. “wafer 1a”) and wafers without anneal are labeled “n” for “not-annealed” (e.g. “wafer 1n”).

87

Film depositions are performed with 20 sccm of N2 flowing in the background at

a chamber pressure of 300 mTorr. One ALD cycle consists of a 100 ms step in which the

hafnium source valve is open, introducing the precursor into the growth chamber,

followed by a purge delay, Table 3.2, in which excess precursor is removed, which is

then followed by a 20 ms step in which the water vapor source valve is open, followed by

another purge. The times used for the purge step depend on the precursor and the

deposition temperature and are listed in Table 3.2. The hafnium precursor source is

heated to 75 °C, a temperature at which the vapor pressure is ~1 Torr [79]. The room-

temperature vapor pressure of water is ~24 Torr [79], thus, the water source does not

need to be heated. Metal contacts are formed on the wafers by electron-beam evaporation

of 5 nm of Ti followed by 400 nm of Au. Wafers in the first set have only one contact

size, 85 × 85 µm2. Two wafers are fabricated for each deposition with the annealed “a”

wafers receiving a 400 °C, 2 minute PMA in N2 ambient using a rapid thermal processing

(RTP) system and the other wafers are not annealed, “n”.

88

TABLE 3.2

PURGE TIMES USED IN HFO2 ALD PROCESS FOR DIFFERENT DEPOSITION

PRECURSORS AND TEMPERATURES

Growth temperature (°C) Purge time (s)

80 100 > 100

TDMA-Hf 80 80 5 Precursor

H2O 110 80 5

The second wafer matrix is summarized in Table 3.3. Designed in response to

results from the first wafer matrix, the second wafer matrix explores a greater range of

growth temperatures while reducing the number of ALD cycles and focusing on a single

pretreatment. Wafers are fabricated with both Ti-Au and Pd-Au contacts. Each wafer in

the second set has both 35 × 35 and 85 × 85 µm2 contacts. After an initial round of

current and impedance characterization, samples receive a 200 °C, 1 hour PMA in N2

using a probe station wafer chuck heater. Wafers from the second set are also referred to

as annealed “a” and not-annealed “n”.

89

TABLE 3.3

MATRIX OF METAL-HFO2-INAS OXIDE PREPARATION DEPENDENCES IN THE

SECOND WAFER SET

Growth temperature (°C) Growth cycles

Wafer 80 250 300 350 30 40 50

8 × × 9 × × 10 × × 11 × × 12 × × 13 × ×

Wafers are made with both Ti-Au (labeled “t”) and Pd-Au (labeled “p”) contacts. After initial measurements, all wafers are annealed for 1 hour at 200 °C in N2. Wafers are labeled “n.” before anneal and “a” after anneal.

Table 3.3 details the film deposition variation in the second growth matrix. All

samples are pretreated with HCl. However, in contrast to the first sample set in which

HCl is used straight from the bottle (37% concentration from the manufacturer), the HCl

is diluted 1:1 with deionized water (DI), resulting in an 18.5% solution. The treatment

time is also reduced from 60 to 10 seconds. These measures are taken to reduce the

roughening of the substrate, as HCl is known to be an aggressive InAs etchant [80]. Two

wafers for each deposition are fabricated to examine the influence of contact metals on

90

I-V and C-V characteristics; one received an evaporation of 50-220 nm of Pd-Au and the

other received 10-300 nm of Ti-Au.

A group of three additional HfO 2-InAs wafers (with no metal contacts) was

produced for HfO 2 film thickness measurement by ellipsometry. The wafers used the

same InAs substrates and receive the same BHF pretreatment as the samples in the first

set. The HfO2 films were grown using 40, 150, and 300 ALD cycles and a growth

temperature of 250 °C. The wafers are listed in Table 3.4 and are labeled with an “E”

prefix to denote their use for ellipsometry.

TABLE 3.4

MATRIX OF HFO2-INAS OXIDE PREPARATION DEPENDENCES IN THE

ELLIPSOMETRY WAFER SET

Wafer Growth cycles

E1 40

E2 150

E3 300

Wafers are pretreated with BHF and grown using a temperature of 250 °C.

Another group of nine wafers was prepared for evaluation by XPS. These wafers

used one of three pretreatments: the HCl or (NH4)2S pretreatments described earlier, or a

30 s dip in 10% HF. Growth temperatures range from 150 to 350 °C and the number of

ALD cycles ranges from 25 to 50. One wafer was characterized without HfO 2 deposition

91

and one sample was subsequently annealed with an RTP at 400 °C for 2 minutes in N2.

After film growth, the wafers were characterized by Anders Mikkelsen and Kees-Jan

Weststrate of the Division of Synchrotron Radiation Research within the Department of

Physics at Lund University using Beamline I311 at the MAX-II synchrotron ring [81].

The wafers for this characterization are listed in Table 3.5 and are labeled with an “X”

prefix to denote their use for XPS.

TABLE 3.5

MATRIX OF HFO2-INAS OXIDE PREPARATION DEPENDENCES IN THE XPS

WAFER SET

Pretreatment Growth Temperature (°C) Growth cycles Wafer

no HfO2

(NH4)2S HCl HF 150 250 350 25 38 50 PMA

X1 × × X2 × × × X3 × × × X4 × × × X5 × × × X6 × × × X7 × × × X8 × × × X9 × × × ×

Wafer X9 is annealed at 400 °C for 2 minutes in N2.

92

3.2 Frequency dependence of metal-HfO2-InAs MOS capacitor C-V characteristics

In Chapter 2, LF and HF C-V characteristics are modeled by including and

excluding minority carriers, respectively. Low frequency is defined as a frequency low

enough that the minority carrier generation can follow the applied AC signal. High

frequency is defined as a frequency so high that minority carriers cannot follow the

signal. In Si-based MOS devices at room temperature, low-frequency curves are observed

around 10 Hz and below while high-frequency curves are observed around 1 kHz and

above [82].

In practice, the transition between LF and HF curves is not abrupt and there is a

frequency range over which the inversion-regime capacitance is frequency-dependent. In

Si, this range is between approximately 10 Hz and 1 kHz. To model frequency-dependent

inversion-regime capacitance, time constants corresponding to minority carrier

generation and interface trap response are included, often in the form of a frequency- and

bias-dependent conductance [82].

The frequencies corresponding to LF and HF are measured experimentally by

performing C-V measurements over a range of frequencies. Figure 3.1 contains quasi-

static (QS), 1 kHz, and 1 MHz C-V curves for wafer 7a which is a Au-Ti-HfO2-InAs

MOS capacitor grown using 200 °C and 125 cycles and annealed. The QS curve is

obtained from measuring the displacement current through the capacitor, similar to the

measurement of capacitance described in Section 2.6. This measurement is automated by

the Agilent 4155C and produces an equilibrium (low-frequency) C-V curve.

93

0

0.4

0.8

1.2

1.6

-4 -2 0 2 4

Cap

acita

nce

(µF/

cm2 )

Gate Voltage (V)

Au-Ti-HfO2-InAs

wafer 7aHCl (37%) pretreatment

200 °C growth temperature125 ALD cycles

400 °C, 2 min., N2 PMA

85 × 85 µm2

quasi-static (QS)

1 kHz

1 MHz

Figure 3.1 Capacitance-voltage characteristics of annealed InAs-HfO2 MOS capacitor wafer 7a, grown at 200 °C with 125 ALD cycles measured quasi-statically (orange) and with 1 kHz (red) and 1 MHz (blue) AC signals.

In Si-based MOS capacitors even at 1 kHz, a HF characteristic is expected in the

C-V, where the inversion layer cannot respond to the applied AC field, as discussed for

Figure 2.13. In contrast, in the measurements of Figure 3.1 for HfO2-InAs, the

capacitance for the negative biases exhibits a frequency dependence even at 1 MHz.

Generally, the inversion regime capacitance decreases with increasing frequency, as

fewer minority carriers respond to the measurement signal, but the dependence is very

different between Si and InAs. The differences for negative biases are consistent with the

low thermal generation rates in Si, a consequence of low defect densities [82], and the

relatively higher thermal generation rates in narrow-bandgap InAs.

Not anticipated by the model discussed in Chapter 2 is the frequency dependence

seen in the accumulation regime of Figure 3.1. In the simple model, the majority carriers

that form the accumulation layer are able to respond to the measurement signal,

94

regardless of frequency. This is a reasonable assumption, given that majority carrier

response time near the oxide-Si interface is on the order of 10-6 s for Si doped 1016 cm-3

n-type. The response time in InAs is even shorter, given that it scales with resistivity. The

frequency dispersion seen in Figure 3.1 (and other III-V MOS devices) has traditionally

been explained by strong Fermi- level pinning [83]. More recently, a distributed pinning

spot model (DPS) has been proposed to describe both vertical- (capacitance shift) and

horizontal- (voltage shift) type frequency dispersion in a unified manner [75].

Another deviation from the simple model of accumulation capacitance occurs in

devices with ultrathin oxides or low-effective-mass semiconductors like InAs. In Figure

2.14, it is shown that the capacitance of a Ti-100-nm-HfO2-n-InAs device, even in strong

accumulation, saturates below the oxide capacitance level due to the low conduction-

band density-of-states (DOS). This adds further uncertainty in the determination of the

oxide capacitance, which is often assumed to be equal to the capacitance in strong

accumulation.

Several techniques exist to extract the oxide capacitance from the measured C-V

curve [84-88]. The QS and HF (taken at 1 MHz) curves of a device from wafer 7a are

plotted with their derivative with respect to gate voltage in Figure 3.2. The data is

smoothed with a plotting program to reduce noise in the calculated derivative. Using

wafer 7a as an example, the oxide capacitance can be calculated using two different

techniques.

95

0

2 10-11

4 10-11

6 10-11

8 10-11

1 10-10

1.2 10-10

0

5 10-12

1 10-11

1.5 10-11

2 10-11

2.5 10-11

3 10-11

0 1 2 3

CM

(F

)

dCM /dV

G (F/V

)

VG (V)

QS

1 MHz

Cacc

= 115 pF

99.6 pF

Au-Ti-HfO2-InAs

wafer 7aHCl (37%) pretreatment

200 °C growth temperature125 ALD cycles

400 °C, 2 min., N2 PMA

85 × 85 µm2

Figure 3.2 Quasi-static (red) and 1 MHz (blue) C-V curves and their derivatives with respect to gate voltage for wafer 7a, an annealed Au-Ti-HfO2-InAs MOS capacitor wafer grown at 200 °C with 125 ALD cycles.

Among the most commonly used oxide capacitance extraction method is the

technique developed by Maserjian [88]. By assuming negligible interface trap

capacitance in accumulation and roughly equal trap charge densities at flatband and

accumulation, a capacitance-voltage relationship is derived,

6/12/13/1

2

1211

G

M

MOXM dVdC

CaCC

+= , (3.1)

where CM is the HF measured capacitance, a is a constant related to the DOS, and VG is

the applied gate voltage.

A plot of (3.1), shown in Figure 3.3, allows the value of COX to be extracted from

a linear fit of the data. However, a close look at the curve (Figure 3.3 inset) shows that

the resulting extracted value for oxide capacitance is dependent on the number of data

points used for the fit. This is because the assumptions made by the Maserjian model

(such as low interface trap density) do not apply to a high-k-III-V system.

96

0

500

1000

1500

2000

6 109 8 109 1 1010 1.2 1010

y = -4821.5 + 5.8922e-7x R= 0.99198 y = -6959.3 + 8.0075e-7x R= 0.99694

CM

-1/2

*(dC

M/d

VG)1/

6 (F

-1/3

V-1

/6)

1/CM (1/F)

COX

=115 pF

1000

1100

1200

1300

1 1010 1.02 1010 1.04 1010

122 pF

wafer 7a1 MHz

Figure 3.3 Maserjian method plot to determine COX for HfO2-InAs MOS capacitor wafer 7a. The measured data is from a 1 MHz C-V characteristic. The red line is fit to the last 20 data points while the blue line is fit to the last 40 data points.

Recognizing this deficiency, Kar developed a more suitable COX measurement

technique for high-k-III-V systems [89]. Assuming only that the semiconductor and

interface trap capacitances are exponential functions of the surface potential, the

following relation results for low-frequency C-V curves,

( )MOXOXG

M

M

CCCdV

dCC

−=2/12/1

1 β, (3.2)

where CM is the measured QS capacitance, and ß is a constant in the exponential

capacitance-surface-potential relationship. A Kar method plot, shown in Figure 3.4,

reveals a COX measurement that is less dependent on the number of points used than the

Maserjian method.

97

0

0.1

0.2

0.3

0.4

0.5

0.6

8 10-11 1 10-10 1.2 10-10 1.4 10-10

y = 1.499 - 1.1533e+10x R= 0.99606 y = 1.4719 - 1.129e+10x R= 0.99761 (1

/CM*d

CM/d

VG)1/

2 (V

-1/2

)

CM

(F)

130 pF130 pFC

OX =

0.16

0.2

0.24

1.09 10 -10 1.12 10-10 1.15 10 -10wafer 7a

QS

Figure 3.4 Kar method plot to determine COX for HfO2-InAs MOS capacitor wafer 7a. The measured data is from a QS C-V characteristic. The red line is fit to the last 20 data points while and the blue line is fit to the last 40 data points.

To check that the dependence of the calculated oxide capacitance on the number

of data points used is a function of the method and not the data itself, the Maserjian

technique is applied to the QS data and the Kar technique is applied to the 1 MHz data.

Percentage error is calculated based on the difference in oxide capacitance values

calculated using 20 and 40 data points. The values calculated from the wafer 7a QS and 1

MHz data using the accumulation capacitance, Maserjian, and Kar methods are listed in

Table 3.6. The bold values are the calculations performed using the appropriate data (i.e.

1 MHz for the Maserjian method and QS for the Kar and accumulation capacitance

methods) for the measurement technique. From the table, it can be seen that the Kar

method, when applied to both QS and 1 MHz curves, produces the oxide capacitance

values least dependent on the portion of the curve fitted. Values of oxide capacitance

98

quoted in this work are based on Kar’s method using data from the lowest available

measurement frequency.

TABLE 3.6

OXIDE CAPACITANCE OF HFO2-INAS MOS CAPACITOR WAFER 7A AS

CALCULATED BY THE ACCUMULATION, MASERJIAN, AND KAR METHODS

COX (pF) QS 1 MHz

accumulation 115 99.6

Maserjian 190.5 ± 4.5% 118.5 ± 3.0%

Kar 130.0 ± 0.2% 104.5 ± 0.5%

Values in bold represent the calculation based on the appropriate measurement data for the technique. The errors quoted for the Maserjian and Kar method values are based off the percentage difference resulting from fits using 20 and 40 data points.

3.3 Temperature dependence of metal-HfO2-InAs MOS capacitor C-V characteristics

Temperature, like measurement frequency, also affects inversion-regime

capacitance. Increasing the device temperature increases the intrinsic carrier

concentration, and thus, the generation rates. The increased generation rates have their

biggest effect on minority carriers and the inversion-regime capacitance. Figure 3.5

contains C-V curves from HfO2-InAs MOS capacitor wafer 3n, grown at 300 °C and

using 75 cycles, and measured from 223 – 373 K (-50 to 100 °C) at 10 kHz, 100 kHz, and

1 MHz. A bidirectional sweep is performed on two different devices at five temperatures

for each frequency.

99

0

1

2

3

-2 -1 0 1 2C

apac

itanc

e (µ

F/cm

2 )Gate Voltage (V)

373 K (100 °C) 323 (50)296 (23)273 (0)

223 (-50)

10 kHz

2 devices swept up and down at 5 temperatures

wafer 3n

85 × 85 µm2

Au-Ti-HfO2-InAs

HCl (37%) pretreatment300 °C growth temperature

75 ALD cyclesno PMA

(a)

0

1

2

3

-2 -1 0 1 2Gate Voltage (V)

100 kHz

373 K (100 °C) 323 (50)296 (23)273 (0)

223 (-50)Cap

acita

nce

(µF

/cm

2 )

(b)

0

1

2

3

-2 -1 0 1 2Gate Voltage (V)

1 MHz

373 K (100 °C) 323 (50)296 (23)273 (0)

223 (-50)Cap

acita

nce

(µF

/cm

2 )

(c)

Figure 3.5 Capacitance-voltage characteristics of HfO2-InAs wafer 3n, grown at 300 °C for 75 cycles, measured at 10 kHz (a), 100 kHz (b), and 1 MHz (c) at temperatures ranging from 223 to 373 K.

100

At each frequency, the inversion regime capacitance increases with temperature.

The increased generation rates allow the minority carriers to respond to higher

frequencies. In accumulation, majority carriers are able to respond to the measurement

signal at room temperature, and thus, increased temperature has little effect on the

capacitance. At 223 K and 1 MHz, the transition to a HF curve is observed; the bump in

capacitance around -1.5 VDC can be the result of either large interface trap capacitance

[90] or weak inversion response [91].

Figure 3.6 plots the minimum capacitances, Cmin , and hysteresis voltage shifts,

? Vhyst, versus temperature taken from the 10 kHz, 100 kHz, and 1 MHz measurements of

Figure 3.5. Both the minimum capacitance and hysteresis shift increase linearly with

temperature.

0

0.5

1

1.5

2

0

100

200

300

400

500

220 260 300 340 380

Cm

in (

µF/c

m2 ) ∆

Vhyst (m

V)

Temperature (K)

10 kHz100 kHz1 MHz

Au-Ti-HfO2-InAs

HCl (37%) pretreatment300 °C growth temperature

75 ALD cyclesno PMA

wafer 3n

85 × 85 µm2

Figure 3.6 Minimum capacitance (red, left axis) and hysteresis voltage shift (blue, right axis) plotted vs. measurement temperature for HfO2-InAs MOS capacitor wafer 3n measured at 10 kHz, 100 kHz, and 1 MHz.

Since (in the absence of interface trap capacitance) the minimum capacitance is

dependent on the semiconductor doping density, this density can be calculated from the

101

Cmin-T data. Assuming the onset of strong inversion occurs when the semiconductor

surface potential, VS, is equal to twice the bulk potential, 2VB, and the depletion width

becomes fixed at this surface potential, then the maximum depletion width, wmax, is given

by

D

BS

qNV

wε

2max = , (3.3)

where VB is given by (2.3). The minimum HF capacitance is then a series combination of

the oxide and depletion capacitances,

1

maxmin

1−

+=

SOX

wC

Cε

. (3.4)

Since the bulk potential, and therefore, maximum depletion width and depletion

capacitance, is temperature dependent, the minimum capacitance is plotted as a function

of temperature for different doping densities against the measured minimum capacitance

at 1 MHz in Figure 3.7 for HfO2-InAs MOS capacitor wafer 3n. The bulk potential is also

dependent on ni, which also has a temperature dependence. The temperature-dependent ni

is calculated from empirical relationships for InAs from [72]. The oxide capacitance used

in the theoretical calculations is determined by applying the Kar method to the 10 kHz,

373 K C-V measurement of wafer 3n and results in a value of 3.1 µF/cm2.

102

0

0.4

0.8

1.2

1.6

220 260 300 340 380

Cm

in (µ

F/cm

2 )

Temperature (K)

measured @ 1 MHzEq. 3.4

ND = 2 × 1019 cm-3

2 × 1018

2 × 1017

2 × 1016

COX

= 3.1 µF/cm2

wafer 3n

Cmin

from simulated (Vogel) QS curve

Figure 3.7 Theoretical and measured minimum capacitance vs. temperature. Theoretical values are calculated from (3.4) for doping densities ranging from 2 × 1016 to 2 × 1019 cm-3 using a COX of 3.1 µF/cm2, calculated from the Kar method applied to the 10 kHz, 373 K data of HfO2-InAs MOS capacitor wafer 3n. Measured values are the minimum capacitances of wafer 3n at 1 MHz.

It is clear from the analysis in Figure 3.7 that (3.4) is not an accurate model for

the 1 MHz minimum capacitance of wafer 3n. Unlike the measured minimum

capacitance, the theoretical minimum capacitance exhibits little dependence on

temperature. At the manufacture-quoted doping density of 2 × 1016 cm-3, (3.4) fails to

predict the magnitude of the measured minimum capacitance as well, being off by a

factor of more than 11× at room temperature. This is a major difference which is worth

further consideration.

One assumption made in this calculation is that the minimum capacitance can be

acquired from the HF C-V curve. Looking at the data in Figure 3.5(c), this is clearly not

the case, as the capacitance never flattens out in the inverse bias polarity. The apparent

inversion capacitance increases the minimum measured capacitance. However, as

103

indicated by the blue dot in Figure 3.7, which is the expected QS capacitance minimum

as calculated by the Vogel simulator (see Section 2.2 and [64]), this increase due to

inversion is by a factor of less than 2× at room temperature. The inversion capacitance

alone is not enough to explain the difference between the calculated and observed

minimum capacitance.

The fact that (3.3) and (3.4) fail to explain both the magnitude and temperature

dependence of the minimum capacitance could be because interface traps are ignored.

The observed hysteresis voltage shift in wafer 3n suggests that trapping is an important

factor in these capacitors. Modifying (3.4) to include capacitance due to interface traps

allows one to calculate the interface trap capacitance, CIT,

max

1

min

11wCC

C S

OXIT

ε−

−=

−

. (3.5)

The interface trap density is then calculated using

qC

D ITIT = . (3.6)

Since it is assumed the minimum capacitance occurs at a known value of the surface

potential (VS = 2VB), the interface trap density calculated at each temperature may be

mapped to an energy, ET, within the bandgap using the following relations,

)()( TiiCTC EEEEEE −+−=− , (3.7)

−=− *

*

ln43

2 n

pB

GiC m

mTk

EEE , and (3.8)

=−=−=−

i

DBBSBTi n

NTkVVVEE ln , (3.9)

104

where *pm and *

nm are the hole and electron DOS effective masses, respectively, and EG

and ni are functions of temperature.

The interface-trap-density-energy profile calculated for wafer 3n using this

method is plotted in Figure 3.8. The calculation assumes an oxide capacitance of 3.1

µF/cm2 and a doping density of 2 × 1016 cm-3, and that an HF (but not THF as defined in

Section 2.2) curve is used. Since inversion capacitance also contributes to the minimum

capacitance, even in the 1 MHz data used for this calculation, the resulting DIT values

could be overestimated by a factor of 2× or more, according to the Vogel simulation of

the QS minimum capacitance. Despite this possible source of error, the method results in

a magnitude for the interface state density which is consistent with other III-V MOS

reports in the 1012 – 1013 cm-2eV-1 range [52, 92]. The increased trap dens ity with

temperature agrees with the increased hysteresis shift with temperature observed in wafer

3n. The linearity of the data shows that the interface trap capacitance is an exponential

function of surface potential, and thus, confirms one of the assumptions made by the Kar

method.

105

1012

1013

1014

0 0.1 0.2 0.3

DIT

(cm

-2eV

-1)

EC - E

T (eV)E

CE

V

373 K323

296273

223wafer 3n

Au-Ti-HfO2-InAs

HCl (37%) pretreatment300 °C growth temperature

75 ALD cyclesno PMA

85 × 85 µm2

COX

= 3.1 µF/cm2

ND = 2 × 1016 cm-3

Figure 3.8 Interface trap density, DIT, vs. position in bandgap, EC – ET, for HfO2-InAs MOS capacitor wafer 3n calculated using (3.5) – (3.9) and the 1 MHz minimum capacitance measured using temperatures ranging from 223 to 373 K.

A HF frequency curve is not observed at room temperature at 1 MHz in Au-Ti-

HfO2-InAs MOS devices. In Figure 3.5, the transition to a HF curve is seen to begin at

223 K, however, there is still a bump around -1.5 VDC in the capacitance, which

prevents a THF curve (one in which neither interface traps nor minority carriers respond)

from being observed. Wafers are cooled with liquid nitrogen (LN2) and measured using

the LT configuration to obtain THF curves. Figure 3.9 contains the room- and LN2-

temperature C-V measurements of annealed wafer 2a, which is grown at 200 °C with 75

cycles.

106

0

0.5

1

1.5

2

2.5

-4 -2 0 2 4

Cap

acita

nce

(µF/

cm2 )

Gate Voltage (V)

room temperaturemeasurement

liquid nitrogenmeasurement

10 kHzLT connection

wafer 2aAu-Ti-HfO

2-InAs

HCl (37%) pretreatment200 °C growth temperature

75 ALD cycles400 °C, 2 min., N

2 PMA

85 × 85 µm2

77 K

300 K

Figure 3.9 Room (red) and liquid nitrogen (blue) temperature C-V curves of annealed Au-Ti-HfO2-InAs MOS capacitor from wafer 2a, grown at 200 °C for 75 cycles, measured at 10 kHz.

Even at 10 kHz, a THF is observed when the wafer is cooled with LN2. The

device temperature is assumed to be 77 K, the boiling point of LN2. The frequency of 10

kHz is used so that both a LF and THF curve is measured simply by changing the

temperature. The constant frequency eliminates the need for instrument recalibration

between LF and THF measurements. The difference between the room temperature and

LN2 temperature curves, hereafter referred to as the LF and THF curves, in depletion and

accumulation is attributed to interface trap capacitance.

Taking the difference between the two curves in depletion and accumulation, in

this case, when VG > -0.8 V, allows one to determine the interface trap capacitance using

111111

−−

−−

−=

OXTHFOXLFIT CCCC

C , (3.10)

where CLF and CTHF are the LF and THF capacitances, respectively, and COX is

determined using the Kar method. This is known as the high-frequency-low-frequency

107

(HF-LF) method [93]. The interface trap density is obtained using (3.6). Equations (3.10)

and (3.6) give the interface trap density as a function of gate bias. The remaining step is

to relate the gate bias to the surface potential so that DIT may be plotted as a function of

position in the bandgap.

The surface-potential-gate-bias relationship is determined experimentally using

the LF curve and

G

V

V OX

LFGS dV

CC

VVG

FB

∫

−= 1)( , (3.11)

where VS is a function of VG and the flatband voltage, VFB, is independently determined.

From (2.1), the flatband voltage for a Ti-oxide-InAs MOS device doped 2 × 1016 cm-3 n-

type with no oxide trap charge or interface states is -0.6 V. Using the Terman method

(described later), the flatband voltage for wafer 2a, a Au-Ti-HfO2-InAs MOS device

wafer, is measured to be closer to -0.8 V.

Using VFB = -0.8 V and (3.11), VS is plotted as a function of VG using the LF curve

of wafer 2a in Figure 3.10. The surface potential is related to position in bandgap using

(3.7), (3.8), and

Si

DBSBTi V

nN

TkVVEE −

−=−=− ln . (3.12)

The interface trap density versus position in bandgap is plotted in Figure 3.11.

108

-0.2

0

0.2

0.4

0.6

0.8

1

-1 0 1 2 3 4

VS (

V)

VG (V)

Eq. 3.11

COX

= 2.17 µF/cm2

VFB

= -0.8 V wafer 2aAu-Ti-HfO

2-InAs

HCl (37%) pretreatment200 °C growth temperature

75 ALD cycles400 °C, 2 min., N

2 PMA

85 × 85 µm2

C from 10 kHz,room temperature measurement

VS-V

G from the HF-LF method

Figure 3.10 Surface potential vs. gate voltage calculated for HfO2-InAs MOS capacitor wafer 2a from (3.11) using the 10 kHz, room temperature C-V measurement.

1012

1013

1014

-0.8 -0.6 -0.4 -0.2 0 0.2

DIT

(cm

-2eV

-1)

EC - E

T (eV)

wafer 2aAu-Ti-HfO

2-InAs

HCl (37%) pretreatment200 °C growth temperature

75 ALD cycles400 °C, 2 min., N

2 PMA

85 × 85 µm2

EC

DIT from the HF-LF method

Figure 3.11 Interface trap density vs. position in bandgap for wafer 2a, calculated using the HF-LF method.

The HF-LF calculation results in an interface state density minimum that occurs

well above the conduction band, in contrast to other reports in which the minimum occurs

within the bandgap [52, 92]. It should be noted that the calculation of surface potential

109

and position in bandgap using (3.11) is dependent on the choice of flatband voltage; this

could explain why the application of the HF-LF method to wafer 2a results in trap levels

well above the conduction band.

The HF-LF method is valid only in the depletion and accumulation regimes where

there is no inversion capacitance, which as seen in Figure 3.11, limits the method’s

ability to probe trap densities deep into the bandgap. The Terman [94] method compares

the THF curve to a theoretical THF curve. This allows THF data measured up to the

threshold voltage to be used in the calculation of interface trap density.

For a given COX and a given value of measured THF capacitance, CTHF, the

surface potential in an ideal (no interface traps) and actual (with interface traps) device is

the same. The simple model of Chapter 2 can then be used to compute the theoretical,

normalized THF capacitance, CTHF/COX, versus surface potential. The model uses (2.5)

and (2.6) to calculate the curve in accumulation (when VS > 0) and (2.9) and (2.10) to

calculate the curve in depletion and inversion (when VS < 0). However, as shown in

Figure 3.12, this approach produces a CTHF/COX curve with a discontinuity due to the

sudden change from equilibrium capacitance to depletion capacitance at the flatband

voltage (VS = 0). A more accurate way to model the THF capacitance is to use (2.5) and

(2.6) for both accumulation and depletion with the charge due to minority carriers “turned

off” (pn0 = 0 for the n-type case). Figure 3.12 plots the THF capacitance versus surface

potential calculated using both approaches.

110

0

0.2

0.4

0.6

0.8

1

-0.3 -0.2 -0.1 0 0.1 0.2

CT

HF/C

OX

VS (V)

T = 77 K

COX

= 2.17 µF/cm2

εS = 12.3

ni = 5.4 × 103 cm-3

ND

= 2 × 1016 cm- 3

accumulationdepletion

Eqs. 2.5 & 2.6

Eqs. 2.9 & 2.10

Eqs. 2.5 & 2.6(p

n0 = 0) theoretical

THF capaciance

metal-oxide-InAs

Figure 3.12 Theoretical THF capacitance vs. surface potential for a metal-oxide-InAs MOS capacitor at 77 K using different models for depletion capacitance.

Once the CTHF-VS relationship is established, it is compared to a measured CTHF-

VG curve to map out how VS relates to VG. Figure 3.13 contains the theoretical CTHF/COX-

VS (a) and measured CTHF/COX-VG (b) plots used to calculate VS(VG) for wafer 2a. For

each point, VS, on the theoretical curve, the point, VG, on the measured curve is found that

has the same capacitance. As an example, the flatband voltage is found in Figure 3.13 by

matching VS(0) to the value of VG that has the same capacitance. The flatband voltage is

calculated to be -0.9 V. Figure 3.14 is the full VS-VG curve found using this technique.

111

0

0.2

0.4

0.6

0.8

1

-0.3 -0.2 -0.1 0 0.1 0.2

CT

HF/C

OX

VS (V)

T = 77 K

COX

= 2.17 µF/cm2

ND

= 2 × 1016 cm-3

accumulationdepletion

theoreticalTHF capaciance

VS(0) = 0.25

0

0.2

0.4

0.6

0.8

1

-4 -2 0 2 4V

G (V)

wafer 2aAu-Ti-HfO

2-InAs

HCl (37%) pretreatment200 °C growth temperature

75 ALD cycles400 °C, 2 min., N

2 PMA

85 × 85 µm2

10 kHz77 K

VG(-0.79) = 0.25

VFB

= -0.79 V

accumulationdepletion

(a) (b)

Figure 3.13 Theoretical capacitance-surface-potential (a) and measured capacitance-gate-bias (b) plots for wafer 2a showing determination of the flatband voltage [VFB = VG(VS = 0)].

-0.3

-0.25

-0.2

-0.15

-0.1

-0.05

0

0.05

-4 -3 -2 -1 0 1 2 3 4

VS (

V)

VG (V)

wafer 2aAu-Ti-HfO

2-InAs

HCl (37%) pretreatment200 °C growth temperature

75 ALD cycles400 °C, 2 min., N

2 PMA

85 × 85 µm2

VS-V

G from the Terman method

Figure 3.14 Surface potential vs. gate bias. The interface trap density as well as the flatband voltage may be obtained from this plot.

Using the slope of the curve in Figure 3.14, dVS/dVG, the interface trap

capacitance is found with

)(1)(1

SSG

SOXSIT VC

dVdV

CVC −

−

=

−

, (3.13)

112

where CIT and CS are functions of VS and CS is found by taking the derivative of (2.5)

with respect to VS [62]. Equation (3.6) is used to find the interface trap density and (3.7),

(3.8), and (3.12) are used to relate surface potential to position in bandgap. Figure 3.15

plots the resulting interface trap density profile for wafer 2a.

1013

1014

1015

1016

-0.1 0 0.1 0.2 0.3

DIT

(cm

-2eV

-1)

EC - E

T (eV)

wafer 2aAu-Ti-HfO

2-InAs

HCl (37%) pretreatment200 °C growth temperature

75 ALD cycles400 °C, 2 min., N

2 PMA

85 × 85 µm2

DIT from the Terman method

Figure 3.15 Interface trap density vs. position in bandgap for HfO2-InAs MOS capacitor wafer 2a calculated using the Terman method.

Low temperature characterization is also used to test for the existence of an

inversion layer composed of mobile carriers. Koester et al. use light-dependence

measurements to see if inversion-regime capacitance in ALD-HfO2-a-Si-n-GaAs MOS

capacitors is the result of an inversion layer of mobile carriers or immobile trapped

charge. The claim is that if a dark measurement yields a HF curve and an illuminated

measurement yields a LF curve, then a true inversion layer is present. Their argument is

as follows:

113

“The purpose of the illumination can be understood by considering a capacitor on p-type GaAs. First of all, the peripheral illumination provides a source of charge such that a quasiequilibrium surface electron layer can be maintained as the gate bias is swept to positive voltages, thus preventing the device from going into deep depletion. Secondly, the illumination reduces the potential barrier from the surface electron layer to the bulk material at the edges of the dot, so that the electrons can respond to the ac excitation signal faster than when the sample is tested in the dark. The presence of surface electrons is therefore confirmed if conditions can be found where ‘high-frequency’ C-V behavior is observed in the dark, but ‘low-frequency’ behavior is observed under illumination, since this situation can only occur by means of lateral transport of free electrons between the interior and edges of the dot. A similar situation applies to identifying surface hole transport in MOS capacitors on n-type GaAs.”

Koester et al. [95]

It is still possible that interface traps, and not free carriers, could give rise to this

kind of light-dependent behavior [96]. To explore the effect of illumination, a similar test

is conducted on a Au-Ti-HfO2-InAs MOS capacitor from wafer 2a, and plotted against

the results of Koester et al. [95] in Figure 3.16. Inversion-regime light-dependence in

wafer 2a is measured at 77 K using the LT setup to achieve the HF condition required for

the measurement. The illumination increases the inversion-regime saturation capacitance

from 4 to 40 % of the maximum capacitance in wafer 2a, while the inversion capacitance

exceeds the accumulation capacitance in the HfO 2-a-Si-GaAs device. Inversion

capacitance is dependent on the illumination intensity and could explain why the HfO 2-a-

Si-GaAs device exhibits higher inversion capacitance than the device from this work; a

brighter illumination source could have been used. Not all wafers exhibit inversion-

regime light dependence and the saturation level is dependent on the processing

conditions.

114

0

1

2

-4 -2 0 2 4

Cap

acita

nce

(µF/

cm2 )

Gate Voltage (V)

300 K100 Hz

light on

light off

wafer 2aAu-Ti-HfO

2-InAs

HCl (37%) pretreatment200 °C growth temperature

75 ALD cycles400 °C, 2 min., N

2 PMA

85 × 85 µm2

77 K10 kHz

Koester et al.HfO

2-α-Si-GaAs

(NH4)

2S pretreatment

300 °C growth temperature8.3 nm HfO

2, 1.9 nm α-Si

800 °C, 1 min., N2 anneal

100 µm diameter

Figure 3.16 Capacitance-voltage curves with and without illumination for HfO2-InAs MOS capacitor wafer 2a and a HfO 2-a-Si-GaAs MOS capacitor from [95].

3.4 Dependence of film thickness on metal-HfO2-InAs MOS capacitor properties

Transmission electron microscopy performed by Tom Kosel at Notre Dame on

unannealed wafer 6n, pretreated with HCl (37%) and grown at 200 °C for 50 cycles,

reveals an HfO 2 film that ranges from 3.5 to 4.5 nm in thickness with a 1 – 2 nm bright

layer in between the HfO2 and InAs that is possibly native arsenic or indium oxide

formed before or during ALD, Figure 3.17. To reduce InAs surface roughness, the HCl

pretreatment used in the second wafer matrix is diluted 1:1 with water to make a 18.5%

solution. TEM provides an accurate measurement of MOS oxide film thickness, as the

high resolution provided by the technique allows for comparison with the lattice constant

of the semiconductor.

115

Figure 3.17 TEM micrographs of unannealed HfO 2-InAs MOS capacitor wafer 6n. The substrate is pretreated with HCl (37%). The HfO 2 is grown using 50 ALD cycles and a temperature of 200 °C. Images taken by Tom Kosel.

X-ray photoelectron spectroscopy is a surface chemical analysis technique that

can determine the chemical composition of oxide-semiconductor interfaces. X-ray

photons penetrate from one to ten nanometers into the substrate. The energy of the

photons is absorbed, resulting in the emission of an electron from the material surface.

The number and energy of these emitted electrons is measured and the resulting electron-

count-energy profiles are analyzed to determine chemical properties of the material.

Bonds within the material have characteristic binding energies which allow XPS to

determine which bonds are present and in what quantity.

116

Collaborators at Lund performed XPS measurements on high-k-InAs and bare

InAs wafers to study the effects of ALD precursor, chemical pretreatment, and deposition

temperature on the chemical composition of the wafers. The high-k films are thin enough

(= 2 nm) that x-ray photons easily penetrate the oxide, reaching and revealing

information about the oxide and the semiconductor-oxide interface. This information

gives a chemical- level understanding of the effects of processing conditions and supports

conclusions drawn from electrical data.

XPS can also be used to determine film thickness. Oxide film thickness is

determined by comparing the signal intensity at the In-As binding energy in the In 3d

spectra of a wafer with an oxide film against a wafer without an oxide film. The thicker

an oxide film is, the more it will attenuate the In-As signal originating from the InAs

substrate. A model contained in the software fitxps2 [97] is used by Kees-Jan Weststrate

of Lund to determine film thicknesses. The data from each sample is normalized by either

the measurement photon flux or the background signal before fitting. Each normalization

method results in a different answer for film thickness and provides an error bar for the

technique. The In 3d XPS spectra of wafers X2 and X8, pretreated with HF and grown at

250 °C with 25 and 50 ALD cycles, respectively, is shown in Figure 3.18. In the figure,

the data is normalized by the background signal level. The 50-cycle film exhibits a

weaker In-As peak than the 25-cycle film. The table inset shows the values of film

thickness extracted using the technique.

117

442444446Binding Energy (eV)

Eph

= 890 eV

In-O In-As

Inte

nsity

(arb

. uni

ts)

25 ALD cycles

50

HfO2-InAs

wafers X2 and X8HF pretreatment250 °C growth

3.5

1.6

Photonflux

3.250

N/A25

Backgroundsignal

ALDcycles

3.5

1.6

Photonflux

3.250

N/A25

Backgroundsignal

ALDcycles

thickness estimate (nm)In 3d

Figure 3.18 Indium 3d XPS spectra of HfO 2-InAs heterostructures grown using 25 (red) and 50 (blue) ALD cycles at a temperature of 250 °C (wafers X2 and X8). The samples are pretreated with HF. The table inset contains the HfO 2 film thickness estimates calculated from the XPS signals based on signal normalization by the background signal and the photon flux.

The HfO2 films on wafers E1, E2, and E3 are measured using spectroscopic

ellipsometry. The wafers contain films grown at 250 °C using 40, 150, and 300 cycles.

The spectroscopic ellipsometry technique also relies on a model fit to extract film

thickness, requiring the complex refractive index of the measured materials to be known

at each wavelength used. The thicknesses measured using TEM, XPS, and ellipsometry

are plotted versus ALD cycles in Figure 3.19 to determine the thickness of HfO 2

deposited during each ALD cycle. The rate is determined to be 0.074 ± 0.01 nm/cycle.

The error bar is calculated from the TEM images; the 50-cycle film shown in Figure 3.17

fluctuates by ± 0.5 nm. The linear fit of the measurement data features a nonzero y-

intercept, likely the result of the bright layer existing between the HfO 2 and InAs seen in

the TEM images. This growth rate is just below the rate of 0.093 ± 0.001 obtained in [79]

118

and could be the result of insufficient (non-saturating) precursor dose times, which leads

to less than total wafer coverage during an ALD cycle [79].

0

10

20

30

0 100 200 300

y = 0.19059 + 0.073616x R= 0.99613

HfO

2 th

ickn

ess

(nm

)

# of ALD cycles

XPSellipsometry

TEM

growth rate:0.074 nm/cycle with

0.190 nm offset

9.4125

5.775

3.950

3.140

2.430

thickness (nm)ALD cycles

9.4125

5.775

3.950

3.140

2.430

thickness (nm)ALD cycles

Figure 3.19 Hafnium dioxide film thickness on InAs versus number of ALD growth cycles, wafers E1, E2, E3, X2, X8, and 6n. Film thicknesses are measured with XPS, ellipsometry, and TEM. The table inset contains the thicknesses calculated from the linear fit of the data.

Figure 3.20 contains the 1 MHz C-V curves of Au-Ti-HfO2-InAs MOS devices

grown at 200 (a) and 300 (b) °C using cycles ranging from 30 to 125. The capacitance

plotted is the measured equivalent parallel capacitance. At each growth temperature, the

maximum capacitance occurs in accumulation and increases with decreasing film

thickness. The capacitance does not increase in inversion for capacitors grown using 50

or fewer ALD cycles; this is the result of high leakage current unbalancing the impedance

measurement bridge, yielding inaccurate results. This is not observed in Au-Pd-based

devices, which exhibit lower leakage currents (shown later).

119

0

1

2

3

4

5

-3 -2 -1 0 1 2 3

Cap

acita

nce

(µF

/cm

2 )

Gate Voltage (V)

Au-Ti-HfO2-InAs

wafers 2n, 6n, and 7nHCl (37%) pretreatment

no PMA

85 × 85 µm2

1 MHz

200 °C growth temperature

50 ALD cycles

75

125

(a)

0

1

2

3

4

5

-3 -2 -1 0 1 2 3

Cap

acita

nce

(µF

/cm

2 )

Gate Voltage (V)

wafers 11tn, 12tn, and 13tnAu-Ti-HfO

2-InAs

HCl (18.5%) pretreatment

35 × 35 µm2

1 MHz

300 °C growth temperature

30 ALD cycles

4050

75

wafer 3nAu-Ti-HfO

2-InAs

HCl (37%) pretreatment

85 × 85 µm2

(b)

Figure 3.20 Capacitance-voltage characteristics of unannealed Au-Ti-HfO2-InAs MOS capacitors grown at 200 (a) and 300 (b) °C with ALD cycles ranging from 30 to 125 measured at 1 MHz.

The dielectric constant of HfO 2 films grown at 200 °C is determined by

calculating the capacitance equivalent thickness (CET) of films grown using 50, 75, and

125 ALD cycles. The CET is given by

120

M

SiO

CA

2CETε

= , (3.14)

where A is the device area and CM is the measured capacitance. The measured

capacitance is taken at some defined gate voltage and can be in either inversion or

accumulation. Note that CET is different from EOT. The EOT, given by (2.11), is a

function only of the oxide film’s thickness and dielectric constant, while the CET is a

function of the measured capacitance, and thus, includes semiconductor- and interface-

related effects such as surface quantization and interface trap capacitance. Since CET

includes these effects, it is the most relevant to MOSFET devices, as it governs drive

current. EOT is useful because it provides an unambiguous way to compare between

alternative gate dielectrics, independent of the channel and gate electrode material used.

In MOS devices in which the measured capacitance saturates to the oxide capacitance,

the CET and EOT are equal.

Figure 3.21 contains low frequency (10 kHz) C-V characteristics of wafers 2n, 6n,

and 7n, unannealed Au-Ti-HfO2-InAs MOS capacitors grown at 200 °C with 50, 75, and

125 ALD cycles, respectively. The measured capacitance of each wafer at VG = +1.9 V is

used to calculated the CET. The CETs are plotted versus physical film thickness in

Figure 3.22. The physical film thicknesses used for the plot are calculated using the rate

found in Figure 3.19 (without the 0.190 nm offset). The relative dielectric constant of the

film is 23 from the slope of a linear fit of the data. The CET of the interlayer (the layer

between the HfO 2 and InAs) is 0.8 nm, found from the y-intercept of the plot. The

interlayer CET is approximately equal to the interlayer thickness observed in the TEM

images of Figure 3.17, indicating that the interlayer dielectric constant is near that of SiO 2

(3.9e0).

121

0

1

2

3

4

5

-3 -2 -1 0 1 2 3

Cap

acita

nce

(µF

/cm

2 )

Gate Voltage (V)

Au-Ti-HfO2-InAs

wafers 2n, 6n, and 7nHCl (37%) pretreatment

no PMA

85 × 85 µm2

10 kHz

200 °C growth temperature

50 ALD cycles

75

125

Figure 3.21 Capacitance-voltage characteristics of unannealed Au-Ti-HfO2-InAs MOS capacitors grown at 200 °C with 50, 75, and 125 ALD cycles measured at 10 kHz.

0

1

2

0 2 4 6 8 10

y = 0.83546 + 0.16826x R= 0.99269

CE

T (n

m)

Physical Thickness (nm)

εOX

= 23ε0

Au-Ti-HfO2-InAs

wafers 2n, 6n, and 7nHCl (37%) pretreatment

200 °C growth temperatureno PMA

85 × 85 µm2

capacitance equivalent thickness (CET)calculated from 10 kHz measurement

in accumulation (VG = +1.9 V)

Figure 3.22 Capacitance equivalent thickness versus physical thickness of unannealed Au-Ti-HfO2-InAs MOS capacitors grown at 200 °C with 50, 75, and 125 ALD cycles measured at 10 kHz and +1.9 VDC.

The dielectric constant of unannealed films grown at 200 °C is 23 based on

measurements taken at +1.9 VDC. However, since in these InAs-based MOS devices, the

122

accumulation does not saturate in the range of gate biases used, the calculated dielectric

constant depends on the gate bias. Figure 3.23 plots the relative dielectric constant

calculated using different gate biases. The calculated eOX increases as the gate bias used

approaches the flatband voltage. The value at +1.9 V is taken to be the most accurate as

the capacitance measured at this point is closest to the oxide capacitance. EOT is

calculated using the physical thickness and a relative dielectric constant of 23. The

physical thickness, CET, and EOT values of the wafers used in this measurement are

summarized in Table 3.7.

0

10

20

30

0 0.5 1 1.5 2

ε OX (ε

0)

VG (V)

Au-Ti-HfO2-InAs

wafers 2n, 6n, and 7nHCl (37%) pretreatment

200 °C growth temperatureno PMA

85 × 85 µm2

relative HfO2 dielectric constant calculated

using CETs taken from different values of VG

Figure 3.23 Relative dielectric constant of HfO 2 calculated using CET measurements taken at 10 kHz and different gate biases on Au-Ti-HfO2-InAs MOS capacitors grown at 200 °C using 50, 75, and 125 ALD cycles.

123

TABLE 3.7

PHYSICAL, CAPACITANCE EQUIVALENT, AND EQUIVALENT OXIDE

THICKNESSES OF AU-TI-HFO2-INAS MOS CAPACITORS GROWN USING 50, 75,

AND 125 ALD CYCLES

ALD cycles Physical thickness (nm)

CET (nm) EOT (nm)

50 3.9 1.4 0.7

75 5.7 1.8 1.0

125 9.4 2.4 1.6

Measurements on HfO2-InAs MOS capacitor wafers 2n, 6n, and 7n. Physical thickness based off growth rate calculated in Figure 3.19. CET calculated from 10 kHz, +1.9 VDC measurement. EOT calculated using relative dielectric constant of 23 and physical thicknesses shown in the table.

Like capacitance, leakage current due to tunneling is strongly dependent on oxide

film thickness. Figure 3.24 contains the J-V curves of Au-Ti-HfO2-InAs MOS devices

grown at 200 (a) and 300 (b) °C using cycles ranging from 30 to 125. The 75- and 125-

cycle films grown at 200 °C do not exhibit strong oxide thickness dependence and is an

indication that a mechanism other than tunneling, such as thermionic emission, is

responsible for the leakage in these films. The films grown at 300 °C do exhibit strong

thickness dependence, with a 10-cycle (~0.7 nm) decrease in oxide thickness leading to

roughly a decade increase in leakage current at ±1 V.

124

10-10

10-8

10-6

10-4

10-2

100

-3 -2 -1 0 1 2 3

Cur

rent

Den

sity

(A/c

m2 )

Gate Voltage (V)

50

75

125 ALD cycles

Au-Ti-HfO2-InAs

wafers 2n, 6n, and 7nHCl (37%) pretreatment

no PMA

85 × 85 µm2

200 °C growth temperature

(a)

10-10

10-8

10-6

10-4

10-2

100

-3 -2 -1 0 1 2 3

Cur

rent

Den

sity

(A/c

m2 )

Gate Voltage (V)

50

75

Au-Ti-HfO2-InAs

wafer 3nHCl (37%) pretreatment

85 × 85 µm2

Au-Ti-HfO2-InAs

wafers11tn, 12tn, and 13tn

HCl (18.5%) pretreatment

35 × 35 µm2

40

30 ALD cycles300 °C growth temperature

(b)

Figure 3.24 Current-density-voltage characteristics of unannealed Au-Ti-HfO2-InAs MOS capacitors grown at 200 (a) and 300 (b) °C with ALD cycles ranging from 30 to 125.

The data in Figure 3.24 is fit to a direct tunneling model to see if the leakage

current scaling in 200 and 300 °C films is consistent with direct tunneling. Figure 3.25

contains the fits for the films grown at 200 (a) and 300 (b) °C. The modeling technique

follows the work of Brar et al. [12] and allows for the extraction of the tunneling

125

effective mass of the oxide if the oxide-semiconductor barrier height is known. Plotting

the product of the leakage current density and the square of the oxide thickness, JtOX2,

versus the oxide thickness, tOX, enables one to calculate the magnitude of the electron

wave vector, ?, using

)2exp(02

OXOX tJJt κ−= , (3.15)

where J0 and ? are fitting parameters. With ?, the tunneling effective mass, *OXm , can be

calculated by assuming a parabolic or non-parabolic energy-momentum (E-k)

relationship.

126

10-22

10-20

3 4 5 6 7 8 9 10

J*t O

X

2 (A)

tOX

(nm)

+1 V

+0.5

+0.1

VG =

Au-Ti-HfO2-InAs

wafers 2n, 6n, and 7nHCl (37%) pretreatment

no PMA

85 × 85 µm2

200 °C growth temperature

(a)

10-21

10-19

10-17

10-15

10-13

0 1 2 3 4 5 6

J*t O

X

2 (A)

tOX

(nm)

+1 V

+0.5

+0.1

VG

=

300 °Cgrowth

temperature

Au-Ti-HfO2-InAs

wafers11tn, 12tn, and 13tn

HCl (18.5%) pretreatment

35 × 35 µm2

Au-Ti-HfO2-InAs

wafer 3nHCl (37%) pretreatment

85 × 85 µm2

(b)

Figure 3.25 Direct tunneling model plots for unannealed Au-Ti-HfO2-InAs MOS capacitors grown at 200 (a) and 300 (b) °C with ALD cycles ranging from 30 to 125.

The leakage current density measured at gate biases of +0.1, +0.5, and +1 V is

plotted for both growth temperatures. It is clear from comparison of the two temperatures

that the devices grown at 300 °C (which were grown using fewer ALD cycles) conform

best to the direct tunneling model, providing agreement over five orders of magnitude.

127

Using the non-parabolic E-k assumption, a tunneling effective mass of 0.05 ± 0.01 m0 is

found for the 300 °C films. Regardless of the actual mass that comes out of the model fit,

the relevant point is that the leakage current density of the films grown at 300 °C is

consistent with a direct tunneling description. This exponential dependence of the leakage

current on film thickness lends support to the method of using exponential projections to

predict how these films perform as the thicknesses are further scaled (Chapter 5).

The breakdown voltage is another oxide film property dependent on thickness.

The breakdown voltage of HfO 2 films grown at 300 °C is determined by measuring the

voltage at which irreversible breakdown occurs for 30-, 40-, and 50-cycle films. This

voltage is measured by slowly ramping the applied bias on a film and recording the

voltage at which a sudden jump in leakage current occurs. A subsequent I-V measurement

confirms that the film has been irreversibly changed, exhibiting much higher leakage than

the previous measurement. Figure 3.26 plots the breakdown voltage measured for

multiple devices on each of wafers 11tn, 12tn, and 13tn at 300 and 373 K versus film

thickness. The slope of a linear fit of the data is used to calculate the breakdown field,

FBD.

128

0

0.5

1

1.5

2

2.5

0 1 2 3 4

y = 0.69973 + 0.35156x R= 0.89902 y = 0.76172 + 0.25056x R= 0.99023

Bre

akdo

wn

Vol

tage

(V

)

Physical HfO2 Thickness (nm)

measurement temperature:300 K (room)

373 K (100 °C)

FBD

= 3.5 MV/cm

2.5 MV/cm

Au-Ti-HfO2-InAs

wafers11tn, 12tn, and 13tn

HCl (18.5%) pretreatment300 °C growth temp.

35 × 35 µm2

Figure 3.26 Breakdown voltage (measured at room temperature and 100 °C) vs. film thickness for Au-Ti-HfO2-InAs MOS capacitors grown at 300 °C using 30, 40, and 50 ALD cycles. The breakdown field is calculated at each measurement temperature from the slope of the linear fit to the data.

The breakdown field is 3.5 MV/cm at 300 K and 2.5 MV/cm at 373 K. This

reduction in breakdown field at increased temperature is consistent with amorphous solid

theory [98]. The linear fits of the data do not pass through the origin as would be

expected in the ideal case. This further supports the hypothesis that an interlayer exists

between the InAs and HfO 2 (or perhaps the HfO 2 and gate metal). From the y- intercept of

the linear fits, this interlayer breaks down at around 0.75 V.

The breakdown fields exhibited by these HfO 2 films is lower than high-quality

SiO2, which typically breakdowns around 10 MV/cm [99]. However, just as the physical

film thickness of a high-k material must be scaled by the relative dielectric constant for a

fair comparison to SiO 2, so too must the breakdown field. Figure 3.27 plots equivalent

breakdown field for HfO 2 films grown at different temperatures. Since each data point in

this plot was obtained not from the slope of several data points as in the previous figure

129

but from a single measurement, the flatband voltage is subtracted from the applied

voltage to obtain the true voltage across the oxide. In terms of equivalent field, these

HfO2 films compare favorably to SiO 2.

0

10

20

30

50 150 250 350

Equ

ival

ent F

BD (

MV

/cm

)

HfO2 Growth Temperature (°C)

VFB

= -0.67 V

room temperaturemeasurement

EOTVVF FBBD

equivBD−=,

Au-Ti-HfO2-InAs

wafers8tn, 9tn, 10tn, and 13tn

HCl (18.5%) pretreatment50 ALD cycles

no PMA

35 × 35 µm2

Figure 3.27 Equivalent breakdown field vs. film growth temperature for unannealed Au-Ti-HfO2-InAs wafers 8tn, 9tn, 10tn, and 13tn, grown using 50 ALD cycles.

3.5 Influence of growth temperature on metal-HfO2-InAs MOS capacitor properties

Growth temperature is found to have a significant impact on high-k-InAs device

properties. Figure 3.28 contains the C-V characteristics of 75- (a) and 50- (b) cycle Au-

Ti-HfO2-InAs MOS wafers grown using temperatures ranging from 100 to 350 °C. For

75-cycle films, increased growth temperature produces capacitors that exhibit higher

capacitance and high capacitance modulation, suggesting that the surface potential is

moving with gate bias. The device grown at 100 °C exhibits little capacitance

modulation, suggesting a pinned Fermi level. For the thinner, 50-cycles films, a similar

trend is seen; films grown above 200 °C exhibit higher capacitance and modulation than

130

the film grown at 200 °C. The apparent inversion capacitance in the 350 °C device could

be the result of interface trap capacitance, which fixes the minimum capacitance to a

level higher than would be seen in the trap-free case. The 250 and 300 °C devices may be

free of this trap capacitance, and thus, be able to extend further into depletion.

0

1

2

3

-2 -1 0 1 2

Cap

acita

nce

(µF/

cm2 )

Gate Voltage (V)

Au-Ti-HfO2-InAs

wafers 1n, 2n, and 3nHCl (37%) pretreatment

no PMA

85 × 85 µm2

1 MHz

100 °Cgrowth temperature

200

300

75 ALD cycles

(a)

0

1

2

3

-2 -1 0 1 2

50 ALD cycles

1 MHz

Cap

acita

nce

(µF

/cm

2 )

Gate Voltage (V)

300 °Cgrowth

temperature250350

200Au-Ti-HfO

2-InAs

wafer 6nHCl (37%) pretreatment

200 °C growth temp.no PMA

85 × 85 µm2

Au-Ti-HfO2-InAs

wafers 9tn (250 °C),10tn (350), and 13tn (300)HCl (18.5%) pretreatment

no PMA

35 × 35 µm2

(b)

Figure 3.28 Capacitance-voltage characteristics of unannealed Au-Ti-HfO2-InAs MOS capacitors grown using 75 (a) and 50 (b) ALD cycles and growth temperatures ranging from 100 to 350 °C measured at 1 MHz.

131

Leakage current is also strongly influenced by HfO 2 growth temperature. Figure

3.29 contains the J-V characteristics of 75- (a) and 50- (b) cycle Au-Ti-HfO2-InAs MOS

wafers grown using temperatures ranging from 100 to 350 °C. In both 75- and 50-cycle

films, the highest leakage is exhibited by films grown at 300 °C; films that also exhibit

the highest capacitance. The As and In 3d XPS spectra of unannealed HfO 2-InAs wafers

X2, X5, and X6, grown for 25 cycles at 150, 250, and 350 °C, respectively, are shown in

Figure 3.30. The spectra also show strong growth temperature dependence, with the 150

and 350 °C films exhibiting weaker In-As peaks than the 250 °C film, indicating a thicker

film is produced when these temperatures are used. The Figure 3.30(b) table inset shows

the thicknesses calculated from the In 3d XPS data. The films grown at 150 and 350 °C

are more than 30% thicker than the film grown at 250 °C.

132

10-9

10-8

10-7

10-6

10-5

10-4

10-3

-2 -1 0 1 2

Cur

rent

Den

sity

(A

/cm

2 )

Gate Voltage (V)

75 ALD cycles

100

200

300 °Cgrowth

temperature

Au-Ti-HfO2-InAs

wafers 1n, 2n, and 3nHCl (37%) pretreatment

no PMA

85 × 85 µm2

(a)

10-9

10-8

10-7

10-6

10-5

10-4

10-3

-2 -1 0 1 2

Cur

rent

Den

sity

(A

/cm

2 )

Gate Voltage (V)

50 ALD cycles

200

250

Au-Ti-HfO2-InAs

wafer 6nHCl (37%) pretreatment

200 °C growth temp.no PMA

Au-Ti-HfO2-InAs

wafers 9tn (250 °C),10tn (350), and 13tn (300)HCl (18.5%) pretreatment

no PMA

300

350

(b)

Figure 3.29 Current-density-voltage characteristics of unannealed Au-Ti-HfO2-InAs MOS capacitors grown using 75 (a) and 50 (b) ALD cycles and growth temperatures ranging from 100 to 350 °C.

133

373941434547

Inte

nsity

(ar

b. u

nits

)

Binding Energy (eV)

As-InAs-InAs-O

Eph

= 170 eV250 °Cgrowthtemperature

150350

HfO2-InAs

wafers X2, X5, and X6HF (10%) pretreatment

25 ALD cyclesno PMA

As 3d

(a)

442443444445446

Eph

= 890 eV

In-O In-As

Inte

nsity

(arb

. uni

ts)

Binding Energy (eV)

In 3d

250 °Cgrowthtemperature

150350

1.6N/A250

2.2

2.1

Photonflux

1.9350

1.8150

Backgroundsignal

°C

1.6N/A250

2.2

2.1

Photonflux

1.9350

1.8150

Backgroundsignal

°C

film thickness (nm)

(b)

Figure 3.30 Arsenic (a) and indium (b) 3d XPS spectra for unannealed HfO2-InAs wafers X2, X5, and X6, pretreated with HF and grown using 25 ALD cycles.

134

3.6 Influence of PMA on metal-HfO2-InAs MOS capacitor properties

Post-growth annealing is a common practice in high-k-III-V gate dielectric films

[100, 101]. Figure 3.31 contains C-V characteristics of 75- (a) and 50- (b) cycle Au-Ti-

HfO2-InAs MOS devices before (solid lines) and after (dashed lines) PMA. The annealed,

75-cycle wafers in (a) receive a 400 °C, 2 minute, N2 PMA using an RTP system. The

50-cycle wafers in (b) receive a 200 °C, 1 hour, N2 PMA using the probe station wafer

chuck heating system.

In both cases, the capacitance is increased; however, the most significant effect is

from the 200 °C, 1 hour PMA on the 50-cycle films. In the 50-cycle films grown from

250 to 350 °C, the 200 °C, 1 hour anneal significantly increases the inversion-regime

capacitance. The slope (stretch-out) of the C-V curves is also improved, indicating a

reduction in interface traps. Further support for the reduction of interface traps is given

by the bidirectional C-V sweeps of wafers 3n, 3a, and 13t, 75- and 50-cycle films grown

using 300 °C, in Figure 3.32, which show a reduction in hysteresis voltage shift after

PMA.

135

0

1

2

3

4

-2 -1 0 1 2

Cap

acita

nce

(µF

/cm

2 )

Gate Voltage (V)

Au-Ti-HfO2-InAs

wafers 1n/a, 2n/a, and 3n/aHCl (37%) pretreatment

85 × 85 µm2

1 MHz

100

200

300 °C

75 ALD cycles

solid - no PMAdashed - 400 °C, 2 min., N

2

(a)

0

1

2

3

4

-2 -1 0 1 2

50 ALD cycles

1 MHz

Cap

acita

nce

(µF/

cm2 )

Gate Voltage (V)

300 °C

250350

Au-Ti-HfO2-InAs

wafers 9t (250 °C),10t (350), and 13t (300)

HCl (18.5%) pretreatment

35 × 35 µm2

solid - no PMAdashed - 200 °C, 1 hour, N

2

(b)

Figure 3.31 Capacitance-voltage characteristics of Au-Ti-HfO2-InAs MOS capacitors grown using 75 (a) and 50 (b) ALD cycles and growth temperatures ranging from 100 to 350 °C measured at 1 MHz before (solid lines) and after (dashed lines) PMA. The annealed, 75-cycle wafers in (a) receive a 400 °C, 2 minute, N2 PMA. The 50-cycle wafers in (b) receive a 200 °C, 1 hour, N2 PMA.

136

0

1

2

3

4

-2 -1 0 1 2

Cap

acita

nce

(µF

/cm

2 )

Gate Voltage (V)

Au-Ti-HfO2-InAs

wafers 3n and 3aHCl (37%) pretreatment

85 × 85 µm2

1 MHz

300 °C

75 ALD cycles

solid - no PMAdashed - 400 °C, 2 min., N

2

160PMA

200no PMA

Vhyst (mV)wafer 3

160PMA

200no PMA

Vhyst (mV)wafer 3 ∆

(a)

0

1

2

3

4

-2 -1 0 1 2

50 ALD cycles

1 MHz

Cap

acita

nce

(µF/

cm2 )

Gate Voltage (V)

300 °C

Au-Ti-HfO2-InAs

wafer 13tHCl (18.5%) pretreatment

35 × 35 µm2

solid - no PMAdashed - 200 °C, 1 hour, N

2

120PMA

180no PMA

Vhys t (mV)wafer 13t

120PMA

180no PMA

Vhys t (mV)wafer 13t ∆

(b)

Figure 3.32 Bidirectional capacitance-voltage characteristics of Au-Ti-HfO2-InAs MOS capacitors grown at 300 °C using 75 (a) and 50 (b) ALD cycles measured at 1 MHz before (solid lines) and after (dashed lines) PMA. The 75-cycle, annealed wafer in (a) receives a 400 °C, 2 minute, N2 PMA. The 50-cycle wafer in (b) receives a 200 °C, 1 hour, N2 PMA.

The thickness dependence of PMA effects is explored by measuring the CET of

Au-Ti-HfO2-InAs capacitors grown at 200 °C using 50, 75, and 125 ALD cycles with and

without a 400 °C, 2 minute, N2 PMA. Figure 3.33 plots the CET of the devices measured

137

at 10 kHz and +1.9 VDC versus physical thickness. Both the dielectric constant of the

oxide and the interlayer CET are reduced with PMA. This creates a “crossover” thickness

below which the CET is reduced with PMA and above which the CET is increased with

PMA. This could explain why the thinner, 50-cycle films in the previous figures are more

affected by PMA. The reduced interlayer CET is consistent with the evidence from the

previous figures of reduced interface trap density.

0

1

2

3

0 2 4 6 8 10

y = 0.83546 + 0.16826x R= 0.99269 y = 0.28816 + 0.24135x R= 0.99994

CE

T (n

m)

Physical Thickness (nm)

no PMAε

OX = 23ε

0Au-Ti-HfO

2-InAs

wafers 2n/a, 6n/a, and 7n/aHCl (37%) pretreatment

200 °C growth temperature

85 × 85 µm2εR = 16ε

0

400 °C, 2 min. N2 PMA

Figure 3.33 Capacitance equivalent thickness versus physical thickness of Au-Ti-HfO2-InAs MOS capacitors grown at 200 °C with 50, 75, and 125 ALD cycles measured at 10 kHz and +1.9 VDC with (red) and without (blue) a 400 °C, 2 minute, N2 PMA.

The effect of PMA on leakage current is studied to explore the thermodynamic

stability of the films. Figure 3.34 shows the J-V characteristics of Au-Pd-HfO2-InAs

wafer 8p, grown at 80 °C for 50 cycles, before and after a 1 hour anneal at 200 °C in N2.

The leakage current is substantially reduced following the PMA. The PMA reduces the

leakage current by an order of magnitude without a significant increase in the CET.

While the PMA is beneficial for HfO 2 films grown at 80 °C, this is not true of films

138

grown at higher temperatures. Figure 3.35 shows the J-V curves of wafers 11t, 12t, and

13t, grown at 300 °C with 30, 40, and 50 cycles, respectively, before and after a 1 hour,

200 °C PMA in N2. The leakage is significantly increased for each thickness. Films

grown at 250 and 350 °C also see an increase in leakage after PMA.

10-9

10-8

10-7

10-6

10-5

-1 0 1

Cur

rent

Den

sity

(A

/cm

2 )

Gate Voltage (V)

no anneal

200 °C, 1 hour, N2

CET = 2.32 nm

2.35 nm

Au-Pd-HfO2-InAs

wafer 8pHCl (18.5%) pretreatment80 °C growth temperature

50 ALD cycles

85 × 85 µm2

Figure 3.34 Current-voltage characteristics of HfO2-InAs wafer 8p, grown at 80 °C using 50 cycles, before and after PMA at 200 °C for 1 hour. The current is reduced an order of magnitude without a significant increase in the CET.

139

10-9

10-7

10-5

10-3

10-1

101

103

-1 0 1

Cur

rent

Den

sity

(A/c

m2 )

Gate Voltage (V)

30 ALD cycles

40

50

lines - no PMAcircles - 200 °C, 1 hour, N

2

Au-Ti-HfO2-InAs

wafer 11t, 12t, and 13tHCl (18.5%) pretreatment300 °C growth temperature

85 × 85 µm2

Figure 3.35 Current-voltage characteristics of HfO 2-InAs MOS capacitor wafers 11t, 12t, and 13t, grown at 300 °C using 30, 40, and 50 cycles, respectively, before and after PMA at 200 °C for 1 hour in N2.

Despite the increased leakage current, devices grown using 50 or fewer cycles

still conform to a direct tunneling model after PMA, as shown in Figure 3.36. Using the

non-parabolic E-k relationship, the extracted effective tunne ling mass increases from 0.05

± 0.01 before PMA to 0.15 ± 0.04 m0 after PMA.

140

10-21

10-19

10-17

10-15

10-13

0 1 2 3 4 5 6

y = 5.1558e-9 * e^(-3.8843x) R= 0.99974

y = 6.8224e-9 * e^(-4.9765x) R= 0.99985

y = 1.182e-10 * e^(-5.0163x) R= 0.99982

J*t O

X

2 (A)

tOX

(nm)

+1+0.5VG = +0.1 V

Au-Ti-HfO2-InAs

wafer 11ta, 12ta, and 13taHCl (18.5%) pretreatment

300 °C growth temperature

85 × 85 µm2

after 200 °C,1 hour, N

2

PMA

Figure 3.36 Direct tunneling model plot for annealed Au-Ti-HfO2-InAs wafers 11ta, 12ta, and 13ta, grown using 300 °C and 30, 40, and 50 cycles, respectively, and annealed at 200 °C for 1 hour in N2.

Thermodynamic stability is important for a MOSFET gate dielectric because of

the high processing temperatures involved in the fabrication process. It is important that

the film properties remain constant throughout the lifetime of the device. To further study

thermodynamic stability, in situ J-V characterization is performed on devices during

PMA. Figure 3.37(b) shows how the J-V characteristic of Au-Ti-HfO2-InAs wafer 8t,

grown at 80 °C for 50 cycles, changes before, during, and after the temperature of the

sample is momentarily raised to 100 and 200 °C in an N2 background. The five

measurements shown in the figure are performed in the following order: 1) VG swept

from 0 to +3 V at room temperature; 2) VG swept from 0 to +3 V at 100 °C (the sample

was cooled down to room temperature immediately following); 3) VG swept from 0 to +3

V at room temperature again; 4) VG swept from 0 to +2 V at 200 °C (sample then cooled

to room temperature); 5) VG swept from 0 to +3 V at room temperature. Figure 3.37(a) is

a visual representation of the thermal and measurement history of the device.

141

Tem

p (°

C)

room

100

1

2

200

3 5

4

(a)

10-9

10-8

10-7

10-6

10-5

10-4

10-3

0 1 2 3

Cur

rent

Den

sity

(A/c

m2 )

Gate Voltage (V)

1

2

3

5

4

Au-Ti-HfO2-InAs

wafer 8tHCl (18.5%) pretreatment80 °C growth temperature

50 ALD cycles

85 × 85 µm2

(b)

Figure 3.37 Current-voltage measurements of HfO2-InAs MOS capacitor wafer 8t, grown at 80 °C for 50 cycles, during PMA. The thermal and measurement history is diagramed in (a) and the J-V curves are shown in (b).

Even a momentary, 100 °C PMA reduces the room temperature leakage by a

significant amount (measurement #3). A momentary, 200 °C PMA reduces leakage

further still (#5). The measurements performed at 100 (#2) and 200 (#4) °C exhibit higher

leakage than the room temperature measurements. To determine the time after which

PMA ceases to reduce the leakage current in wafer 8t, the wafer temperature is held at

200 °C in N2 for 1 hour while in situ J-V measurements are taken every ten minutes for

142

the first half-hour. Figure 3.38 contains the history (a) and J-V results (b) of this

measurement. T

emp

(°C

)

room

100

200 8 1097

10 min.10 min.

10 min.10 min.

10 min.10 min.

6 11

(a)

10-9

10-8

10-7

10-6

10-5

10-4

10-3

0 0.5 1 1.5 2

Cur

rent

Den

sity

(A/c

m2 )

Gate Voltage (V)

6

78910

11

Au-Ti-HfO2-InAs

wafer 8tHCl (18.5%) pretreatment80 °C growth temperature

50 ALD cycles

85 × 85 µm2

(b)

Figure 3.38 Current-voltage measurements of HfO2-InAs MOS capacitor wafer 8t, grown at 80 °C for 50 cycles, during 1 hour, 200 °C PMA in N2. The thermal and measurement history is diagramed in (a) and the J-V curves are shown in (b).

The most significant reduction in the leakage current occurs during the first ten

minutes of the anneal (between measurement #7 and #8). Measurements taken at

subsequent times (#9 and #10) reveal a slight increase in the leakage. After 1 hour at 200

°C, the sample is returned to room temperature; the leakage current (#11) is lower than

before the anneal (#6). After 10 minutes of annealing, the film appears to stabilize, that

is, the leakage current level stops changing by large amounts, suggesting that the film is

143

thermally stable (at least up to 200 °C). To confirm this, the sample is put through

another momentary 200 °C thermal cycle, with measurements taken during the ramp-up

and ramp-down phases. Figure 3.39 contains the measurement history (a) and results (b)

of this measurement. In contrast to Figure 3.38, where momentary 100 and 200 °C

thermal cycles produced large shifts in the leakage current, the 200 °C thermal cycle

shown in Figure 3.39, performed after the 1 hour, 200 °C PMA, produced no such shift.

This data suggests that a 1 hour, 200 °C PMA can irreversibly reduce the leakage current

of an HfO2 film grown at 80 °C while increasing thermal stability.

Tem

p (

°C)

room

100

200

13

14

15

12

50

16

17

18

19

(a)

10-10

10-9

10-8

10-7

10-6

10-5

0 0.25 0.5 0.75 1

Cur

rent

Den

sity

(A

/cm

2 )

Gate Voltage (V)

12,19

15,16

13,18

14,17

Au-Ti-HfO2-InAs

wafer 8tHCl (18.5%) pretreatment80 °C growth temperature

50 ALD cycles85 × 85 µm2

(b)

Figure 3.39 Current-voltage measurements of HfO2-InAs MOS capacitor wafer 8t, grown at 80 °C for 50 cycles, during a momentary 200 °C thermal cycle in N2. The thermal and measurement history is diagramed in (a) and the J-V curves are shown in (b).

144

Samples with HfO 2 films grown at temperatures higher than 80 °C exhibit

increased leakage current after PMA. Measurements are performed on Au-Ti-HfO2-InAs

wafer 13t, grown at 300 °C using 50 cycles, before, during, and after a 100 °C thermal

cycle. The results are plotted in Figure 3.40. Unlike wafer 8t, which exhibits a significant

change in leakage current, leakage current in wafer 13t increases only slightly at 100 °C

(measurement #2) and returns to its original level upon cooling back down to room

temperature (#3).

Tem

p (

°C)

room

100

1

2

200

3

(a)

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

0 0.2 0.4 0.6 0.8 1

Cur

rent

Den

sity

(A

/cm

2 )

Gate Voltage (V)

1

23

Au-Ti-HfO2-InAs

wafer 13tHCl (18.5%) pretreatment300 °C growth temperature

50 ALD cycles

85 × 85 µm2

(b)

Figure 3.40 Current-voltage measurements of HfO2-InAs MOS capacitor wafer 13t, grown at 300 °C for 50 cycles, during a momentary 100 °C thermal cycle in N2. The thermal and measurement history is diagramed in (a) and the J-V curves are shown in (b).

145

3.7 Influence of pretreatment on metal-HfO2-InAs MOS capacitor properties

Pre-deposition semiconductor wet chemical treatments (pretreatments) are studied

with C-V, J-V, and XPS characterization. The purpose of pretreatment is to remove any

native oxides that exist on the semiconductor surface prior to oxide deposition, and

thereby reduce the density of interface traps [102]. Figure 3.41 contains 1 MHz C-V (a)

and J-V (b) curves for unannealed Au-Ti-HfO2-InAs wafers 2n, 4n, and 5n, grown at 200

°C using 75 cycles with HCl, (NH4)2S, and BHF pretreatments, respectively. The HCl

and BHF pretreatments yield similar characteristics. The (NH4)2S pretreatment produces

a device with lower capacitance modulation than the other pretreatments, indicative of a

greater density of interface traps. All three pretreatments exhibit similar levels of leakage

current with the (NH4)2S exhibiting higher leakage under reverse bias, possibly due to an

increased amount of trap-assisted conduction.

146

0

1

2

-4 -2 0 2 4

Cap

acita

nce

(µF

/cm

2 )

Gate Voltage (V)

1 MHz

Au-Ti-HfO2-InAs

wafers 2n, 4n, and 5n200 °C growth temperature

75 ALD cyclesno PMA

85 × 85 µm2

(NH4)2S

HClBHF

(a)

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

-4 -2 0 2 4

Cur

rent

Den

sity

(A/c

m2 )

Gate Voltage (V)

Au-Ti-HfO2-InAs

wafers 2n, 4n, and 5n200 °C growth temperature

75 ALD cyclesno PMA

85 × 85 µm2(NH4)2S

BHFHCl

(b)

Figure 3.41 Capacitance-voltage at 1 MHz (a) and current-density-voltage (b) characteristics of unannealed Au-Ti-HfO2-InAs MOS wafers 2n, 4n, and 5n, grown at 200 °C using 75 cycles and HCl, (NH4)2S, and BHF pretreatments, respectively.

The three pretreatments are further distinguished by their low-temperature

characteristics. Figure 3.42 contains 10 kHz C-V curves from wafers 2n, 4n, and 5n

measured at 77 and 300 K. In addition to the expected reduction in inversion-regime

147

capacitance, a large shift along the voltage axis is observed in the (NH4)2S curve while a

large reduction in accumulation capacitance is observed in the BHF curve. Application of

the Terman method to the 10 kHz, 77 K data, Figure 3.43, reveals a large density of

interface traps at the conduction band edge of the BHF device and throughout the upper

half of the bandgap of the (NH4)2S device. The role of interface traps in the low-

temperature behavior of the HCl and BHF devices is discussed further in Section 4.2.2.

0

1

2

-4 -2 0 2 4Gate Voltage (V)

Cap

acita

nce

(µF/

cm2) 10 kHz

300 K

77 K

Au-Ti-HfO2-InAs

wafers 2n, 4n, and 5n200 °C growth temperature

75 ALD cyclesno PMA

85 × 85 µm2

BHF

HCl(NH4)2S

Figure 3.42 Capacitance-voltage characteristics of unannealed Au-Ti-HfO2-InAs MOS wafers 2n, 4n, and 5n, grown at 200 °C using 75 cycles and HCl, (NH4)2S, and BHF pretreatments, respectively, measured at 10 kHz at 300 (solid lines) and 77 (dashed lines) K.

148

1013

1014

1015

1016

0 0.1 0.2 0.3

DIT

(cm

-2eV

-1)

EC - E

T (eV)

Au-Ti-HfO2-InAs

wafers 2n, 4n, and 5n200 °C growth temperature

75 ALD cyclesno PMA

85 × 85 µm2

BHF

HCl(NH

4)2S

DIT

calculated using the Terman method and 77 K data

Figure 3.43 Interface trap density versus position in bandgap for unannealed Au-Ti-HfO2-InAs MOS wafers 2n, 4n, and 5n, grown at 200 °C using 75 cycles and HCl, (NH4)2S, and BHF pretreatments, respectively. The interface trap density is calculated by applying the Terman method to measurements taken at 10 kHz and 77 K.

3.8 Influence of gate metal on metal-HfO2-InAs MOS capacitor properties

Gate length and gate oxide thickness scaling in CMOS has required the

abandonment of polysilicon gates in favor of metal gates [103]. Metal gates lower gate

resistance and gate depletion from which polysilicon gates suffer [104]. However, the use

of metal as the gate material introduces a new challenge. If only one metal is to be used

for both n- and p- type devices, it must align to the mid-gap of the channel. However, this

leads to large threshold voltages and poor short-channel and off-current characteristics

[105]. The alternative is to use two gate metals, one that aligns to the semiconductor

conduction band and one that aligns to the valence band. And while the use of a narrow-

bandgap material such as InAs for the channel presents additional challenges, the fact

149

remains that metal work function is an important quantity in MOSFET design, and thus,

the study of MOS capacitors.

The use of different gate metals results in shifts of the flatband voltage related to

the metal workfunction. Assuming no charge at the oxide-semiconductor interface, the

flatband voltage is simply equal to the work function difference between the metal and

semiconductor which is expressed as

+−−=−=

D

CB

GSMSMFB N

NTk

E?FFFqV ln

2, (3.16)

where FM is the metal work function, FS is the semiconductor work function, ? S is the

semiconductor electron affinity, EG is the semiconductor bandgap, NC is the conduction

band DOS, and ND is the doping concentration . From the substrate manufacturer data,

the doping is known to be 2 × 1016 cm-3 n-type. Using the vacuum values of 5.12 and

4.33 eV for the Pd and Ti work functions, respectively, 4.9 eV for the InAs electron

affinity, 0.35 eV for the InAs bandgap, and 8.7 × 1016 cm-3 for the conduction band DOS,

ideal flatband voltages are +0.12 V for the Pd-HfO2-InAs devices and -0.67 V for the Ti-

HfO2-InAs devices.

Differences in the flatband voltage (due to differences in metal work function)

manifest themselves in C-V characteristics as a shift along the voltage axis.

Characteristics of capacitors with identical HfO 2 layers but different metals are plotted in

Figure 3.44. In Figure 3.44(a), a 0.9 V difference between equal-capacitance points is

seen between the curves of devices from wafers 13tn and 13pn, grown at 300 °C using 50

cycles with Au-Ti and Au-Pd metal contacts, respectively. This is close to the value

expected from the difference in the vacuum work functions of the metals (FPd/q – FTi/q =

5.12 – 4.33 = 0.79 V). By plotting the capacitance of the two devices versus the gate

150

voltage minus the vacuum work function (in V), as is done in Figure 3.44(b), a nearly

continuous characteristic is observed. This is to be expected as at each point along the

voltage-axis, the two devices should have the same InAs surface potential.

0

1

2

3

-1 0 1

Cap

acita

nce

(µF

/cm

2 )

VG (V)

Au-Pd

Au-Ti

1 MHz ∆VFB

= 0.9 V

metal-HfO2-InAs

wafers 13tn and 13pn300 °C growth temperature

50 ALD cyclesno PMA

35 × 35 µm2

(a)

0

1

2

3

-6.5 -5.5 -4.5 -3.5

Cap

acita

nce

(µF

/cm

2 )

VG - Φ

M/q (V)

Au-Pd (ΦM,Pd

= 5.12 eV)

Au-Ti (ΦM,Ti

= 4.33 eV)1 MHz

metal-HfO2-InAs

wafers 13tn and 13pn300 °C growth temperature

50 ALD cyclesno PMA

35 × 35 µm2

(b)

Figure 3.44 Capacitance versus gate voltage (a) and gate voltage minus work function (b) for unannealed metal-HfO2-InAs wafers 13tn and 13pn, grown at 300 °C using 50 cycles with Au-Ti (blue) and Au-Pd (red) contacts.

151

3.9 Summary

Metal-HfO2-InAs MOS capacitors were fabricated by means of ALD and studied

as a function of film growth conditions, surface treatments, and post metallization anneals

for MOSFET applications. The capacitors were evaluated using C-V and J-V over a range

of frequencies and temperatures; XPS, ellipsometry, and TEM characterization were used

to further understand the physical properties.

The Maserjian technique, which uses high-frequency C-V data was compared to

the Kar technique, which uses low-frequency C-V data. The model developed by Kar is

shown to provide the best fit to the measured capacitance data of metal-HfO2-InAs MOS

capacitors.

The temperature dependence of the device properties were examined from 77 to

373 K. In the range of 223 to 373 K, the minimum measured capacitance was used to

calculate midgap interface trap densities for a Au-Ti-HfO2-InAs device grown at 300 °C

using 75 ALD cycles. Low temperature (77 K) measurements were conducted to obtain a

true high-frequency-type curve which was used in conjunction with the Terman method

to calculate interface trap density across the entire bandgap. Low temperature light

dependence measurements provided evidence of inversion capacitance due to mobile

charge carriers.

MOS devices with oxide films grown using ALD cycles ranging from 30 to 125

were used to study how measured characteristics change with oxide thickness. Using a

combination of XPS, ellipsometry, and TEM measurements, an ALD growth rate was

established. TEM images reveal a bright layer that exists between the InAs and HfO 2.

This interlayer produced offsets in plots of CET and breakdown voltage versus expected

152

film thickness. A relative dielectric constant of 23 was calculated by plotting CET versus

physical thickness.

Leakage current and breakdown voltage were measured in devices with varying

film thicknesses. For devices grown using 50 or fewer ALD cycles, leakage current

conformed to a direct tunneling model. Breakdown voltage was shown to scale linearly

with film thickness; breakdown fields of 3.5 and 2.5 MV/cm were calculated for HfO 2

films grown at 300 °C at 300 and 373 K, respectively.

The effects of growth temperature and PMA were studied with C-V, J-V, and XPS

characterization. Both capacitance and leakage is strongly dependent on growth

temperature, with peak capacitance and leakage occurring in films grown at 300 °C.

PMA was found to greatly improve inversion-regime capacitance in 50-ALD-cycle films

while having a lesser effect on thicker, 75-cycle films. This could be the result of a

simultaneous decrease in oxide dielectric constant and interlayer CET that occured during

PMA. When plotting CET versus physical thickness before and after PMA, a crossover

thickness was observed, below which PMA reduces CET and above which PMA

increases CET. In situ J-V characterization was used to study Au-Ti-HfO2-InAs MOS

capacitors grown at 80 and 300 °C during a 200 °C PMA. The devices grown at 80 °C

exhibit large variations in leakage current even after a momentary anneal, while devices

grown at 300 °C exhibit little change.

The influence of semiconductor pretreatment and gate metal was also examined.

Terman measurements performed on Au-Ti-HfO2-InAs devices grown at 200 °C using 75

cycles with HCl, (NH4)2S, and BHF pretreatments reveal that the HCl pretreatment

produces devices with the lowest total (integrated over the bandgap) interface trap

153

densities, while the (NH4)2S pretreatment produces the highest. The high interface trap

density manifests itself in reduced modulation in the measured capacitance. Metal-HfO2-

InAs MOS devices with Au-Ti and Au-Pd gate metals were measured to explore the

effects of gate metal on C-V characteristics. Comparison of curves from devices that use

the two metals show the expected shifts in characteristics versus gate bias.

154

CHAPTER 4:

BILAYER HFO2-AL2O3 INAS MOS CAPACITORS

High-k-InAs MOS capacitors are fabricated using oxide films composed of two

discrete layers. These bilayer dielectrics are shown to improve electrical properties of

interest for MOSFETs. In this study, source precursors and growth temperatures were

explored. The devices were again characterized by C-V, J-V, and XPS measurements and

compared to similar HfO 2-only InAs devices. The HfO 2-Al2O3 structures exhibit lower

leakage current, lower bidirectional C-V sweep hysteresis, and lower interface trap

densities than single- layer HfO2 structures with comparable CETs.

4.1 Fabrication procedure and sample matrices

As shown in Chapter 3, films grown at high temperature had the lowest density of

interface traps while films grown at low temperature had the highest breakdown voltages.

In the bilayer structures, the first layer was grown at high temperature to minimize

interface traps, followed by a second layer grown at low temperature geared toward

maintaining high breakdown voltage. In addition to varying the interfacial growth

temperature, the interfacial layer precursor was also changed for one of the wafers to

create a HfO2-Al2O3-InAs structure.

As with the previous wafers, the bilayer dielectric wafers were grown on 2 × 1016

cm-3 n-type InAs substrates. The wafers received the BHF pretreatment described in

155

Chapter 3. Following pretreatment, the wafers were immediately loaded into the ALD

chamber and ten cycles of the first layer (either Al2O3 or HfO2) were grown at 300 °C

followed by 50 cycles of HfO 2 grown at 100 °C. Trimethylaluminum [TMA, Al2(CH3)6]

and TDMA-Hf were used as the Al2O3 and HfO2 precursors, respectively. This approach

differed from other Al- and Hf-based nanolaminate approaches in that only two discrete

layers were used (e.g. 10 cycles of Al2O3 followed by 50 cycles of HfO 2) instead of

multiple, alternating layers (e.g. 1 cycle of Al2O3 followed by 1 cycle of HfO 2, repeated

30 times) [106-108]. Both Pd-Au (50-220 nm, labeled “p”) and Cr-Au (22-200 nm,

labeled “c”) contacts were deposited on each of the wafers and each wafer received a 200

°C, 1 hour, N2 PMA using the probe station wafer chuck heating system following initial

characterization. Table 4.1 summarizes the two wafers. Three additional wafers without

gate contacts, summarized in Table 4.2, were prepared for XPS characterization: one

Al2O3-InAs wafer, one HfO2-InAs wafer, and one bare InAs wafer used for reference

measurements.

156

TABLE 4.1

MATRIX OF BILAYER-OXIDE-INAS MOS CAPACITOR PREPARATION

DEPENDENCES IN THE SECOND GROWTH SET

Pretreatment Layer 1 (300 °C, 10 cycles)

Layer 2 (100 °C, 50 cycles)

Wafer BHF Al2O3 HfO2 HfO2

14 × × × 15 × × ×

Each wafer has Pd-Au (labeled “p”) and Cr-Au (labeled “c”) contacts. Annealed wafers are labeled “a” and wafers without anneal are labeled “n” for not-annealed.

TABLE 4.2

MATRIX OF OXIDE PREPARATION DEPENDENCES IN THE SECOND XPS

WAFER SET

Oxide

Wafer none Al2O3 HfO2

X10 × X11 × X12 ×

Wafers are pretreated with HF. Oxides are grown at 250 °C using 25 ALD cycles.

157

4.2 Bilayer HfO2-Al2O3-InAs MOS capacitors

The bilayer approach seeks to combine the low leakage current offered by Al2O3-

based MOS devices with the high dielectric constant (and thus, lower CET) offered by

HfO2-based devices [106-108]. To study the impact of the Al2O3 layer in HfO2-Al2O3-

InAs capacitors, J-V and C-V data from wafers with (wafer 14) and without (wafer 8) the

Al2O3 layers were compared. The HfO 2 layers in each of these wafers are similar, the

only variation being a 20 °C difference in growth temperature (wafer 8: 80 °C, wafer 14:

100 °C). Aside from the small variation in HfO 2 layer processing, the pretreatments are

different: wafer 8 had HCl pretreatment while wafer 14 had BHF pretreatment.

Therefore, it is necessary to establish the role that this variation plays in any observed

differences in device performance. This is done with a comparison between wafers 2 and

5 which have identically-grown HfO2 films, but HCl and BHF pretreatments,

respectively. Further confirmation of the role of Al2O3 in device performance

improvement comes with a comparison of wafers 14 and 15, grown with the same

pretreatment, temperature, and cycle recipe with the first ten cycles being Al2O3 and

HfO2, respectively.

4.2.1 Leakage current and interface trap reduction by inclusion of Al2O3

For a fair evaluation of gate dielectric materials, comparisons should be made

between films with equal CETs. For oxides with the same dielectric constant, this means

equal physical thickness, however, for materials with different dielectric constants, the

physical thicknesses should be scaled by the k values. In the case of wafers 8 and 14, a

direct comparison of CET is made with C-V measurements. Figure 4.1 compares the 1

MHz C-V curves of wafers 8pn and 14pn, and establishes that, while 8pn does not have

158

an Al2O3 layer and 14pn does, the CETs differ by only 0.01 nm. Despite the negligble

apparent difference in CET, the leakage current, shown in Figure 4.2, is lower in the

HfO2-Al2O3-InAs device by two orders of magnitude.

After the samples are subjected to a 200 °C, 1 hour PMA in N2, the situation

changes. The CET difference between wafers 8pa and 14pa calculated from the C-V

curves shown in Figure 4.3 increases to 0.1 nm. While at low bias, the wafer with the

Al2O3 layer (wafer 14pa) has lower leakage current, the differential resistance is also

lower, and thus at higher bias, wafer 14pa has higher current than the wafer without the

Al2O3 layer (8pa), Figure 4.4.

0

0.4

0.8

1.2

1.6

-1 0 1

Cap

acita

nce

(µF/

cm2 )

Gate Voltage (V)

HfO2-InAs

HfO2-Al

2O

3-InAs

1 MHz

EOT = 2.32 nm

2.33 nm

Au-Ti-high-k-InAswafers 8pn and 14pn

8pn: HCl (18.5%) pretreatment, 14pn: BHFAl

2O

3: 300 °C, 10 ALD cycles

HfO2: 80-100 °C, 50 ALD cycles

no PMA

35 × 35 µm2

Figure 4.1 Capacitance-voltage characteristic of wafers 8pn and 14pn, HfO2-InAs (red) and HfO 2-Al2O3-InAs (blue) MOS capacitors, measured at 1 MHz.

159

10-10

10-9

10-8

10-7

10-6

10-5

-1 0 1

Cur

rent

Den

sity

(A

/cm

2 )

Gate Voltage (V)

HfO2-InAs

HfO2-Al

2O

3-InAs

Au-Ti-high-k-InAswafers 8pn and 14pn

8pn: HCl (18.5%) pretreatment, 14pn: BHF

Al2O

3: 300 °C, 10 ALD cycles

HfO2: 80-100 °C, 50 ALD cycles

no PMA35 × 35 µm2

Figure 4.2 Current-density-voltage characteristics of wafers 8pn and 14pn, HfO2-InAs (red) and HfO2-Al2O3-InAs (blue) MOS capacitors.

0

0.4

0.8

1.2

1.6

-1 0 1

Cap

acita

nce

(µF/

cm2 )

Gate Voltage (V)

HfO2-InAs

HfO2-Al

2O

3-InAs

1 MHz

EOT = 2.35 nm

2.45 nm

Au-Ti-high-k-InAswafers 8pa and 14pa

8pa: HCl (18.5%) pretreatment, 14pa: BHFAl

2O

3: 300 °C, 10 ALD cycles

HfO2: 80-100 °C, 50 ALD cycles

200 °C, 1 hour, N2 PMA

35 × 35 µm2

Figure 4.3 Capacitance-voltage characteristic of wafers 8pa and 14 pa, HfO2-InAs (red) and HfO 2-Al2O3-InAs (blue) MOS capacitors, measured at 1 MHz after 200 °C, 1 hour, N2 PMA.

160

10-9

10-8

10-7

10-6

10-5

10-4

10-3

-1 0 1

Cur

rent

Den

sity

(A

/cm

2 )

Gate Voltage (V)

HfO2-InAs

Al2O

3-HfO

2-InAsAu-Ti-high-k-InAs

wafers 8pa and 14pa8pa: HCl (18.5%) pretreatment, 14pa: BHF

Al2O

3: 300 °C, 10 ALD cycles

HfO2: 80-100 °C, 50 ALD cycles

200 °C, 1 hour, N2 PMA

35 × 35 µm2

Figure 4.4 Current-density-voltage characteristics of wafers 8pa and 14 pa, HfO2-InAs (red) and HfO 2-Al2O3-InAs (blue) MOS capacitors, measured after 200 °C, 1 hour, N2 PMA.

The direct tunneling current model described in Chapter 2 provides insight into

what may cause the change in slope of the post-anneal HfO2-Al2O3-InAs J-V curve. The

modeling reveals that the slope of a log(J)-V curve is mostly dependent on φB while the

magnitude depends on both φB and the oxide thickness. The J-V data of Figure 4.2

suggests that prior to PMA, the HfO 2 has a lower barrier and is thinner than the HfO 2-

Al2O3 structure. After PMA, the HfO2 barrier remains the same with an increased

thickness while the HfO2-Al2O3 tunneling barrier decreases substantially, coupled with an

increase in thickness, to produce the J-V curves of Figure 4.4.

Figure 4.1 and Figure 4.3 show dramatic improvement of the MOS capacitor

device characteristics of both structures after PMA in terms of stretch-out, flatband

voltage shift, and inversion-regime capacitance. Figure 4.5 contains bidirectional C-V

sweeps of HfO2-InAs and HfO2-Al2O3-InAs MOS capacitors before and after PMA.

Significant reduction in the HfO 2-Al2O3-InAs bidirectional sweep hysteresis is seen while

161

the large flatband voltage shift in the HfO 2-InAs device prior to anneal prevents its

hysteresis from being accurately determined in the -1 to +1 V measurement range.

0.6

0.8

1

1.2

1.4

1.6

1.8

-1.5 -1 -0.5 0 0.5 1 1.5

Cap

acita

nce

(µF

/cm

2)

Gate Voltage (V)

HfO2-InAs

HfO2-Al

2O

3-InAs1 MHz

Au-Ti-high-k-InAswafers 8p and 14p

8p: HCl pretreatment, 14p: BHFAl

2O

3: 300 °C, 10 ALD cycles

HfO2: 80-100 °C, 50 ALD cycles

35 × 35 µm2

no PMA

(a)

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

-1.5 -1 -0.5 0 0.5 1 1.5

Cap

acita

nce

(µF

/cm

2)

Gate Voltage (V)

HfO2-InAs

HfO2-Al

2O

3-InAs

1 MHz

200 °C, 1 hour, N2 PMA

(b)

Figure 4.5 Bidirectional C-V sweeps of wafers 8p and 14p, HfO 2-InAs (red) and HfO 2-Al2O3-InAs (blue) MOS capacitors, at 1 MHz before (a) and after (b) PMA.

While both HfO 2-InAs and HfO2-Al2O3-InAs devices are improved by PMA, it is

the latter device which exhibits the lowest hysteresis and highest inversion-regime

162

capacitance. All of these improvements (reduced flatband voltage shift, hysteresis, and

stretch-out) are the result of a reduction in interface trap density. Using low temperature

Terman measurements, the improvement of the HfO 2-Al2O3 device in terms of interface

trap density is quantified. The low temperature C-V measurements in Figure 4.6 reveal a

slightly steeper slope in the HfO 2-Al2O3-InAs device, indicative a lower interface trap

density. As shown in Figure 4.7, the interface trap density 80 meV from the conduction

band edge is more than 3× lower in the HfO 2-Al2O3-InAs device.

0

0.4

0.8

1.2

-2 -1 0 1

Cap

acita

nce

(µF

/cm

2 )

Gate Voltage (V)

10 kHz77 K

HfO2-InAs HfO

2-Al

2O

3-InAs

Au-Ti-high-k-InAswafers 8pa and 14pa

8pa: HCl pretreatment, 14pa: BHFAl

2O

3: 300 °C, 10 ALD cycles

HfO2: 80-100 °C, 50 ALD cycles

200 °C, 1 hour, N2 PMA

85 × 85 µm2

Figure 4.6 Capacitance-voltage curves of wafers 8pa and 14pa, HfO 2-InAs (red) and HfO 2-Al2O3-InAs (blue) MOS capacitors, taken at 10 kHz at LN2 temperature.

163

1013

1014

1015

1016

-0.04 0 0.04 0.08 0.12

DIT

(cm

-2-e

V-1

)

EC - E

T (eV)

HfO2-InAs

HfO2-Al

2O

3-InAs

Au-Ti-high-k-InAswafers 8pa and 14pa

8pa: HCl pretreatment, 14pa: BHFAl

2O

3: 300 °C, 10 ALD cycles

HfO2: 80-100 °C, 50 ALD cycles

200 °C, 1 hour, N2 PMA

85 × 85 µm2

Figure 4.7 Interface trap density versus position in bandgap for wafers 8pa and 14pa, HfO 2-InAs (red) and HfO 2-Al2O3-InAs (blue) MOS capacitors, as measured by the low temperature Terman method.

4.2.2 Role of HCl and BHF pretreatments in higk-k-InAs device performance

The HfO2-InAs and HfO2-Al2O3-InAs MOS devices compared in the previous

section have HCl and BHF pretreatments, respectively. It is therefore necessary to

establish the effects pretreatment has on device properties to isolate these effects from

those of the Al2O3 interlayer. This is done for all three pretreatments used in this work in

Section 3.7. Here, particular attention is paid to the HCl and BHF pretreatments. Wafers

2n and 5n each have 50-cycle, 200 °C HfO 2 films, Ti-Au contacts, and are unannealed.

Wafer 2n has HCl pretreatment and 5n has BHF pretreatment. The role of pretreatment in

device characteristics is determined through comparison of these two wafers.

Figure 4.8 contains the room (a) and low (b) temperature C-V characteristics of

devices from wafers 2n and 5n. In terms of capacitance, flatband voltage, and stretch-out,

the films are quite similar at room temperature. However, the accumulation capacitance is

significantly lower in the BHF device at low temperature. This accumulation capacitance

164

dispersion is the result of a high density of interface traps near the conduction band edge.

Figure 4.9 compares the interface trap densities of the HCl- and BHF-pretreated devices

as determined by the low temperature Terman method. At the conduction band edge, the

interface trap density is 17× higher in the BHF device than in the HCl device.

The accumulation capacitances of the devices in Figure 4.8 at room and low

temperature, and the effect of interface traps are explained as follows. At room

temperature, the measured accumulation capacitance of both the BHF and HCl devices is

very near the oxide capacitance, which, ideally, is the same for both devices since the

film deposition conditions are the same. This is because at room temperature, the

combined parallel contribution of the semiconductor and interface trap capacitances is

much higher than the oxide capacitance. In both devices, this combined semiconductor-

interface-trap capacitance is due mostly to interface traps at room temperature.

At low temperature, the response of the interface traps slows down and they are

unable to respond to the AC measurement signal and do not to contribute to the measured

differential capacitance, leaving the semiconductor capacitance to dominate the

semiconductor- interface-trap capacitance. Interface traps can respond to the applied DC

signal however, and affect the semiconductor capacitance by influencing the

semiconductor surface potential. Interface traps partially screen the semiconductor

surface from the gate potential, thus reducing the semiconductor capacitance from its

ideal, interface-trap-free value.

165

0

0.5

1

1.5

2

-4 -2 0 2 4

Cap

acita

nce

(µF

/cm

2)

Gate Voltage (V)

300 K

BHFHCl

10 kHz

Au-Ti-HfO2-InAs

wafers 2n and 5n200 °C growth temperature

75 ALD cyclesno PMA

85 × 85 µm2

(a)

0

0.5

1

1.5

2

-4 -2 0 2 4Gate Voltage (V)

77 K

Cap

acita

nce

(µF

/cm

2 )

BHF

HCl

10 kHz

(b)

Figure 4.8 Room (a) and low (b) temperature 10 kHz C-V curves of wafers 2n and 5n, 200 °C, 50-cycle HfO 2 devices with HCl and BHF InAs pretreatments, respectively.

In the HCl device, this interface trap density is low enough to still allow a

semiconductor capacitance several times larger than the oxide capacitance and thus, the

measured accumulation capacitance is not significantly lower at low temperature. In the

BHF device, however, the interface traps reduce the semiconductor capacitance to a level

166

roughly equal to that of the oxide capacitance, and as a result, the measured accumulation

capacitance is reduced significantly at low temperature. Despite the increased trap density

resulting from the BHF pretreatment, HfO 2-Al2O3-InAs MOS capacitors still exhibit

superior C-V behavior compared to HCl-pretreated HfO 2-InAs devices.

1013

1014

1015

1016

0 0.1 0.2 0.3

DIT

(cm

-2eV

-1)

EC - E

T (eV)

Au-Ti-HfO2-InAs

wafers 2n and 5n200 °C growth temperature

75 ALD cyclesno PMA

85 × 85 µm2

BHF

HCl

DIT

calculated using the Terman method and 77 K data

Figure 4.9 Interface trap density versus position in bandgap as measured by the low-temperature Terman method for wafers 2n and 5n, 200 °C, 50-cycle HfO2 devices with HCl and BHF InAs pretreatments, respectively.

4.2.3 Role of interfacial growth temperature and precursor in higk-k-InAs device

performance

Section 4.2.1 compares the characteristics of devices with and without Al2O3

layers and shows that high-k-InAs capacitors of comparable CET have 3× lower interface

trap density when Al2O3 is grown at the InAs surface, followed by HfO 2, than when only

HfO2 is grown. In the two devices compared, from wafers 8pa (HfO 2-InAs) and 14pa

(HfO2-Al2O3-InAs), the HfO2 is grown at low temperature (= 100 °C) for 50 cycles. The

primary difference between the two devices is that dielectric film growth in wafer 14pa

begins with 10 cycles of the Al2O3 precursor at 300 °C and ends with the HfO 2 precursor,

167

while wafer 8pa begins and ends with the HfO 2 precursor. In addition to the different

interfacial precursors, however, are the different interfacial growth temperatures. The

interfacial material of wafer 8pa is grown at 80 °C while the interfacial material of wafer

14pa is grown at 300 °C. Because both the interfacial growth precursor and temperature

differ in these wafers, the effects of precursor and temperature must be isolated.

Figure 4.10 compares the interface trap densities of wafers 8pa and 9pa, HfO 2-

InAs capacitors grown with 50 cycles at 80 and 250 °C, respectively, as measured by the

low temperature Terman method. As seen in the figure, 100 meV from the conduction

band edge, HfO 2 films grown at 250 °C have significantly lower DIT than films grown at

80 °C. This result suggests that the improved DIT in the HfO2-Al2O3-InAs device over the

HfO2-InAs might actually be due to the differing interfacial growth temperature and not

the interfacial precursor.

1013

1014

1015

1016

0 0.1 0.2

DIT

(cm

-2eV

-1)

EC - E

T (eV)

80 °C

250 °C

Au-Ti-HfO2-InAs

wafers 8pa and 9paHCl (18.5%) pretreatment

50 ALD cycles200 °C, 1 hour, N

2 PMA

85 × 85 µm2

Figure 4.10 Interface trap density versus position in bandgap as measured by the low-temperature Terman method for wafers 8pa and 9pa, 50-cycle HfO2-InAs capacitors grown at 80 and 250 °C, respectively.

168

While, as Figure 4.10 shows, increased growth temperature reduces interface trap

density, increased growth temperature alone cannot explain the lowered interface trap

density in the HfO 2-Al2O3-InAs device over HfO 2-InAs device. Figure 4.11 compares the

C-V curves of devices from wafers 14p and 15p before (a) and after (b) a 200 °C, 1 hour,

N2 PMA. Wafer 14p is the previously-described HfO 2-Al2O3-InAs wafer. Wafer 15p is

grown with 10 cycles of HfO 2 at 300 °C at the InAs surface, followed by 50 cycles of

HfO2 at 100 °C. The only difference between the growths of wafers 14p and 15p is the

precursor used during the first 10 cycles. The HfO 2-only device has a higher capacitance

than the HfO2-Al2O3 device, which is expected given that HfO 2 has a higher dielectric

constant than Al2O3. However, the accumulation-regime frequency dispersion is much

higher in the HfO 2-only device, an indication of higher interface trap density. This

dispersion improves near flatband after PMA, however, it is still several times higher

than the HfO2-Al2O3 device. The data shows that increased temperature and the Al2O3

precursor play a role in improving high-k-InAs interface trap densities.

169

0.5

1

1.5

2

2.5

3

-1.5 -1 -0.5 0 0.5 1 1.5

Cap

acita

nce

(µF/

cm2 )

Gate Voltage (V)

10 kHz

1 MHz

10 kHz

1 MHz

HfO2-HfO

2

HfO2-Al

2O

3

wafers 14pn and 15pn

35 × 35 µm2

(a)

0.5

1

1.5

2

2.5

3

-1.5 -1 -0.5 0 0.5 1 1.5

Cap

acita

nce

(µF/

cm2 )

Gate Voltage (V)

10 kHz

1 MHz

10 kHz

1 MHz

HfO2-HfO

2

HfO2-Al

2O

3

wafers 14pa and 15pa

35 × 35 µm2

(b)

Figure 4.11 Capacitance-voltage curves of wafers 14p and 15p measured at 10 kHz and 1 MHz before (a) and after (b) 200 °C, 1 hour, N2 PMA. Wafer 14p was grown with 10 cycles of Al2O3 at 300 °C followed by 50 cycles of HfO 2 grown at 100 °C. Wafer 15p was grown with 10 cycles of HfO2 at 300 °C followed by 50 cycles of HfO 2 grown at 100 °C.

170

4.3 XPS studies of Al2O3 and HfO2 ALD processes

High-k-InAs MOS capacitors with Al2O3 grown at the interface have lower

interface trap density, hysteresis, and accumulation-regime frequency dispersion than

InAs capacitors with HfO 2 grown at the interface. The As (a) and In (b) 3d XPS spectra

of as- is InAs, InAs with ALD-grown Al2O3, and InAs with ALD-grown HfO2 of Figure

4.12 reveal a possible chemical explanation. Figure 4.12(a) shows that an as- is InAs

sample (pretreated with BHF and not exposed to ALD growth) has a large peak

associated with the As-O binding energy, indicative of a large presence of AsOX. XPS

spectra for the samples exposed to the Al2O3 and HfO2 ALD processes have no such

peak, suggesting that something in the ALD process (e.g. the elevated substrate

temperature or exposure to the metal precursor) is removing the native AsOX. The In 3d

XPS spectra [Figure 4.12 (b)] tell a similar story for InOX for the Al2O3 ALD process;

however, such is not the case for the HfO 2 ALD process. The XPS spectra show that the

In-O peak is unchanged from the as- is case. Here, a case exists in which two samples

were exposed to the elevated temperature of the ALD growth process, yet one has a

reduced presence of InOX and one does not. The only difference in the preparation of the

two samples is the ALD precursor. In the case of the Al2O3 sample, it is TMA; in the case

of the HfO2, it is TDMA-Hf. The TMA precursor more effectively eliminates InOX

present at the InAs surface – a possible source of interface traps detected by Terman

measurements and the bright interfacial layer in TEM images of HfO 2-InAs interfaces.

171

373941434547

Inte

nsity

(ar

b. u

nits

)

Binding Energy (eV)

InAs (as is)

afterAl

2O

3

HfO2

As-InAs-In

As-O

Eph

= 170 eV HfO2-InAs

wafers X10, X11, and X12As 3d

(a)

442444446Binding Energy (eV)

In-O In-As

Inte

nsity

(arb

. uni

ts)

Eph

= 890 eV

In 3d

(b)

Figure 4.12 Arsenic (a) and indium (b) 3d XPS spectra for wafers X10, X11, and X12, as- is InAs (red), InAs with ALD-grown HfO2 (blue), and InAs with ALD-grown Al2O3 (green), respectively.

4.4 Summary

Bilayer metal-high-k-InAs MOS capacitors were studied by J-V, C-V, and XPS

characterization. InAs-based MOS capacitors of comparable CET had two-orders-of-

172

magnitude lower leakage current density in the HfO 2-Al2O3 versus the HfO2-only case

before 200 °C, 1 hour PMA. This changed following PMA, with the HfO 2-Al2O3-InAs

structure having lower current at low gate biases than the HfO2-InAs structure but higher

current at higher biases. Following PMA, the structures were also superior to the HfO2-

only structures in terms of inversion-regime capacitance, hysteresis, accumulation-regime

frequency dispersion, and interface trap density.

In addition to the use of the Al2O3 precursor, increased growth temperature can

also reduce interface trap densities. InAs MOS capacitors with HfO 2 films grown at 250

°C had three times lower DIT than ones with films grown at 80 °C. From this result, it

may be the case that the increased interfacial growth temperature and not the interfacial

growth material was responsible for the interface trap density differences between the

HfO2-Al2O3-InAs and HfO2-InAs capacitors compared in Section 4.2. However, devices

on wafers grown at the same temperatures with either HfO 2 or Al2O3 grown at the

interface showed significantly less frequency dispersion in the Al2O3-interface devices

than the HfO2-interface devices, establishing interfacial growth material as a primary

factor in interface properties.

XPS characterization further supported the role of interfacial growth precursor in

high-k-InAs interfaces. XPS showed that while AsOX was effectively eliminated by both

HfO2 and Al2O3 ALD processes, only the Al2O3 ALD process reduced InOX, which is a

potential source of interface traps.

173

CHAPTER 5:

CONSIDERATIONS FOR HIGH-K-INAS MOS GATE STACKS

The continued scaling of CMOS technology produces ever- increasing demands

on MOSFETs, demands that motivate investigations into metal gates, high-k gate

dielectrics, and III-V channels. There are many questions that need to be answered to

determine if an oxide film is a suitable MOSFET gate dielectric. Can atomically-uniform,

nanometer-thick high-k films be produced with monolayer precision? What are the

leakage current mechanisms and can the leakage current density be held below 100/LG

nA/µm2, where LG is the gate length in µm?1 Can the dielectric support large electric

fields (1 V/nm) without breaking down? Does it form a smooth, charge-free interface that

does not pin the semiconductor surface potential? Is the film thermodynamically stable?

Some of these questions are addressed for InAs-based gate stacks in this chapter, which

compares the results of this work to other high-k-III-V MOS work and ITRS

requirements. Specifically, leakage current, EOT, and DIT are discussed; however, a

number of other considerations must be made for high-k-III-V MOS gate stacks including

thermal stability, effect on carrier mobility, ability to control threshold voltage, and

dielectric strength. The reader is referred to [52, 92, 109] for a discussion of these issues.

1 This requirement assumes that the off current of a logic device must be 104× lower than a full channel current of 1000 µA/µm.

174

5.1 Scaling considerations for metal-high-k-InAs MOS gate stacks

The “scalability,” i.e. the ability to meet MOSFET gate stack requirements as gate

length is reduced, of metal-high-k-InAs is assessed by comparing data from this work to

the high-performance targets in the 2008 update of the ITRS [11] front-end processes

section. Two of these requirements, gate dielectric leakage and equivalent physical oxide

thickness, are discussed in this section.

5.1.1 High-performance gate dielectric leakage current

The ITRS specifies a maximum tolerable gate dielectric leakage current at 100 °C

for high-performance, metal-gate, bulk (planar) MOSFETs for each technology node

(physical gate length) through the year 2016. Also specified at each node is the maximum

gate dielectric EOT. These two requirements are plotted together along with data from all

of the metal-high-k-InAs wafers fabricated in this work in Figure 5.1. While the ITRS

requirement is specified in terms of EOT, which excludes quantum-mechanical

semiconductor effects (e.g. location of the semiconductor charge centroid away from the

oxide-semiconductor interface), the data in Figure 5.1 from this work is given in terms

CET, which does include these effects, and represents a worst-case scenario for a given

device since the EOT never exceeds the CET. For this work, the current density is

measured at room temperature with VG = +1 V, which represents the maximum projected

MOSFET operating voltage. Given that direct tunneling is the primary leakage

mechanism for the thinner (= 50 ALD cycles) oxides fabricated in this work (see Figure

3.25), the 100 °C leakage current at VG = +1 V is not expected to differ much from the

room temperature value (see Figure 2.20).

175

10-9

10-7

10-5

10-3

10-1

101

103

0 1 2 3

J(V

G =

+1

V)

(A/c

m2 )

CET or EOT (nm)

metal-high-k-InAswafers 1 - 15

ITRS high-performance,metal-gate, bulk MOSFET

Figure 5.1 Leakage current density measured at VG = +1 V vs. CET measured at 10 kHz and VG = +1 V for all high-k-InAs MOS capacitor heterostructures fabricated in this work (red) and ITRS targets for high-performance, bulk, metal-gate MOSFETs for years 2009 – 2016 (LG = 27 – 14 nm) (blue) from [11].

In general, the gate leakage in wafers 1 – 15, metal-high-k-InAs MOS devices,

scales exponentially with CET, consistent with direct tunneling. ITRS leakage current

requirements are comfortably met down to an equivalent thickness of 0.76 nm. The

dashed lines in Figure 5.1 are used to project how metal-high-k-InAs leakage might scale

below equivalent thicknesses of 0.76 nm. Metal-high-k-InAs is likely to meet ITRS high-

performance, metal-gate, bulk MOSFET leakage current requirements through 2016 (LG

= 14 nm), provided the gate dielectric equivalent thickness can be scaled to 0.5 nm.

Yeo et al. [110] have defined a scaling figure-of-merit, f, related to the slope of

the log(J)-CET/EOT plot, given in units of eV1/2 by

( ) kmf BOX2/1* φ= , (5.1)

176

where *OXm is the oxide tunneling effective mass given in units of m0, φB is the oxide-

semiconductor barrier height in eV, and k is the relative dielectric constant of the oxide.

This figure-of-merit is based on an approximate model for direct tunneling. The

exponential term in the expression from which the scaling figure-of-merit is based,

( )

×− EOT

328

exp~2/1

0* kmm

hq

J BOX φπ

, (5.2)

can be manipulated to calculate an experimental f from the slope of Figure 5.1,

0283

qmSh

fπ−

= , (5.3)

where S is the slope of the log(J)-CET/EOT plot. From the slope of the left-most dashed

line in Figure 5.1, f is found to be 3.3 eV1/2, short of the theoretical value of 13.8 eV1/2

calculated from (5.1) using a barrier height of 2.4 eV, effective tunneling mass of 0.15,

and relative dielectric constant of 23.

The J-CET data from wafers 1 – 15 is plotted against other MOS work in Figure

5.2. The plot contains data from various combinations of deposition techniques, gate

dielectrics, and semiconductors. The published data is given in terms of either CET or

EOT and at differing values of gate bias. The processing and characterization details of

the work plotted in Figure 5.2 are given in Table 5.1. In terms of leakage current, this

work compares favorably to other high-k-III-V MOS device work.

177

10-9

10-7

10-5

10-3

10-1

101

0 1 2 3 4

this work

Ok MEE 86

Lee

Koveshnikov APL 88

Cheng

Shahrjerdi, Kim, Kim

Zhu

ZhangPark

Lee JES 153

Kim

Choi

Dalapati

Koveshnikov APL 92

Ok APL 92

Saito

Saito Thermal OX

J (A

/cm

2 )

CET or EOT (nm)

1: high-k-InAs (this work)

2: TaN-HfO2-Si-p-GaAs

3: Au-Ti-HfO2-n-InGaAs-InP

4: TaN-HfO2-Si-n-GaAs

5: Pt-Gd2O

3-n-GaAs

6: HfO2-Si/Ge-n-GaAs

7: HfO2-AlON-n-GaAs

8: HfSiO-n-GaAs

9: TiO2-HfO

2-n-GaAs

10: TiO2-p-GaAs

11: TaN-HfO2-Ge-n-GaAs

12: TaN-HfO2-Si

13: TaN-high-k-GaAs

14: ZrO2-InGaAs

15: TaN-HfO2-n-InGaAs-n-InP

16: Al-TiN-HfO2-Si

17: SiO2-Si

Figure 5.2 Leakage current density vs. CET or EOT for this work and other MOS work. Citations and structure detail are given in Table 5.1.

178

TABLE 5.1

PROCESSING AND CHARACTERIZATION DETAILS OF MOS DEVICES

PLOTTED IN FIGURE 5.2

Legend #

Materials Dielectric deposition

method

Equivalent thickness

type

Gate bias (V)

First author Year Reference

1 Au-(Ti,Pd)-(HfO2,Al2O3)-n-InAs

ALD CET +1 Wheeler 2009 this work

2 TaN-HfO2-Si-p-GaAs magnetron sputtering EOT VFB – 1 Ok 2009 [100]

3 Au-Ti-HfO2-n-InGaAs-InP

ALD CET VFB + 1 Lee 2008 [111]

4 TaN-HfO2-Si-n-GaAs PVD CET VFB + 1 Koveshnikov 2006 [112] 5 Pt-Gd2O3-n-GaAs PVD CET VFB + 1 Cheng 2008 [113]

6 HfO2-(Si,Ge)-n-GaAs VFB + 1 Shahrjerdi

Kim Kim

2006 2006 2007

[114] [115] [116]

7 HfO2-AlON-n-GaAs VFB + 1 Zhu 2006 [117] 8 HfSiO-n-GaAs VFB + 1.5 Zhang 2006 [118] 9 TiO2-HfO2-n-GaAs VFB + 1 Park 2007 [119] 10 TiO2-p-GaAs VFB – 1 Lee 2006 [120]

11 TaN-HfO2-Ge-n-GaAs DC sputtering CET VFB + 1 Kim 2006 [121]

12 TaN-HfO2-Si DC sputtering

CET VFB + 1 Choi 2005 [122]

13 TaN-

(Al2O3,HfO2,HfAlO)-(p,n)-GaAs

ALD EOT VFB ± 1 Dalapati 2007 [123]

14 ZrO2-InGaAs ALD CET VFB + 1 Koveshnikov 2008 [124]

15 TaN-HfO2-n-InGaAs-n-InP

magnetron sputtering CET VFB + 1 Ok 2008 [125]

16 Al-TiN-HfO2-Si ECR sputtering

CET +1 Saito 2004 [126]

17 SiO2-Si thermal oxidation CET +1 Saito 2004 [126]

179

5.1.2 High-performance gate dielectric equivalent thickness

In addition to bulk MOSFET devices, the ITRS also specifies EOT requirements

for other high-performance, metal-gate device geometries such as fully-depleted silicon-

on- insulator and multi-gate. The use of each of these geometries relaxes the gate

dielectric EOT requirements from the bulk case. The required EOT is plotted in Figure

5.3 as a function of physical gate length for high-performance, metal-gate, bulk (red),

fully-depleted silicon-on- insulator (blue), and multi-gate (green) devices.

0.4

0.6

0.8

1

5 10 15 20 25 30

EO

T (

nm)

LG (nm)

bulk

fully-depleted silicon-on-insulator

20092011201420172022

multi-gate

ITRS requirements forhigh-performance, metal-gate

MOSFET gate dielectrics

Figure 5.3 ITRS gate dielectric EOT requirement vs. physical gate length for high-performance, metal-gate bulk (red), fully-depleted silicon-on-insulator (blue), and multi-gate (green) MOSFETs from [11].

Depending on device geometry and technology node, gate dielectric EOTs as low

as 0.5 nm are required. Figure 5.4 contains the EOT of HfO 2 films on InAs as a function

of physical oxide thickness, tOX, calculated using pre- (blue) and post- (red) PMA

dielectric constants for HfO2. The solid lines in the figure include a contribution to EOT

due to an unintentional interlayer (IL) between the InAs and HfO 2 layers. The EOT is

calculated using

180

ILOXOX

SiO t CETEOT 2 +=ε

ε, (5.4)

where CETIL is the CET of the IL. Both eOX and CETIL for pre- and post-PMA HfO2 films

are calculated in Figure 3.33 and listed in the Figure 5.4 table inset. The PMA considered

in this plot is the 400 °C, 2 min., N2 PMA applied to wafers in the first wafer matrix. The

dashed lines in Figure 5.4 do not include the interlayer contribution (CETIL = 0).

0

1

2

0 2 4 6 8 10

EO

T (

nm)

tOX

(nm)

30ALD

cycles

40 50 75 125

ILOXOX

SiO t CETEOT 2 +=ε

ε

without IL

with IL

ε ε

0.2416PMA

0.8423no PMA

CETIL (nm)OX ( 0)

0.2416PMA

0.8423no PMA

CETIL (nm)OX ( 0)

IL: interlayerPMA: 400 °C, 2 min., N

2

Figure 5.4 EOT vs. physical HfO 2 thickness. EOT is calculated with (solid lines) and without (dashed lines) unintentional interlayer (IL) thickness for pre- (blue) and post- (red) PMA devices. IL thickness and dielectric constant for pre- and post-PMA devices calculated from wafers 2, 6, and 7, Au-Ti-HfO2-InAs devices grown using 200 °C and 50, 75, and 125 cycles, respectively, shown in Figure 3.33. PMA is at 400 °C for 2 min. in N2.

Where the ALD cycles used in this work are expected to fall on the curves in

Figure 5.4 is represented by the square symbols and is based off an ALD growth rate of

0.7 nm/cycle (see Figure 3.19). In the ideal, IL-free case, maximum EOT scaling is

achieved with unannealed HfO 2 because of the larger dielectric constant. However, in

practice, lower EOTs are achieved with annealed HfO 2, despite the lower dielectric

181

constant, because of a reduction in IL CET. The IL CET sets the minimum achievable

equivalent thickness for a particular set of processing conditions. For ALD-deposited,

annealed HfO 2 films on InAs grown at 200 °C, the minimum achievable EOT is 0.24 nm,

below the lowest ITRS projection for gate dielectric equivalent thickness.

5.2 Interface requirements for high-k-based MOS gate stacks

The ITRS specifies a total allowable interfacial charge (in cm-2) in high-k MOS

gate stacks. This specification applies to all device geometries and applications and is

plotted in Figure 5.5 as a function of physical gate length. Over the projected years, the

allowable charge remains relatively constant, ranging from 1.4 – 2.2 × 1011 cm-2. These

values assume that all oxide charge is located at the oxide-semiconductor interface (i.e.

no bulk oxide charge).

1.4

1.8

2.2

5 10 15 20 25 30Inte

rfac

e C

harg

e (×

1011

cm

-2)

LG (nm)

20092011201420172022

ITRS requirements forMOSFET gate dielectrics

Figure 5.5 ITRS total interface charge requirement vs. physical gate length for MOSFET gate dielectrics from [11]. All charge is assumed to be at the gate-dielectric-semiconductor interface (i.e. no bulk oxide charge).

182

The total interfacial charge is calculated for wafer 2n, an unannealed Au-Ti-HfO2-

InAs device grown at 200 °C using 75 ALD cycles and HCl pretreatment, by integrating

the DIT found using the Terman method over the InAs bandgap, shown in Figure 5.6. For

wafer 2n, the total interfacial charge is 2.7 × 1013 cm-2, over two orders-of-magnitude

higher than the maximum allowable interface charge. Given that high-k-III-V MOS

interface trap densities in the low-1011 to low-1012 cm-2eV-1 are routinely achieved [52],

this is an obvious area for improvement.

1013

1014

1015

1016

0 0.1 0.2 0.3

DIT

(cm

-2eV

-1)

EC - E

T (eV)

Au-Ti-HfO2-InAs

wafer 2nHCl pretreatment

200 °C growth temperature75 ALD cycles

no PMA

85 × 85 µm2

DIT

calculated using the Terman method and 77 K data

total charge = 2.7 × 1013 cm-2

Figure 5.6 Interface trap density versus position in bandgap as measured by the low-temperature Terman method for unannealed wafer 2n, Au-Ti-HfO2-InAs grown at 200 °C with 50 cycles and HCl pretreatment. The trap density is integrated over the bandgap to calculate the total interface charge density.

While the total interface charge density in this work is well above ITRS

requirements, it should be noted that these requirements assume a Si MOSFET channel.

Ye [52] argues that while low DIT is necessary for III-V MOSFETs, below a certain level

of DIT, the physics of the bulk semiconductor become more important. Ye uses the

charge-neutrality level (CNL) model to explain all reported ALD III-V MOSFET device

183

results and shows that higher drain currents are achieved, despite higher trap densities, in

inversion-mode InGaAs than GaAs devices because the separation between the CNL and

conduction band minimum (CBM) is lower. This separation decreases as In content is

raised, reaching a minimum in InAs.

Ye makes the same argument from the perspective of band bending in strong

inversion. Assuming, at the onset strong inversion, that the semiconductor surface

potential is twice the bulk potential, the surface potential is given by

==

i

DBBS n

Nq

TkVV ln

22 . (5.5)

The surface potential required to reach strong inversion is reduced as the intrinsic carrier

concentration is increased. This explains why InGaAs MOSFETs outperform GaAs

MOSFETs, and why narrow-bandgap (high ni) semiconductor devices can tolerate higher

interface trap densities.

5.3 Summary

Metal-high-k-InAs MOS capacitor device results from this work were compared

to ITRS performance targets to assess their ability to serve as an MOS gate stack. The

capacitors were found to meet leakage current targets through the predicted range of bulk

devices and compared favorably to other high-k-III-V work. Annealed HfO 2 films on

InAs were shown to meet equivalent thickness scaling targets, based on the unintentional

IL thickness found from an equivalent-thickness-physical-thickness plot. Interface trap

densities were found to be well above the ITRS targets and remain an area for

improvement.

184

CHAPTER 6:

CONCLUSION

In this chapter, the work presented in this thesis is summarized and suggestions

for future research directions are made.

6.1 Summary

In this thesis, metal-high-k-InAs MOS capacitors formed by ALD were

fabricated, exploring different oxide film growth temperatures and thickness, InAs

pretreatments, gate contact metals, and PMAs. The modeling of MOS capacitors was

discussed, explaining the dependence of C-V and I-V data on physical device properties.

Device measurement was discussed, detailing equipment setup, calibration, and use and

exploring the dependence of C-V and I-V data on measurement equipment settings.

In both metal-HfO2-InAs and metal-HfO2-Al2O3-InAs MOS structures, device

characteristics were strongly dependent on measurement bias, temperature, and

frequency. These dependencies were used to calculate the oxide dielectric constant, CET,

EOT, hysteresis voltage shift, flatband voltage, frequency dispersion, interface trap

density, and other quantities of interest for capacitors formed using different processing

conditions. Measurements and calculations were compared to other III-V MOS work and

ITRS requirements to assess the viability of metal-high-k-InAs-based FETs.

185

It is shown that the metal-high-k-InAs system can meet ITRS performance targets

for high-performance, bulk MOSFET gate dielectric leakage current and equivalent

thickness through the year 2016 (14 nm physical gate length). Performance targets are

also met beyond 2016, during which time alternative device structures such as multi-gate

are anticipated. Oxide leakage current and thickness are important quantities for MOS

gate stack assessment; however, equally important to MOSFET device operation is the

ability to unpin the Fermi level at the gate-dielectric-semiconductor interface. This has

been the primary challenge of III-V MOS. In this work, strong evidence of Fermi level

unpinning is provided by the large capacitance modulation and light-dependence of

metal-high-k-InAs structures measured at low temperature; however, C-V stretch-out and

Terman method calculations suggest that further high-k-InAs interface improvement is

possible.

6.2 Suggestions for future research

While metal-high-k-InAs MOS gate stacks are able to meet ITRS requirements

for leakage current and EOT, reducing interface trap density remains a formidable

challenge. The incorporation of Al2O3 at the InAs interface produces better capacitors in

terms of inversion-regime capacitance, accumulation-regime capacitance frequency

dispersion, and hysteresis voltage shift (all likely the result of reduced interface trap

density). However, the inclusion of this layer (which has a lower dielectric constant than

HfO2) increases the overall EOT. A study in which the interface trap density of metal-

HfO2-Al2O3-InAs devices is measured as a function of Al2O3 thickness can determine the

minimum thickness of Al2O3 required to realize the benefit of the layer. This study can be

186

supported by a series of XPS measurements on HfO 2-Al2O3-InAs wafers in which the

Al2O3 layer is similarly scaled. These studies would seek to find an optimized metal-

HfO2-Al2O3-InAs structure in which EOT and DIT are minimized.

It is well known that surface preparation is critical to gate-dielectric-III-V

interface properties [127, 128]. While three chemical pretreatments are explored in this

work for HfO2-InAs interfaces, a similar study has not been conducted in this work for

Al2O3-InAs interfaces. A number of reports exist on InAs surface treatments including

sulfur- [102, 129] and HCl- [130] based approaches. Annealing is also shown to have a

substantial impact on MOS device properties in this work and by others [100, 102]. A

systematic study using Terman measurements on metal-HfO2-Al2O3-InAs devices in

which surface pretreatment and post-growth and post-metal anneals are varied would

determine the optimum pretreatment and anneal type, temperature and duration.

Once a metal-high-k-InAs fabrication process is found, with optimized Al2O3

layer, pretreatment, and anneal, the ultimate goal is to create an InAs MOSFET [20, 21,

35, 37, 57]. A metal-high-k-InAs-based MOSFET device allows the use of additional

characterization techniques. A device in which source and drain regions are formed by

ion implantation enables use of the split C-V technique [131, 132], which distinguishes

between electron and hole capacitance contributions and is commonly used to measure

carrier mobility. The structure also allows for an inversion-mode MOSFET to be tested,

enabling benchmarking of the high-k-InAs material system in terms of common FET

metrics such as drain current and transconductance and providing confirmation of the

formation of a true inversion layer in InAs.

187

APPENDIX A:

CONFERENCE ABSTRACTS

Abstracts from the following conference presentations are included in this

appendix:

“Electrical Properties of HfO 2/InAs MOS Capacitors,” 2007 International

Semiconductor Device Research Symposium;

“Current and Capacitance-Voltage Characterization of HfO 2/InAs and

HfO2/Al2O3/InAs MOS Capacitors formed by Atomic-Layer Deposition,” 2008

Electronic Materials Conference; and

“Deposition of HfO 2 on InAs by ALD,” 2009 Conference of Insulating Films on

Semiconductors.

ISDRS 2007, December 12-14, 2007, College Park, MD, USA

ISDRS 2007 – http://www.ece.umd.edu/ISDRS

Student Paper

Electrical Properties of HfO2/InAs MOS Capacitors

Dana Wheelera, Alan Seabaugha, Linus Frobergb, Claes Thelanderb, and Lars-Erik Wernerssonb

a Department of Electrical Engineering, University of Notre Dame, USA, dwheeler@nd.edu,

b Division of Solid State Physics, Lund University, Sweden

Alternative III-V channel materials are currently under investigation to increase the energy efficiency of microprocessor technology [1]. In this work, the first investigation of Au/Ti/HfO 2/InAs metal-oxide-semiconductor (MOS) capacitors is reported. The HfO 2 is deposited by atomic layer deposition (ALD) and characterized by current-voltage (I-V) and capacitance-voltage (C-V) measurements. The effects of surface treatment, deposition temperature, post-deposition anneal, and film thickness on breakdown field, leakage current, capacitance, and frequency dispersion are studied with the aim of producing HfO 2-InAs interfaces suitable for use in InAs-channel MOSFETs. Hafnium dioxide films were grown using a Cambridge NanoTech Savannah 100 (ALD) system on n-type (~2 x 1016 cm-3) InAs substrates at 100, 200, and 300 °C. Growth cycles of 50, 75, and 125 were used to grow 4.8, 6.5, and 10 nm films, as determined by ellipsometry on calibration samples. The InAs surface was treated prior to loading by immersion in NH4SX, HCl, or buffered HF. After growths, samples were split with one half receiving a 2 min., 400 °C rapid thermal anneal in N2. Titanium-gold was evaporated onto the HfO2 through a stencil mask, yielding 90 × 90 µm2 contacts. The heterojunction band alignments for the heterostructure are given in Fig. 1. The electric field at the onset of destructive breakdown decreases with increasing HfO 2 thickness, Fig. 2. Destructive breakdown occurs at fields as high as 0.95 V/nm in the 6.5 nm films deposited at 100 °C and without a post-growth anneal. Leakage current vs. HfO2 film thickness is plotted in Fig. 3 and fitted to an exponential function as might be anticipated for tunneling leakage. These leakage results can be contrasted with SiON where for an equivalent oxide thickness (EOT) of 1.1-1.46 a leakage current of 50 nA/µm2 is reported [2], while in the HfO 2 of this work an EOT of 1.3 nm (for the HfO 2 4.8-nm film, given εR = 13.9) yields a leakage current typically less than 0.5 pA/µm2. Figure 4 is a representative C-V characteristic with voltage sweeps performed at 10, 100, and 1000 kHz. Sweeping voltage up and down at 1 MHz reveals a significant, 320 mV shift in the characteristic indicating a sheet charge density at the HfO 2/InAs interface of 3 x 1012 cm-2. Figure 5 is a plot of accumulation-regime capacitance versus inverse HfO2 thickness from which a static dielectric constant of 13.9 can be determined from the slope of the line. Figure 6 compares samples pre-cleaned with buffered HF, HCl, and NH4SX, revealing no strong dependence of the leakage current on surface preparation.

References [1] S. Datta et al. “Ultrahigh-speed 0.5 V supply voltage In0.7Ga0.3As quantum-well transistors on silicon substrate,” Electron Dev. Lett, vol. 28, pp. 685-687 (2007). [2] O’Connor et al. “Low voltage stress-induced leakage current in 1.4–2.1 nm SiON and HfSiON gate dielectric layers,” Semicon. Sci. Tech. 20, 668-672 (2005).

ISDRS 2007, December 12-14, 2007, College Park, MD, USA

∆EC2.5 eV

InAsEG

0.36 eV

HfO2EG

6 eV

Ti/Au

Fig. 1. Band alignment for HfO2/InAs MOS

from Robertson and Falabretti, J. Appl. Phys. 100, 014111 (2006).

-1.5

-1

-0.5

0

0.5

1

1.5

0 100 200 300

Bre

akdo

wn

Fie

ld (

V/n

m)

Deposition Temperature (°C)

7w0907LundIV.qpc

solid - no annealopen - 400 °C, 2 min

HClBHFNH

4S

X

6.5 nm4.8,

6.5, and10 nm

6.5 nm

Fig. 2. Destructive breakdown field versus HfO2 deposition temperature for layer thicknesses ranging from 4.8 to 10 nm.

0 2 4 6 8 10 120.01

0.1

1

10

100

1000

Leak

age

Cur

rent

Den

sity

(fA

/µm

2)

HfO2 Thickness (nm)

X - no annealO - 400 °C, 2 min

200 °C depositionHCl treatment

leakage at + and - 1 V

y = 683.12 * e^(-0.85087x) R = 0.49904

Fig. 3. Leakage current density measured at 1 V vs. HfO2 thickness.

0

50

100

150

200

250

-2 -1 0 1 2

Cap

acita

nce

(pF

)

Voltage (V)

7w0823Lund6bFreqCs.qpc

90 X 90 µm2

4.8 nm HfO2

10k Hz

100k

1M

3 × 1012 cm-2

0.32 V shift

HCl surface prep.annealed 400 °C, 2 min

25 mV osc.

Fig. 4. Frequency dependence of the C-V characteristic for a 4.8 nm HfO2 film grown. Voltage sweeps from -2 to 2 V for 10k and 100k Hz; for 1 MHz the sweep is from -2 to

2 and back to -2 V showing hysteresis.

0

50

100

150

200

250

8 107 1.2 108 1.6 108 2 108

y = 9.9809e-7x

1/thickness (m -1)

from slopeε

R = 13.9

90 X 90 µm2

Samples 2b, 6b, 7b200 °C dep., HCl prep.

7w0824LundCvst.qpc

Cap

acita

nce

(pF

)

Fig. 5. Capacitance at substrate bias of -2 V (accumulation). Linear fit (forced through the origin) of capacitance versus inverse

film thickness yields a dielectric constant of 13.9 for films grown at 200 °C.

0

0.2

0.4

0.6

0.8

1

Surface Treatment

HCl NH4S

XBHF

7w0725LeakageTreatment.qpc

6.5 nm HfO2

200 °C depositionX - no anneal

O - 400 °C, 2 min

Leak

age

Cur

rent

Den

sity

(fA

/µm

2 )

leakage measured at + and -1 V

Fig. 6. Leakage current density at +/- 1 V for

various predeposition treatments.

Current and Capacitance-Voltage Characterization of HfO2/InAs and HfO2/Al 2O3/InAs MOS Capacitors formed by Atomic-Layer Deposition

Dana Wheelera, Thomas Kosela, Alan Seabaugha, Linus Frobergb, Claes Thelanderb, and Lars-Erik Wernerssonb

a Department of Electrical Engineering, University of Notre Dame, USA, dwheeler@nd.edu,

b Division of Solid State Physics, Lund University, Sweden

III-V channel field-effect transistors on silicon are currently under investigation to increase the energy effic iency of microprocessor technology [1,2]. Studies of HfO2/InAs MOS diodes [3] have shown leakage currents as low as 0.3 fA/µm2 for an estimated HfO2 equivalent oxide thickness (EOT) of 1.6 nm, with a breakdown voltage which is dependent on growth temperature. This paper extends this work to explore the dependence of current-voltage (I-V) and capacitance-voltage (C-V) characteristics on temperature on both HfO2/InAs and HfO2/Al2O3/InAs heterostructures. The effects of surface treatment, deposition temperature, post-deposition anneal, film thickness, and contact metal on breakdown field, leakage current, capacitance, and frequency dispersion are studied with the aim of producing dielectric -InAs interfaces suitable for use in InAs-channel MOSFETs. Hafnium dioxide films were grown using a Cambridge NanoTech Savannah 100 atomic layer deposition (ALD) system on n-type (~2 × 1016 cm-3) InAs substrates at 80, 250, 300, and 350 °C. The number of ALD growth cycles used ranged from 30 to 50, which, according to ellipsometry performed on calibration samples, should yield films ranging from 2.2 to to 4.8 nm thick. The InAs surface was treated prior to loading by immersion in HCl:H2O (1:1). After growths, samples were split with one half receiving PdAu contacts and the other TiAu. The metal was evaporated onto the HfO2 through a stencil mask, yielding 35 × 35 and 85 × 85 µm2 contacts. Two composite dielectric structures were formed to intentionally create a dielectric interlayer. In the first, 10 cycles of Al2O3 were grown at 300 °C prior to 50 cycles of HfO2 grown at 100 °C. In the second, 10 cycles of HfO2 were grown at 300 °C followed by 50 cycles of HfO2 grown at 100 °C. Through temperature- and thickness- dependent I-V measurements, direct tunneling was determined to be the dominant leakage mechanism through the HfO2. Current density as low as 27 fA/µm2 at 1 V gate bias was observed for a 1.3 nm EOT film with PdAu contacts, which compares favorably to other work on HfO2-III-V MOS [4]. A tunneling effective mass of 0.14me was extracted for biases of 0.5 and 1 V, using a non-parabolic approximation to the HfO2 band structure [5], in good agreement with other studies [6]. The voltage at which destructive dielectric breakdown occurred was found to scale linearly with the number of ALD deposition cycles, consistent with a constant dielectric breakdown field. Breakdown voltage was reduced at higher temperature, in agreement with theory for amorphous dielectrics [7]. Bidirectional capacitance-voltage sweeps revealed hysteresis to be as low as 250 mV, which corresponds to a trapped charge density of 5 × 1012 cm-2, comparable to results obtained by Goel on InGaAs [4]. References [1] S. Datta et al. “Ultrahigh-speed 0.5 V supply voltage In0.7 Ga0.3As quantum-well transistors on silicon substrate,” Electron Dev. Lett, vol. 28, pp. 685-687 (2007). [2] B. Wu et al. “InAs growth on submicron (100) SOI islands for InAs-Si composite channel MOSFETs, Int. Semicon. Dev. Res. Symp. (ISDRS) 2007. [3] D. Wheeler et al. “Electrical Properties of HfO2/InAs MOS Capacitors,” ISDRS 2007. [4] N. Goel et al. “InGaAs metal-oxide-semiconductor capacitors with HfO2 gate dielectric grown by atomic-layer deposition,” Appl. Phys. Lett. 89, 163517 2006. [5] B. Brar et al. “Direct extraction of the electron tunneling effective mass in ultrathin SiO2,” Appl. Phys. Lett. 69, pp. 2728-2730 1996. [6] C. L. Hinkel et al. ”Enhanced tunneling in stacked gate dielectrics with ultra-thin HfO2 (ZrO2) layers sandwiched between thicker SiO2 layers,” Surf. Sci. 566-568, pp. 1185-1189 2004. [7] H. Fröhlich “On the Theory of Dielectric Breakdown in Solids,” Proc. Roy. Soc. London, Ser. A 188, pp. 521-532 1947.

∆EC2.5 eV

InAsEG

0.36 eV

HfO2EG

6 eV

Ti/Au

Fig. 1. Band alignment for HfO2/InAs MOS

from Robertson and Falabretti, J. Appl. Phys. 100, 014111 (2006).

y = 1.607e-8 * e^(-3.9102x) R= 0.99354 y = 5.1524e-9 * e^(-4.2654x) R= 0.99243

10-19

10-18

10-17

10-16

10-15

10-14

0 1 2 3 4 5

J*t O

X

2 (A)

tOX

(nm)

+1 V+0.5 V

HCl, 300 °C, TiAuno anneal

85 X 85 µm2

10-7

10-5

10-3

10-1

101

-2 -1 0 1 2

J (

nA/µ

m2)

Voltage (V)

3.4 nm

4.1

4.8

Fig. 2. Tunnel current density times oxide thickness squared vs. oxide thickness tOX.

Tunnel current density increases exponentially with reduced film thickness,

suggesting that direct tunneling is the dominate leakage mechanism. Using a

barrier height (F M - ?InAs + ? EC) of 1.8 eV, a tunneling effective mass of 0.14me is

obtained for both gate biases. The inset contains the I-V characteristics from which the tunneling effective mass was obtained.

10-9

10-7

10-5

10-3

10-1

-2 -1 0 1 2

Cur

rent

Den

sity

(nA

/µm

2 )

Voltage (V)

250

80

300 °C

HCl, 50 cycles, TiAu 85 X 85 µm2

80

250

300

Fig. 3. Gate current-voltage characteristics

for films grown at different deposition temperatures with nominally the same

thickness (50 ALD cycles).

0

0.5

1

1.5

2

2.5

0 10 20 30 40 50 60

y = 0.76417 + 0.025875x R= 0.89902 y = 0.80765 + 0.018441x R= 0.99023

Bre

akdo

wn

Vol

tage

(V)

# of ALD cycles

HCl, 300 °CTiAu

85 X 85 µm2

measurement temperature:solid - room

open - 100 °C

Fig. 4. Destructive breakdown voltage vs.

number of ALD cycles. Breakdown voltage scales linearly with the number of cycles,

consistent with a constant dielectric breakdown field, however, it does not scale to zero for zero ALD cycles, suggesting the

existence of an interlayer.

y = 10.363 - 0.020663x R= 0.8372 0

2

4

6

8

10

0 100 200 300 400

Bre

akdo

wn

Fie

ld (M

V/c

m)

HfO2 Growth Temperature (°C)

HCl pre-treatmentTiAu contacts

no anneal3.4 - 10 nm HfO

2

85 X 85 µm2

Fig. 5. Breakdown field vs. HfO2 growth

temperature. Over a range of film thicknesses, breakdown field is shown to

increase with reduced growth temperature.

0

2

4

6

-1 0 1Cap

acita

nce

Den

sity

(µF/

cm2 )

Voltage (V)

30 cycles

40

50

35 X 35 µm2

1 MHz, 25 mV osc.

HCl, 300 °Cno anneal

TiAu contacts

0

0.4

0.8

1.2

0 10 20 30 40 50 60

EO

T (n

m)

# of ALD cycles

R = 0.99774y = 0.057 + 0.021x

Fig. 6. C-V characteristics of 30, 40, and 50 cycle films. Inset shows EOT vs. number of ALD cycles, from which an interlayer EOT

of 0.57 nm is calculated.

Deposition of HfO2 on InAs by ALD

D Wheeler*, L-E Wernersson, L Fröberg, C Thelander, A Mikkelsen, K-J Weststrate, A Seabaugh*

Solid State Physics, Lund University, Lund, Sweden *Electrical Engineering, University of Notre Dame, Notre Dame, US

Tel: +46-462227678, email:lars-erik.wernersson@ftf.lth.se

1. Introduction The introduction of high-κ material on III/V

semiconductors is attracting increasing interest. The use of a III/V channel material increases the drive current, which allows for low-power operation. Although there are several reports on the properties of HfO2 on various III/V materials [1, 2], the combination of HfO2 and InAs has not been studied in detail yet [3, 4].

In this study, HfO2 has been deposited on InAs by Atomic Layer Deposition and the electrical properties of the films are evaluated by current-voltage and capacitance-voltage spectroscopy, supported by XPS studies. In particular, the deposition conditions, i.e. the temperature, and sample pre -treatment have been studied. It is shown that the deposition temperature has a strong influence on both the leakage current and the capacitance characteristics.

2. Processing and characterization techniques Hafnium dioxide films were grown using a

Cambridge NanoTech Savannah 100 (ALD) system using TDMA-Hf (tetrakis (dimethylamino) hafnium) and water vapor as source materials. The substrates were n-type (~2 x 1016 cm-3) InAs substrates and the deposition were done in the range of 80 to 350 °C. Growth cycles of 50, 75, and, 125 were used to grow 3.9, 5.7, and 9.4 nm films, as determined by ellipsometry on calibration samples. The InAs surface was treated prior to loading by immersion in NH3OH, NH4SX, HCl, or buffered HF. After growths, samples were split with one half receiving a 2 min., 400 °C rapid thermal anneal in N2. Titanium-gold was evaporated onto the HfO2 through a stencil mask, yielding 85 × 85 ? m2 contacts.

The electrical properties were characterized in a Cascade probe station using the substrate as a back contact. The I-V and C-V characteristics were measured for the different samples at various temperatures. Reference samples were used to perform XPS and TEM of the interface between the HfO2 and the InAs.

3. Experimental results The I-V characteristics reveal that the leakage

current is greatly reduced when the film is deposited at a low temperature. Also the breakdown voltage is increased. From the capacitance studies we learn that the films deposited at 300 °C reaches the highest accumulation capacitance and hence have a stronger

modulation, while the films deposited at 250-300 °C show the smallest hysteresis.

In order to get a better understanding about the physical processes at the interfaces, we have studied the interface properties of HfO2/InAs structures by XPS. In this case the HfO2 film thickness was reduced to 25 cycles corresponding to nominally 1.6 nm to increase the resolution in the measurements. The data showed that the samples treated with HF or HCl has a weaker signal related to the AsOx as compared to the samples treated with NH3OH or S-passivation. The signal related to In, however, essentially remained constant and also the thickness was similar on the samples, as expected. For the HF-treated sample, the films deposited at 150 and 350 ºC showed stronger signals related to AsOx and InOx than the sample deposited at 250 °C.

4. Further experiments Due to the narrow band gap of InAs, the dynamic

processes are very fast and in order to accurately record the depletion and inversion capacitance, the samples have been studied at 77 K (not shown). At this temperature, the high frequency C-V show no inversion, while the low frequency C-V show inversion, as expected. This verifies that the room temperature C-V is a good measure of the material quality.

We have also used the ALD to insert an AlOx layer into the HfO2/InAs structure to form a composite MOS-structure. This structure shows better electrical characteristics with a reduced density of states, while the XPS demonstrate that the AlOx is effective in dissolving both the AsOx and the InOx.

4. Discussion We have fabricated and characterized HfO2 films on

InAs substrates for the use in MOS capacitors. Films deposited at low temperature show lower leakage currents and higher breakdown voltages than films deposited at higher temperatures. XPS studies and determination of the hysteresis in the capacitance curves show that the optimum deposition temperature is about 250 °C and that both the oxide-related XPS signal as well as the hysteresis are increasing at higher and lower deposition temperatures.

References

[1] N Goel, et al, App Phys Lett 89 (2006) 163517 [2] H-S Kim, et al, App Phys Lett 93 (2008) 062111 [3] D Wheeler et al, Tech Digest ISDRS (2007) [4] S Roddaro et al, App Phys Lett, 92 (2008) 253509

Fig.1.Schematic structure. Fig.2.Summary of IVs for deposition at various

temperatures.

Deposition temperature

ºC

EOT

Å

Cacc/C/inv Vhyst

V

100 3.0 1,43 2.44

200 1.87 1.42 0.66

300 1.40 1.38 0.2

Fig.3. Summary of CV for depositions at various temperatures. Fig.4. Summary for CV-data for MOS capacitors with 75 cycles HfO2 deposited at various

temperatures and with HCl pretreatment. No annealing was done.

Surface pretreatment

EOT

Å

Cacc/C/inv Vhyst

V

HCl:H2O 1.87 1.42 0.66

NH4Sx 1.76 1.49 0.73

BHF 1.83 1.48 0.27

Fig.5 Summary for CV-data for MOS capacitors with 75

cycles HfO2 deposited at T=200 ºC without annealing. Fig.6. Example from XPS study comparing the As 3d spectra for HfO2 and Al2O3 to the bare InAs surface.

194

REFERENCES

[1] V. V. Zhirnov, R. K. Cavin, III, J. A. Hutchby, and G. I. Bourianoff, "Limits to binary logic switch scaling - a gedanken model," Proceedings of the IEEE, vol. 91, pp. 1934, 2003.

[2] J. Bardeen and W. H. Brattain, "The transistor, a semi-conductor triode," Physical

Review, vol. 74, pp. 230, 1948. [3] J. E. Lilienfeld, (1926) Method and apparatus for controlling electric currents.

U.S. Patent No. 1745175 [4] M. Riordan and L. Hoddeson, "Minority views," in Crystal fire. New York: W.

W. Norton & Company, 1997, pp. 144-146. [5] J. Bardern, "Surface states and rectification at a metal semi-conducter contact,"

Physical Review, vol. 71, pp. 717, 1947. [6] W. Shockley and G. L. Pearson, "Modulation of conductance of thin films of

semi-conductors by surface charges," Physical Review, vol. 74, pp. 232, 1948. [7] M. M. Atalla, (1965) Semiconductor devices having dielectric coatings. U.S.

Patent No. 3,206,670 [8] D. Kahng and M. M. Atalla, "Silicon-silicon dioxide field induced surface

devices," in IRE-AIEE Solid-State Device Res. Conf. Carnegie Inst. of Technol., Pittsburgh, PA, 1960.

[9] D. Kahng, "A historical perspective on the development of mos transistors and

related devices," IEEE Transactions on Electron Devices, vol. ED-23, pp. 655, 1976.

195

[10] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McLntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, "A 45 nm logic technology with high-k+metal gate transistors, strained silicon, 9 cu interconnect layers, 193 nm dry patterning, and 100% pb-free packaging," 2007 IEEE International Electron Devices Meeting - IEDM '07, 2007, pp. 247.

[11] International technology roadmap for semiconductors. 2008. 3 February 2009

http://public.itrs.net [12] B. Brar, G. D. Wilk, and A. C. Seabaugh, "Direct extraction of the electron

tunneling effective mass in ultrathin silicon dioxide," Applied Physics Letters, vol. 69, pp. 2728, 1996.

[13] J. Robertson, "High dielectric constant oxides," European Physical Journal,

Applied Physics, vol. 28, pp. 265, 2004. [14] K. F. Brennan and A. S. Brown, "Theory of modern electronic semiconductor

devices." New York: John Wiley & Sons, Inc., 2002, pp. 435-442. [15] S. M. Sze, "Physics of semiconductor devices." New York: John Wiley & Sons,

Inc., 1981, pp. 849. [16] Z. Qin, F. Tian, X. Huili, A. Seabaugh, and D. Jena, "Graphene nanoribbon tunnel

transistors," IEEE Electron Device Letters, vol. 29, pp. 1344, 2008. [17] Z. Qin, Z. Wei, and A. Seabaugh, "Low-subthreshold-swing tunnel transistors,"

IEEE Electron Device Letters, vol. 27, pp. 297, 2006. [18] S. Jha, X. Song, S. E. Babcock, T. F. Kuech, D. Wheeler, B. Wu, P. Fay, and A.

Seabaugh, "Growth of inas on si substrates at low temperatures using metalorganic vapor phase epitaxy," Journal of Crystal Growth, vol. 310, pp. 4772, 2008.

[19] W. Bin, D. Wheeler, Y. Changhyun, I. Yoon, S. Jha, A. Brown, T. Kuech, P. Fay,

and A. Seabaugh, "Inas growth on submicron (100) soi islands for inas-si composite channel mosfets," International Semiconductor Device Research Symposium, 2007, pp. 371.

196

[20] C. Thelander, L. E. FrobergFroberg, C. Rehnstedt, L. Samuelson, and L.-E. Wernersson, "Vertical enhancement-mode inas nanowire field-effect transistor with 50-nm wrap gate," IEEE Electron Device Letters, vol. 29, pp. 206, 2008.

[21] C. Rehnstedt, T. Martensson, C. Thelander, L. Samuelson, and L.-E. Wernersson,

"Vertical inas nanowire wrap gate transistors on si substrates," IEEE Transactions on Electron Devices, vol. 55, pp. 3037, 2008.

[22] H. Becke, R. Hall, and J. White, "Gallium arsenide m. O. S. Transistors," Solid-

State Electronics, vol. 8, pp. 813, 1965. [23] H. W. Becke and J. P. White, "Gallium arsenide fet's outperform conventional

silicon mos devices," Electronics, vol. 40, pp. 82, 1967. [24] T. Mimura, S. Hiyamizu, T. Fujii, and K. Nanbu, "A new field-effect transistor

with selectively doped gaas/n-alxga1-xas heterojunctions," Japanese Journal of Applied Physics, vol. 19, pp. 225, 1980.

[25] P. D. Ye, "Beyond silicon's elemental logic," IEEE Spectrum, vol. 45, pp. 42,

2008. [26] L. Messick, "Power gain and noise of inp and gaas insulated gate microwave

fets," Solid-State Electron., vol. 22, pp. 71-&, 1979. [27] K. Kamimura and Y. Sakai, "Properties of gaas-al2o3 and inp-al2o3 interfaces

and the fabrication of mis field-effect transistors," Thin Solid Films, vol. 56, pp. 215-223, 1979.

[28] H. C. Casey, A. Y. Cho, and E. H. Nicollian, "Use of oxygen-doped alxga1-xas

for insulating layer in mis structures," Appl. Phys. Lett., vol. 32, pp. 678-679, 1978.

[29] M. R. Melloch, N. Otsuka, J. M. Woodall, A. C. Warren, and J. L. Freeouf,

"Formation of arsenic precipitates in gaas buffer layers grown by molecular-beam epitaxy at low substrate temperatures," Appl. Phys. Lett., vol. 57, pp. 1531-1533, 1990.

[30] D. N. Butcher and B. J. Sealy, "Electrical-properties of thermal oxides on gaas,"

Electron. Lett., vol. 13, pp. 558-559, 1977. [31] R. A. Logan, B. Schwartz, and W. J. Sundburg, "Anodic-oxidation of gaas in

aqueous h2o2 solution," J. Electrochem. Soc., vol. 120, pp. 1385-1390, 1973. [32] H. Hasegawa, K. E. Forward, and H. L. Hartnagel, "New anodic native oxide of

gaas with improved dielectric and interface properties," Appl. Phys. Lett., vol. 26, pp. 567-569, 1975.

197

[33] Weinreic.Oa, "Oxide films grown on gaas in an oxygen plasma," J. Appl. Phys.,

vol. 37, pp. 2924-&, 1966. [34] V. M. Bermudez, "Photoenhanced oxidation of gallium-arsenide," J. Appl. Phys.,

vol. 54, pp. 6795-6798, 1983. [35] H. E. Kunig, "Analysis of an inas thin film transistor," Solid-State Electronics,

vol. 11, pp. 335, 1968. [36] R. J. Schwartz, R. C. Dockerty, and H. W. Thompson Jr, "Capacitance voltage

measurements on n- type inas mos diodes," 14, pp. 115, 1971. [37] H. Terao, T. Ito, and Y. Sakai, "Interface properties of inas-mis structures and

their application to fet," Electrical Engineering in Japan, vol. 94, pp. 127. [38] C. W. Wilmsen, L. G. Meiners, and D. A. Collins, "Single- and double- layer

insulator metal-oxide-semiconductor capacitors on indium arsenide," Thin Solid Films, vol. 46, pp. 331, 1977.

[39] D. H. Laughlin and C. W. Wilmsen, "Thermal oxidation of inas," Thin Solid

Films, vol. 70, pp. 325, 1980. [40] L. Messick, "A dc to 16 ghz indium phosphide misfet," Solid-State Electronics,

vol. 23, pp. 551, 1980. [41] L. G. Meiners, "Electrical properties of sio2 and si3n4 dielectric layers on inp," J.

Vac. Sci. Technol. (USA), 1981, pp. 373. [42] L. J. Messick, "A high-speed monolithic inp misfet integrated logic inverter,"

IEEE Transactions on Electron Devices, vol. ED-28, pp. 218, 1981. [43] D. L. Lile, D. A. Collins, L. G. Meiners, and L. Messick, "N-channel inversion-

mode inp m. I. S. F. E. T," Electronics Letters, vol. 14, pp. 657, 1978. [44] L. L. Chang and W. E. Howard, "Surface inversion and accumulation of anodized

insb," Appl. Phys. Lett., vol. 7, pp. 210-&, 1965. [45] Y. C. Wang, M. Hong, J. M. Kuo, J. P. Mannaerts, J. Kwo, H. S. Tsai, J. J.

Krajewski, Y. K. Chen, and A. Y. Cho, "Demonstration of submicron depletion-mode gaas mosfet's with negligible drain current drift and hysteresis," IEEE Electron Device Lett., vol. 20, pp. 457-459, 1999.

198

[46] F. Ren, J. M. Kuo, M. Hong, W. S. Hobson, J. R. Lothian, J. Lin, H. S. Tsai, J. P. Mannaerts, J. Kwo, S. N. G. Chu, Y. K. Chen, and A. Y. Cho, "Ga2o3(gd2o3)/ingaas enhancement-mode n-channel mosfet's," IEEE Electron Device Lett., vol. 19, pp. 309-311, 1998.

[47] J. Zhang, T. H. Kosel, D. C. Hall, and P. Fay, "Fabrication and performance of

0.25 -m gate length depletion-mode gaas-channel mosfets with self-aligned inalp native oxide gate dielectric," IEEE Electron Device Letters, vol. 29, pp. 143, 2008.

[48] Y. Cao, X. Li, J. Zhang, P. Fay, T. H. Kosel, and D. C. Hall, "Microwave

performance of gaas mosfet with wet thermally oxidized inalp gate dielectric," IEEE Electron Device Letters, vol. 27, pp. 317, 2006.

[49] L. Xiang, Y. Cao, D. C. Hall, P. Fay, X. Zhang, and R. D. Dupuis, "Electrical

characterization of native-oxide inalp/gaas metal-oxide-semiconductor heterostructures using impedance spectroscopy," Journal of Applied Physics, vol. 95, pp. 4209, 2004.

[50] Y. Cao, J. Zhang, X. Li, T. H. Kosel, P. Fay, D. C. Hall, X. B. Zhang, R. D.

Dupuis, J. B. Jasinski, and Z. Liliental-Weber, "Electrical properties of inalp native oxides for metal-oxide-semiconductor device applications," Applied Physics Letters, vol. 86, pp. 62105, 2005.

[51] T. Suntola and J. Hyvarinen, "Atomic layer epitaxy," in Annual review of

materials science. Vol.15. Palo Alto, CA, USA: Annual Reviews, 1985, pp. 177. [52] P. D. Ye, "Main determinants for iii-v metal-oxide-semiconductor field-effect

transistors (invited)," Journal of Vacuum Science &amp; Technology A (Vacuum, Surfaces, and Films), vol. 26, pp. 697, 2008.

[53] P. D. Ye, G. D. Wilk, B. Yang, J. Kwo, S. N. G. Chu, S. Nakahara, H. J. L.

Gossmann, J. P. Mannaerts, M. Hong, K. K. Ng, and J. Bude, "Gaas metal-oxide-semiconductor field-effect transistor with nanometerthin dielectric grown by atomic layer deposition," Appl. Phys. Lett., vol. 83, pp. 180-182, 2003.

[54] P. D. Ye, G. D. Wilk, J. Kwo, B. Yang, H. J. L. Gossmann, M. Frei, S. N. G. Chu,

J. P. Mannaerts, M. Sergent, M. Hong, K. K. Ng, and J. Bude, "Gaas mosfet with oxide gate dielectric grown by atomic layer deposition," IEEE Electron Device Letters, vol. 24, pp. 209, 2003.

[55] M. M. Frank, G. D. Wilk, D. Starodub, T. Gustafsson, E. Garfunkel, Y. J. Chabal,

J. Grazul, and D. A. Muller, "Hfo2 and al2o3 gate dielectrics on gaas grown by atomic layer deposition," 86, 2005.

199

[56] N. Goel, P. Majhi, C. O. Chui, W. Tsai, D. Choi, and J. S. Harris, "Ingaas metal-oxide-semiconductor capacitors with hfo2 gate dielectric grown by atomic-layer deposit ion," preprint submitted to Applied Physics Letters, 2006.

[57] L. Ning, E. S. Harmon, J. Hyland, D. B. Salzman, T. P. Ma, and P. D. Ye,

"Properties of inas metal-oxide-semiconductor structures with atomic- layer-deposited al2o3 dielectric," Applied Physics Letters, vol. 92, pp. 143507, 2008.

[58] P. D. Ye, B. Yang, K. K. Ng, J. Bude, G. D. Wilk, S. Halder, and J. C. M. Hwang,

"Gan metal-oxide-semiconductor high-electron-mobility-transistor with atomic layer deposited al2o3 as gate dielectric," Applied Physics Letters, vol. 86, pp. 63501, 2005.

[59] H.-S. Kim, I. Ok, M. Zhang, F. Zhu, S. Park, J. Yum, H. Zhao, J. C. Lee, P.

Majhi, N. Goel, W. Tsai, C. K. Gaspe, and M. B. Santos, "A study of metal-oxide-semiconductor capacitors on gaas, in[sub 0.53]ga[sub 0.47]as, inas, and insb substrates using a germanium interfacial passivation layer," Applied Physics Letters, vol. 93, pp. 062111, 2008.

[60] M. Shur, "Surface charge in metal oxide semiconductor capacitor," in Physics of

semiconductor devices. Upper Saddle River, NJ: Prentice Hall, 1990, pp. 341. [61] M. Shur, "Surface charge in metal oxide semiconductor capacitor," in Physics of

semiconductor devices. Upper Saddle River, NJ: Prentice Hall, 1990, pp. 332-343. [62] E. H. Nicollian and J. R. Brews, "Small-signal steady-state capacitance methods,"

in Mos (metal oxide semiconductor) physics and technology, Wiley Classics Library ed. Hoboken, NJ: John Wiley & Sons, 2003, pp. 321-333.

[63] D. L. Winn, M. J. Hale, T. J. Grassman, A. C. Kummel, R. Droopad, and M.

Passlack, "Direct and indirect causes of fermi level pinning at the sio/gaas interface," Journal of Chemical Physics, vol. 126, pp. 84703, 2007.

[64] E. M. Vogel, C. A. Richter, and B. G. Rennex, "A capacitance-voltage model for

polysilicon-gated mos devices including substrate quantization effects based on modification of the total semiconductor charge," Solid-State Electron., vol. 47, pp. 1589-1596, 2003.

[65] A. Yassine and R. Hijab, "Temperature dependence of gate current in ultra thin

sio2 in direct-tunneling regime," 1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319), 1997, pp. 56.

[66] J. Scarpulla, D. C. Eng, S. R. Olson, and C. S. Wu, "A tddb model of si3n4-based

capacitors in gaas mmics," 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296), 1999, pp. 128.

200

[67] L. Larcher, A. Paccagnella, and G. Ghidini, "Gate current in ultrathin mos capacitors: A new model of tunnel current," IEEE Transactions on Electron Devices, vol. 48, pp. 271, 2001.

[68] J. Robertson and B. Falabretti, "Band offsets of high k gate oxides on iii-v

semiconductors," Journal of Applied Physics, vol. 100, pp. 14111, 2006. [69] L. Wen-Chin and H. Chenming, "Modeling cmos tunneling currents through

ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling," IEEE Transactions on Electron Devices, vol. 48, pp. 1366, 2001.

[70] C. L. Hinkle, C. Fulton, R. J. Nemanich, and G. Lucovsky, "Enhanced tunneling

in stacked gate dielectrics with ultra-thin hfo2 (zro2) layers sandwiched between thicker sio2 layers," Surf. Sci. (Netherlands), 2004, pp. 1185.

[71] Y. Yee Chia, L. Qiang, L. Wen Chin, K. Tsu-Jae, H. Chenming, W. Xiewen, G.

Xin, and T. P. Ma, "Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric," IEEE Electron Device Letters, vol. 21, pp. 540, 2000.

[72] Basic parameters of indium arsenide (inas). 23 July 2001. Ioffe Physico-Technical

Institute, St. Petersburg, Russia. 23 December 2008 http://www.ioffe.ru/SVA/NSM/Semicond/InAs/index.html

[73] Agilent technologies, "impedance measurement handbook," 2006. [74] Agilent technologies, "evaluation of mos capacitor oxide c-v characteristics using

the agilent 4294a," application note 4294-3, 2003. [75] M. Akazawa and H. Hasegawa, "Admittance study of gaas high-k metal- insulator-

semiconductor capacitors with si interface control layer," Journal of Vacuum Science &amp; Technology B (Microelectronics and Nanometer Structures), vol. 26, pp. 1569, 2008.

[76] M. Passlack, "Development methodology for high-&kappa; gate dielectrics on iii-

v semiconductors: Gdxga0.4-xo0.6/ga2o3 dielectric stacks on gaas," J. Vac. Sci. Technol. B, Microelectron. Nanometer Struct. (USA), 2005, pp. 1773.

[77] Isi web of knowledge, http://www.Isiwebofknowledge.Com/ [78] Engineering information engineering village, http://www.Ei.Org/ [79] D. M. Hausmann, E. Kim, J. Becker, and R. G. Gordon, "Atomic layer deposition

of hafnium and zirconium oxides using metal amide precursors," Chemistry of Materials, vol. 14, pp. 4350, 2002.

201

[80] V. I. Belyi, T. P. Smirnova, and N. F. Zakharchuk, "On the problem of elemental bv material in the interface of native oxide/aiiibv structures," Thin Solid Films, vol. 113, pp. 157, 1984.

[81] R. Nyholm, J. N. Andersen, U. Johansson, B. N. Jensen, and I. Lindau, "Beamline

i311 at max-lab: A vuv/soft x-ray undulator beamline for high resolution electron spectroscopy," Nucl. Instrum. Methods Phys. Res. A, Accel. Spectrom. Detect. Assoc. Equip. (Netherlands), 2001, pp. 520.

[82] E. H. Nicollian and J. R. Brews, "Minority carrier response time," in Mos (metal

oxide semiconductor) physics and technology, Wiley Classics Library ed. Hoboken, NJ: John Wiley & Sons, 2003, pp. 104-156.

[83] H. Hasegawa and H. Ohno, "Unified disorder induced gap state model for

insulator-semiconductor and metal-semiconductor interfaces," J. Vac. Sci. Technol. B, Microelectron. Process. Phenom. (USA), 1986, pp. 1130.

[84] K. Ahmed, E. Ibok, G. Bains, D. Chi, B. Ogle, J. J. Wortman, and J. R. Hauser,

"Comparative physical and electrical metrology of ultrathin oxides in the 6 to 1.5 nm regime," IEEE Transactions on Electron Devices, vol. 47, pp. 1349, 2000.

[85] M. J. McNutt and C. T. Sah, "Determination of the mos oxide capacitance,"

Journal of Applied Physics, vol. 46, pp. 3909, 1975. [86] M. Depast, R. L. van Meirhaeghe, W. H. Laflere, and F. Cardon, "Electrical

characteristics of al/sio2/n-si tunnel diodes with an oxide layer grown by rapid thermal oxidation," Solid-State Electronics, vol. 37, pp. 433, 1994.

[87] B. Ricco, P. Olivo, T. N. Nguyen, T. S. Kuan, and G. Ferriani, "Oxide-thickness

determination in thin- insulator mos structures," IEEE Transactions on Electron Devices, vol. 35, pp. 432, 1988.

[88] J. Maserjian, G. Petersson, and C. Svensson, "Saturation capacitance of thin oxide

mos structures and the effective surface density of states of silicon," Solid-State Electronics, vol., pp. 335, 1974.

[89] S. Kar, "Extraction of the capacitance of ultrathin high-k gate dielectrics," IEEE

Transactions on Electron Devices, vol. 50, pp. 2112, 2003. [90] E. H. Nicollian and J. R. Brews, "Minority carrier response time," in Mos (metal

oxide semiconductor) physics and technology, Wiley Classics Library ed. Hoboken, NJ: John Wiley & Sons, 2003, pp. 144.

202

[91] K. Martens, C. O. Chui, G. Brammertz, B. De Jaeger, D. Kuzum, M. Meuris, M. M. Heyns, T. Krishnamohan, K. Saraswat, H. E. Maes, and G. Groeseneken, "On the correct extraction of interface trap density of mos devices with high-mobility semiconductor substrates," IEEE Transactions on Electron Devices, vol. 55, pp. 547, 2008.

[92] R. Droopad, M. Passlack, N. England, K. Rajagopalan, J. Abrokwah, and A.

Kummel, "Gate dielectrics on compound semiconductors," Microelectronic Engineering, vol. 80, pp. 138, 2005.

[93] R. Castagne and A. Vapaille, "Description of the sio2-si interface properties by

means of very low frequency mos capacitance measurements," Surface Science, vol. 28, pp. 157, 1971.

[94] L. M. Terman, "An investigation of surface states at a silicon/silicon oxide

interface employing metal-oxide-silicon diodes," Solid-State Electronics, vol. 5, pp. 285, 1962.

[95] S. J. Koester, E. W. Kiewra, S. Yanning, D. A. Neumayer, J. A. Ott, M. Copel, D.

K. Sadana, D. J. Webb, J. Fompeyrine, J. P. Locquet, C. Marchiori, M. Sousa, and R. Germann, "Evidence of electron and hole inversion in gaas metal-oxide-semiconductor capacitors with hfo2 gate dielectrics and &alpha;-si/sio2 interlayers," Applied Physics Letters, vol. 89, pp. 42104, 2006.

[96] E. Vogel, University of Texas at Dallas, private communication 2009. [97] D. Adams, Fitxps2, Ver. 2.12, 2001, http://www.sljus.lu.se/download.html [98] H. Frohlich, "On the theory of dielectric breakdown in solids," Proceedings of the

Royal Society of London, Series A (Mathematical and Physical Sciences), vol. 188, pp. 521, 1947.

[99] N. Klein and H. Gafni, "The maximum dielectric strength of thin silicon oxide

films," IEEE Transactions on Electron Devices, vol. ED-13, pp. 281, 1966. [100] I. Ok, H. Kim, M. Zhang, F. Zhu, S. Park, J. Yum, H. Zhao, and J. C. Lee, "Self-

aligned n-channel gaas metal-oxide-semiconductor field-effect transistors (mosfets) using hfo2 and silicon interface passivation layer: Post-metal annealing optimization," Microelectronic Engineering, vol. 86, pp. 291, 2009.

[101] C. P. Chen, Y. J. Lee, Y. C. Chang, Z. K. Yang, M. Hong, J. Kwo, H. Y. Lee, and

T. S. Lay, "Structural and electrical characteristics of ga2o3(gd2o3)/gaas under high temperature annealing," Journal of Applied Physics, vol. 100, pp. 104502, 2006.

203

[102] G. Eftekhari, "The effect of sulfur passivation and rapid thermal annealing on the properties of inas mos structures with the oxide layer deposited by reactive sputtering," Physica Status Solidi A, vol. 161, pp. 571, 1997.

[103] C. Auth, A. Cappellani, J. S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T.

Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi, J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris, N. Rahhal-orabi, P. Ranade, J. Sandford, L. Shifren, V. Souw, K. Tone, F. Tambwe, A. Thompson, D. Towner, T. Troeger, P. Vandervoorn, C. Wallace, J. Wiedemer, and C. Wiegand, "45 nm high-k + metal gate strain-enhanced transistors," 2008 Symposium on VLSI Technology, 2008, pp. 128.

[104] S. B. Samavedam, H. H. Tseng, P. J. Tobin, J. Mogab, S. Dakshina-Murthy, L. B.

La, J. Smith, J. Schaeffer, M. Zavala, R. Martin, B. Y. Nguyen, L. Hebert, O. Adetutu, V. Dhandapani, T. Y. Luo, R. Garcia, P. Abramowitz, M. Moosa, D. C. Gilmer, C. Hobbs, W. J. Taylor, J. M. Grant, R. Hegde, S. Bagchi, E. Luckowski, V. Arunachalam, and M. Azrak, "Metal gate mosfets with hfo2 gate dielectric," 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303), 2002, pp. 24.

[105] L. Qiang, Y. Yee Chia, P. Ranade, H. Takeuchi, K. Tsu-Jae, H. Chenming, S. C.

Song, H. F. Luan, and K. Dim-Lee, "Dual-metal gate technology for deep-submicron cmos transistors," 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104), 2000, pp. 72.

[106] F. S. Aguirre-Tostado, M. Milojevic, K. J. Choi, H. C. Kim, C. L. Hinkle, E. M.

Vogel, J. Kim, T. Yang, Y. Xuan, P. D. Ye, and R. M. Wallace, "S passivation of gaas and band bending reduction upon atomic layer deposition of hfo2/al2o3 nanolaminates," Applied Physics Letters, vol. 93, pp. 061907, 2008.

[107] R. Suri, B. Lee, D. J. Lichtenwalner, N. Biswas, and V. Misra, "Electrical

characteristics of metal-oxide-semiconductor capacitors on p-gaas using atomic layer deposition of ultrathin hfalo gate dielectric," Applied Physics Letters, vol. 93, pp. 193504 (3 pp.), 2008.

[108] T. Yang, Y. Xuan, D. Zemlyanov, T. Shen, Y. Q. Wu, J. M. Woodall, P. D. Ye, F.

S. Aguirre-Tostado, M. Milojevic, S. McDonnell, and R. M. Wallace, "Interface studies of gaas metal-oxide-semiconductor structures using atomic- layer-deposited hfo2/al2o3 nanolaminate gate dielectric," Applied Physics Letters, vol. 91, pp. 142122, 2007.

[109] J. Robertson, "Maximizing performance for higher k gate dielectrics," Journal of

Applied Physics, vol. 104, pp. 124111 (7 pp.), 2008.

204

[110] Y. C. Yeo, K. Tsu-Jae, and H. Chenming, "Direct tunneling leakage current and scalability of alternative gate dielectrics," Applied Physics Letters, vol. 81, pp. 2091, 2002.

[111] K. Y. Lee, P. Chang, Y. C. Chang, M. L. Huang, Y. J. Lee, M. Hong, and J. Kwo,

"Sub-nanometer eot scaling on in0.53ga0.47as with atomic layer deposited hfo2 as gate dielectric," 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2008, pp. 150.

[112] S. Koveshnikov, W. Tsai, I. Ok, J. C. Lee, V. Torkanov, M. Yakimov, and S.

Oktyabrsky, "Metal-oxide-semiconductor capacitors on gaas with high-k gate oxide and amorphous silicon interface passivation layer," Applied Physics Letters, vol. 88, pp. 22106, 2006.

[113] C. Chao-Ching, C. Chao-Hsin, L. Guang-Li, T. Chih-Kuo, C. Hsin-Che, Y. Chun-

Hui, and C. Chun-Yen, "Improved electrical properties of gd2o3/gaas capacitor with modified wet-chemical clean and sulfidization procedures," Journal of the Electrochemical Society, vol. 155, pp. G56-G60, 2008.

[114] D. Shahrjerdi, M. M. Oye, J. A. L. Holmes, and S. K. Banerjee, "Unpinned metal

gate/high-kappa gaas capacitors: Fabrication and characterization," Applied Physics Letters, vol. 89, pp. 043501, 2006.

[115] H.-S. Kim, I. Ok, M. Zhang, T. Lee, F. Zhu, L. Yu, and J. C. Lee, "Metal gate-

hfo[sub 2] metal-oxide-semiconductor capacitors on n-gaas substrate with silicon/germanium interfacial passivation layers," Applied Physics Letters, vol. 89, pp. 222903, 2006.

[116] H.-S. Kim, I. Ok, M. Zhang, F. Zhu, S. Park, J. Yum, H. Zhao, and J. C. Lee,

"Gate oxide scaling down in hfo[sub 2]--gaas metal-oxide-semiconductor capacitor using germanium interfacial passivation layer," Applied Physics Letters, vol. 91, pp. 042904, 2007.

[117] M. Zhu, C.-H. Tung, and Y.-C. Yeo, "Aluminum oxynitride interfacial

passivation layer for high-permittivity gate dielectric stack on gallium arsenide," Applied Physics Letters, vol. 89, pp. 202903, 2006.

[118] M. H. Zhang, I. J. Ok, H. S. Kim, F. Zhu, T. Lee, G. Thareja, L. Yu, and J. C.

Lee, "Characteristics of sputtered hf[sub 1 - x]si[sub x]o[sub 2]/si/gaas gate stacks," Applied Physics Letters, vol. 89, pp. 042902, 2006.

[119] S. I. Park, I. Ok, H.-S. Kim, F. Zhu, M. Zhang, J. H. Yum, Z. Han, and J. C. Lee,

"Optimization of electrical characteristics of tio[sub 2]-incorporated hfo[sub 2] n-type doped gallium arsenide metal oxide semiconductor capacitor with silicon interface passivation layer," Applied Physics Letters, vol. 91, pp. 082908, 2007.

205

[120] M.-K. Lee, C.-F. Yen, J.-J. Huang, and S.-H. Lin, "Electrical characteristics of postmetallization-annealed mocvd-tio[sub 2] films on ammonium sulfide-treated gaas," Journal of The Electrochemical Society, vol. 153, pp. F266, 2006.

[121] H.-S. Kim, I. Ok, Z. Manhong, C. Changhwan, L. Tackhwi, Z. Feng, G. Thareja,

Y. Lu, and J. C. Lee, "Ultrathin hfo2 (equivalent oxide thickness=1.1 nm) metal-oxide-semiconductor capacitors on n-gaas substrate with germanium passivation," Applied Physics Letters, vol. 88, pp. 252906, 2006.

[122] C. Changhwan, K. Chang-Yong, R. Se Jong, M. S. Akbar, S. A. Krishnan, Z.

Manhong, K. Hyoung-Sub, L. Tackhwi, I. Ok, Z. Feng, and J. C. Lee, "Aggressively scaled ultra thin undoped hfo2 gate dielectric (eot&lt;0.7 nm) with tan gate electrode using engineered interface layer," IEEE Electron Device Letters, vol. 26, pp. 454, 2005.

[123] G. K. Dalapati, T. Yi, L. Wei-Yip, M. Hoe Keat, and C. Byung Jin, "Electrical

and interfacial characterization of atomic layer deposited high-gate dielectrics on gaas for advanced cmos devices," IEEE Transactions on Electron Devices, vol. 54, pp. 1831, 2007.

[124] S. Koveshnikov, N. Goel, P. Majhi, H. Wen, M. B. Santos, S. Oktyabrsky, V.

Tokranov, R. Kambhampati, R. Moore, F. Zhu, J. Lee, and W. Tsai, "In0.53ga0.47as based metal oxide semiconductor capacitors with atomic layer deposition zro2 gate oxide demonstrating low gate leakage current and equivalent oxide thickness less than 1 nm," Applied Physics Letters, vol. 92, pp. 222904, 2008.

[125] O. In Jo, H. Kim, M. Zhang, F. Zhu, S. Park, J. Yum, H. Zhao, D. Garcia, P.

Majhi, N. Goel, W. Tsai, C. K. Gaspe, M. B. Santos, and J. C. Lee, "Metal gate: Hfo2 metal-oxide-semiconductor structures on high- indium-content ingaas substrate using physical vapor deposition," Applied Physics Letters, vol. 92, pp. 112904, 2008.

[126] K. Saito, Y. Jin, and M. Shimada, "Mos-diode characteristics with hfo2 gate

insulator deposited by ecr sputtering," Journal of the Electrochemical Society, vol. 151, pp. 328, 2004.

[127] P. W. Chye, C. Y. Su, I. Lindau, C. M. Garner, P. Pianetta, and W. E. Spicer,

"Photoemission studies of the initial stages of oxidation of gasb and inp," Surface Science, vol. 88, pp. 439, 1979.

[128] W. E. Spicer, I. Lindau, P. Skeath, and C. Y. Su, "Unified defect model and

beyond," Journal of Vacuum Science and Technology, vol. 17, pp. 1019, 1980.

206

[129] D. Y. Petrovykh, M. J. Yang, and L. J. Whitman, "Chemical and electronic properties of sulfur-passivated inas surfaces," Surface Science, vol. 523, pp. 231, 2003.

[130] H. F. Hsieh and H. C. Shih, "Studies of thin films grown on inas(111) and

gap(100) in hcl etches using x-ray diffraction methods," Materials Chemistry and Physics, vol. 44, pp. 203, 1996.

[131] J. Koomen, "Investigation of the most channel conductance in weak inversion,"

Solid-State Electronics, vol. 16, pp. 801, 1973. [132] V. Kilchytska, D. Lederer, P. Simon, N. Collaert, J. P. Raskin, and D. Flandre,

"Revised split c-v technique for mobility investigation in advanced devices," 2005 IEEE International SOI Conference (QSIC 2005) (IEEE Cat. No. 05CH37694), 2005, pp. 110.