[01.2

017]

Mod. 0809 2017-01 Rev.8

HE/UE910, UL865 Digital Voice Interface Application Note

80000NT10050A Rev. 7 – 2017-02-13

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SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE

NOTICE

While reasonable efforts have been made to assure the accuracy of this document, Telit assumes no liability resulting from any inaccuracies or omissions in this document, or from use of the information obtained herein. The information in this document has been carefully checked and is believed to be reliable. However, no responsibility is assumed for inaccuracies or omissions. Telit reserves the right to make changes to any products described herein and reserves the right to revise this document and to make changes from time to time in content hereof with no obligation to notify any person of revisions or changes. Telit does not assume any liability arising out of the application or use of any product, software, or circuit described herein; neither does it convey license under its patent rights or the rights of others. It is possible that this publication may contain references to, or information about Telit products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Telit intends to announce such Telit products, programming, or services in your country.

COPYRIGHTS

This instruction manual and the Telit products described in this instruction manual may be, include or describe copyrighted Telit material, such as computer programs stored in semiconductor memories or other media. Laws in the Italy and other countries preserve for Telit and its licensors certain exclusive rights for copyrighted material, including the exclusive right to copy, reproduce in any form, distribute and make derivative works of the copyrighted material. Accordingly, any copyrighted material of Telit and its licensors contained herein or in the Telit products described in this instruction manual may not be copied, reproduced, distributed, merged or modified in any manner without the express written permission of Telit. Furthermore, the purchase of Telit products shall not be deemed to grant either directly or by implication, estoppel, or otherwise, any license under the copyrights, patents or patent applications of Telit, as arises by operation of law in the sale of a product.

COMPUTER SOFTWARE COPYRIGHTS

The Telit and 3rd Party supplied Software (SW) products described in this instruction manual may include copyrighted Telit and other 3rd Party supplied computer programs stored in semiconductor memories or other media. Laws in the Italy and other countries preserve for Telit and other 3rd Party supplied SW certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or reproduce in any form the copyrighted computer program. Accordingly, any copyrighted Telit or other 3rd Party supplied SW computer programs contained in the Telit products described in this instruction manual may not be copied (reverse engineered) or reproduced in any manner without the express written permission of Telit or the 3rd Party SW supplier. Furthermore, the purchase of Telit products shall not be deemed to grant either directly or by implication, estoppel, or otherwise, any license under the copyrights, patents or patent applications of Telit or other 3rd Party supplied SW, except for the normal non-exclusive, royalty free license to use that arises by operation of law in the sale of a product.

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USAGE AND DISCLOSURE RESTRICTIONS

I. License Agreements

The software described in this document is the property of Telit and its licensors. It is furnished by express license agreement only and may be used only in accordance with the terms of such an agreement.

II. Copyrighted Materials

Software and documentation are copyrighted materials. Making unauthorized copies is prohibited by law. No part of the software or documentation may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, without prior written permission of Telit

III. High Risk Materials

Components, units, or third-party products used in the product described herein are NOT fault-tolerant and are NOT designed, manufactured, or intended for use as on-line control equipment in the following hazardous environments requiring fail-safe controls: the operation of Nuclear Facilities, Aircraft Navigation or Aircraft Communication Systems, Air Traffic Control, Life Support, or Weapons Systems (High Risk Activities"). Telit and its supplier(s) specifically disclaim any expressed or implied warranty of fitness for such High Risk Activities.

IV. Trademarks

TELIT and the Stylized T Logo are registered in Trademark Office. All other product or service names are the property of their respective owners.

V. Third Party Rights

The software may include Third Party Right software. In this case you agree to comply with all terms and conditions imposed on you in respect of such separate software. In addition to Third Party Terms, the disclaimer of warranty and limitation of liability provisions in this License shall apply to the Third Party Right software. TELIT HEREBY DISCLAIMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY “OTHER CODE”), AND THE USE OF ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE. NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EXERCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENSE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

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APPLICABILITY TABLE

PRODUCTS SW Versions HE910 Family

HE9101 12.00.xx3

HE910-GA 12.00.xx4

HE910-EUR 12.00.xx4

HE910-NAR 12.00.xx4

UE/UL Family UE910-EUR 12.00.xx4 UE910-NAR 12.00.xx4

UL865-EUR 12.00.xx4

UL865-NAR 12.00.xx4 UL865-N3G 12.00.xx4

Note: the features described in the present document are provided by the products equipped with the software versions equal or higher than the versions shown in the table. See also the Document History chapter. ___________________ 1 HE910 is the “type name” of the products marketed as HE910-G & HE910-DG

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CONTENTS

NOTICE ……………………………………………………………………………2

COPYRIGHTS ................................................................................................ 2

COMPUTER SOFTWARE COPYRIGHTS ...................................................... 2

USAGE AND DISCLOSURE RESTRICTIONS ............................................... 3 I. License Agreements ..................................................................... 3 II. Copyrighted Materials ................................................................... 3 III. High Risk Materials ....................................................................... 3 IV. Trademarks .................................................................................. 3 V. Third Party Rights ......................................................................... 3

APPLICABILITY TABLE ................................................................................ 4

CONTENTS .................................................................................................... 5

FIGURES LIST ............................................................................................... 6

TABLES LIST ................................................................................................. 6

1. INTRODUCTION .......................................................................... 7 Scope ........................................................................................... 7 Audience....................................................................................... 7 Contact Info and Support .............................................................. 7 Text Conventions .......................................................................... 8 Related Documents ...................................................................... 9

2. DVI OVERVIEW ......................................................................... 10

3. DVI BUS ..................................................................................... 11

4. DVI AT COMMANDS.................................................................. 12 AT#DVI ....................................................................................... 12 AT#DVIEXT ................................................................................ 13

5. DVI AT COMMANDS.................................................................. 14 Normal Mode (I2S) ...................................................................... 15

5.1.1. Module is Master ........................................................................ 15 5.1.2. Module is Slave .......................................................................... 19 5.2. Burst Mode (PCM) ...................................................................... 22 5.2.1. Module is Master ........................................................................ 22 5.2.2. Module is Slave .......................................................................... 25

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6. ANNEX ....................................................................................... 28 I2S Overview ............................................................................... 28 Schematic ................................................................................... 29

7. DOCUMENT HISTORY .............................................................. 30

FIGURES LIST

Fig. 1 Example of Digital Voice Interface Use ................................................................. 10 Fig. 2 Master and Slave Configurations .......................................................................... 11 Fig. 3 Telit Module/Codec Connections ........................................................................... 14 Fig. 4 DVI Configurations ................................................................................................ 14 Fig. 5 Module is Master/Normal mode/N bits per sample/Dual Mono .............................. 15 Fig. 6 Module is Master/Normal Mode/16 bits per sample/Dual Mono/=0 ............ 18 Fig. 7 Module is Slave/Normal Mode/24 bits per sample/Dual Mono/=0 .............. 21 Fig. 8 Module is Master/Burst mode/N bits per Sample/Mono Mode ............................... 22 Fig. 9 Module is Master/Burst Mode/16 bits per Sample/Mono Mode/=1 ............. 24 Fig. 10 Module is Slave/Burst Mode/N bits per Sample/Mono Mode ............................... 25 Fig. 11 Module is Slave/Burst Mode/16 bits per Sample/Mono Mode/=1 ............. 27 Fig. 12 I2S bus configurations ......................................................................................... 28 Fig. 13 Schematic for Reference Design ......................................................................... 29

TABLES LIST

Tab. 1 DVI Signals .......................................................................................................... 11 Tab. 2 DVI Configuration via AT#DVI command ............................................................. 12 Tab. 3 DVI Audio Format configuration via AT#DVIEXT command ................................. 13 Tab. 4 BitClockFrequency generated by the module in Master/Normal Mode ................. 16 Tab. 5 BitClockFrequency in Burst Mode ........................................................................ 22

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1. INTRODUCTION The present document provides the reader with a guideline concerning the setting and use of the Digital Voice Interface developed on the Telit’s modules families shown in the Applicability Table.

Scope This Application Note covers the configurations of the Digital Voice Interface, e.g.: the selections of the voice sampling frequency, the bit number of the voice sample, the audio formats, etc. In addition, the document shows some configurations of a popular Audio Codec connected to the Module. These activities are accomplished via I2S and I2C buses; the hardware characteristics of the two buses are beyond the scope of the document.

Audience The document is intended for those users that need to develop applications dealing with signal voice in digital format.

Contact Info and Support For general contact, technical support services, technical questions and report documentation errors contact Telit Technical Support at:

• TS-EMEA@telit.com • TS-AMERICAS@telit.com • TS-APAC@telit.com

Alternatively, use:

http://www.telit.com/support

For detailed information about where you can buy the Telit modules or for recommendations

on accessories and components visit:

http://www.telit.com

Our aim is to make this guide as helpful as possible. Keep us informed of your comments

and suggestions for improvements.

Telit appreciates feedback from the users of our information.

mailto:TS-EMEA@telit.commailto:TS-AMERICAS@telit.commailto:TS-APAC@telit.comhttp://www.telit.com/supporthttp://www.telit.com/

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Text Conventions

Danger – This information MUST be followed or catastrophic equipment

failure or bodily injury may occur.

Caution or Warning – Alerts the user to important points about integrating the

module, if these points are not followed, the module and end user equipment

may fail or malfunction.

Tip or Information – Provides advice and suggestions that may be useful

when integrating the module.

All dates are in ISO 8601 format, i.e. YYYY-MM-DD.

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Related Documents

• HE910 Hardware User Guide, 1vv0300925 • MAX9867 Ultra-Low Power Stereo Audio Codec, MAXIM • HE910/UE910/UL865 AT Commands Reference Guide, 80378ST10091A • UE910 Hardware User Guide, 1vv0301012 • UL865 Hardware User Guide, 1vv0301050

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2. DVI OVERVIEW Before dealing with the configuration and technical aspects of the Telit’ Digital Voice Interface (DVI) it is useful to illustrate briefly where and how this interface can be used, refer to Fig. 1 The voice coming from the downlink, in digital format, is captured by the dedicated software running on the Telit’s module and directed to the Digital Voice Interface. The Audio Codec decodes the voice and sends it to the speaker. The voice captured by the microphone is coded by the Audio Codec and directed through the Digital Voice Interface to the module that collects the received voice, in digital format, and sends it on the uplink.

Fig. 1 Example of Digital Voice Interface Use

NOTICE:

the Digital Voice Interface supports the Echo canceller functionality, which is

beyond the scope of the present document. Refer to document [3] for the

specific AT commands.

Audio Codec Telit Module

Digital Voice

Uplink

Downlink

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3. DVI BUS The physical DVI interface provided by the Telit’s modules is based on the I2S Bus. An overview of the standard I2S Bus is described in chapter 6.1.Tab. 1 summarizes the DVI signals and a short description for each one of them: refer to documents [1], [4], and [5] to have information on electrical characteristics and signals pin-out in accordance with the used module.

HEADLINE DESCRIPTION NOTE

Clock DVI_CLK Data Clock

Word Alignment DVI_WAO Frame Synchronism

serial audio data input DVI_RX Received Data

serial audio data output DVI_TX Transmitted Data

Tab. 1 DVI Signals

The figures below show the two configurations of the DVI interface relating to the Word Alignment and Clock signals. When the module is Master the Clock and Word Alignment signals (also called Word Alignment Output WAO) are generated by the module itself, otherwise, when it is Slave, both signals are generated by the connected Audio Device Codec. In general, before establishing a voice call it is possible to select one of the two configurations and in accordance with the selected setting, configure the module and the codec via the AT commands provided by Telit, refer to documents [3]. The next pages describe the use of these AT commands.

Fig. 2 Master and Slave Configurations

Telit

Module

Audio Device

Codec

Clock

Word Alignment

data input

Module = Master

data output

Telit

Module

Audio Device

Codec

Clock

Word Alignment

data input

data output

Module = Slave

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4. DVI AT COMMANDS Several DVI audio bus configurations are available via AT#DVI and AT#DVIEXT commands. The tables in the following sub-sections summarize their parameters; refer to documents [3] for AT commands syntax details.

AT#DVI AT#DVI command enables/disables the DVI interface, selects the DVI port, and sets the module in Master or Slave configuration. The following table shows the AT command parameters values.

AT#DVI =,,

0 disable DVI interface, factory setting for UE910 products 1 enable DVI interface, factory setting for HE901 and UL865 products 2 reserved

1 reserved 2 select DVI port 2

0 DVI slave 1 DVI master, factory setting

Tab. 2 DVI Configuration via AT#DVI command

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AT#DVIEXT AT#DVIEXT command sets the module in Normal or Burst DVI Audio Format:

• In Normal DVI Audio Format the WAO signal defines the left and right audio channel. • In Burst DVI Audio Format the WAO signal defines the beginning of the audio frame.

The following table shows the AT command parameters values.

DVI AUDIO FORMAT (MODE)

AT#DVIEXT ,, ,,

bit per sample

Normal (I2S)

1

factory setting

0 8 [KHz], factory setting

1 16 [KHz]

0 16 bits per sample factory setting

1 18 bits per sample

2 20 bits per sample

3 24 bits per sample

4 32 bits per sample

0 Mono

1 Dual Mono

In Dual Mono the same Data Word is transmitted on both audio channels (right and left). Factory setting.

0 the falling edge of the clock is used to shift out the next data to transmit. The received data bit is captured on the rising edge of the clock, factory setting.

1 reserved

Burst (PCM)

0 0 the falling edge of the clock is used to shift out the next data to transmit. The received data bit is captured on the rising edge of the clock.

1 the rising edge of the clock is used to shift out the next data to transmit. The received data bit is captured on the falling edge of the clock.

Tab. 3 DVI Audio Format configuration via AT#DVIEXT command

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5. DVI AT COMMANDS The next chapters show examples concerning the audio formats provided by the DVI audio bus in Master and Slave configurations. All the following setting examples are performed using the hardware configuration shown in Fig. 3. I2C bus is used to configure the MAX9867 Codec [2]: the user by means of suitable AT commands can control the codec. The DVI bus provides the voice connection between the two devices.

Fig. 3 Telit Module/Codec Connections

The setting examples are organized as shown in the figure below.

Fig. 4 DVI Configurations

____________________ 2 The following examples use the MAX9867 Codec, see chapter 6.2 for a schematic reference design. In general, the user can use any codec compliant with the technical requirements of the Telit’s modules.

Telit

Module

MAX9867

Codec

Clock

Word Alignment

data input

data output

SDA

SCL

I2C bus

DVI bus based on

I2S bus

User DTE

GPIO

System CLK

Normal Mode Burst Mode

Audio Format Mode

Module Master Module Slave Module Master Module Slave

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Normal Mode (I2S)

5.1.1. Module is Master The Fig. 5 shows a timing diagram that refers to the module in the role of master. In this case, WAO and CLK signals are generated by the module. The WAO signal defines the frame of the two audio channels: left and right.

Fig. 5 Module is Master/Normal mode/N bits per sample/Dual Mono

When module is Master the BitClockFrequency (CLK) is provided by the following expression:

eRateAudioSamplberChannelNumtDataWordBiequencyBitClockFr ××=

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Refer to Tab. 4 for the BitClockFrequency generated by the Module.

DATAWORDBIT AUDIO CHANNELS

AUDIOSAMPLERATE

8 KHz 16 KHz

BitClockFrequency in KHz

0 16 2 256 512

1 18 2

3843 768

2 20 2

3 24 2

4 32 2 512 1024

Tab. 4 BitClockFrequency generated by the module in Master/Normal Mode

Here are the lists of AT commands used to set the module in Master Normal (I2S) Mode, and configure the codec in accordance with the module setting. After each command is described the uses parameters values meaning. ____________________ 3 The module generates 384 or 768 KHz also when the audio sample has 16 or 20 bits. In these configurations only 16 or 20 bits are taken in consideration, all other bits must be discarded.

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Configure the Module in Master Normal (I2S) Mode AT#DVI=1,2,1 OK 1 enable DVI interface 2 use DVI port 2 (mandatory) 1 set the module as Master (factory setting) AT#DVIEXT=1,0,0,1,0 OK 1 Normal Mode (factory setting) 0 sample rate 8 KHz (factory setting) 0 16 bits per sample (factory setting) 1 Dual Mono, the same Data Word is transmitted on both audio channels (factory setting) 0 the falling edge of the clock is used to shift out the next data to transmit; the received data bit is captured on the rising edge of the clock. (factory setting)

Configure the codec in Slave Normal (I2S) Mode AT#I2CWR=X,Y,30,4,19 >00109000100A330000330C0C09092424400060 OK X GPIO number used as SDA, refer to [3] Y GPIO number used as SCL, refer to [3] 30 Device address on I2C, refer to [2] 4 Register address from which start the writing, refer to [2] 19 number of bytes to write >00109000…..refer to [2] AT#I2CWR=X,Y,30,17,1 >8A OK X GPIO number used as SDA, refer to [3] Y GPIO number used as SCL, refer to [3] 30 Device address on I2C, refer to [2] 17 Register address where write data, refer to [2] 1 number of bytes to write >8A, refer to [2]

DVI bus

I2C bus

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The Fig. 6 shows the screenshot of the timing diagram, captured by a logic analyzer, using the above described module/codec setting. The CLK (256 KHz) and WAO signals are generated by the module. Left channel: : Data transitions occur on the falling edge of the CLK : Data are latched on the rising edge of the CLK Right channel: : Data transitions occur on the falling edge of the CLK : Data are latched on the rising edge of the CLK

Fig. 6 Module is Master/Normal Mode/16 bits per sample/Dual Mono/=0

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5.1.2. Module is Slave Here are the lists of the AT commands used to set the module in Slave Normal (I2S) Mode, and configure the codec in accordance with the module setting. After each command is described the used parameters values meaning.

Configure the module in Slave Normal (I2S) Mode AT#DVI=1,2,0 OK 1 enable DVI interface 2 use DVI port 2 (mandatory) 0 set the module as Slave AT#DVIEXT=1,0,3,1,0 OK 1 Normal Mode (factory setting) 0 sample rate 8 KHz (factory setting) 3 24 bits per sample 1 Dual Mono, the same Data Word is transmitted on both audio channels (factory setting) 0 the falling edge of the clock is used to shift out the next data to transmit; the received data bit is captured on the rising edge of the clock. (factory setting)

DVI bus

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Configure the codec in Master Normal (I2S) Mode AT#I2CWR=X,Y,30,4,19 >001010009002330000330C0C09092424400060 OK X GPIO number used as SDA Y GPIO number used as SCL 30 Device address on I2C 4 Register address from which start the writing 19 number of bytes to write >00101000…..refer to [2] AT#I2CWR=X,Y,30,17,1 >8A OK X GPIO number used as SDA Y GPIO number used as SCL 30 Device address on I2C 17 Register address where write data 1 number of bytes to write >8A, refer to [2]

NOTICE:

the codec is in Master configuration and generates a clock equal to 384

KHz. On the module the selected number of bits per sample is 24, see Tab.

4

I2C bus

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The Fig. 7 shows the screenshot of the timing diagram, captured by a logic analyzer, using the above described module/codec setting. The CLK (384 KHz) and WAO signals are generated by the codec. Left channel: : Data transitions occur on the falling edge of the CLK : Data are latched on the rising edge of the CLK Right channel: : Data transitions occur on the falling edge of the CLK : Data are latched on the rising edge of the CLK

Fig. 7 Module is Slave/Normal Mode/24 bits per sample/Dual Mono/=0

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5.2. Burst Mode (PCM)

5.2.1. Module is Master The Fig. 8 shows a timing diagram that refers to the module in the role of master. In this case, the WAO and CLK signals are generated by the module. The WAO signal defines the frame of the audio channel.

Fig. 8 Module is Master/Burst mode/N bits per Sample/Mono Mode

When module is Master the BitClockFrequency (CLK) is provided by the following expression:

( ) eRateAudioSampltDataWordBiequencyBitClockFr ×+= 2 Refer to Tab. 5 for the BitClockFrequency generated by the module in accordance with the connected MAX9867 codec used in the examples.

DATAWORDBIT AUDIOSAMPLERATE

8 KHz 16 KHz

BitClockFrequency in KHz

0 16 (+ 24 ) 144 288

4 32 (+ 2) 272 544

Tab. 5 BitClockFrequency in Burst Mode

______________________ 4 The width of the WAO pulse is 2 CLK.

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Here are the lists of AT commands used to set the module in Master Burst (PCM) Mode, and configure the codec in accordance with the current module setting. After each command is described the used parameters values meaning.

Configure the module in Master Burst (PCM) Mode. AT#DVI=1,2,1 OK 1 enable DVI 2 use DVI port 2 (mandatory) 1 DVI Master (factory setting) AT#DVIEXT=0,0,0,0,1 OK 0 Burst Mode 0 sample rate 8 KHz (factory setting) 0 16 bits per sample (factory setting) 0 Mono Mode 1 the rising edge of the clock is used to shift out the next data to transmit, the received data bit is captured on the falling edge of the clock

Configure the codec in Slave Burst (PCM) Mode. AT#I2CWR=X,Y,30,4,19 > 00109000600A330000330C0C09092424400060 OK X GPIO number used as SDA Y GPIO number used as SCL 30 Device address on I2C 4 Register address from which start the writing 19 number of bytes to write >00109000…..refer to [2] AT#I2CWR=X,Y,30,17,1 >8A OK X GPIO number used as SDA Y GPIO number used as SCL 30 Device address on I2C 17 Register address where write data 1 number of bytes to write >8A refer to [2]

DVI bus

I2C bus

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The Fig. 9 shows the screenshot of the timing diagram, captured by a logic analyzer, using the above described module/codec setting. The CLK (144 KHz) and WAO signals are generated by the module. : Data transitions occur on the rising edge of the CLK : Data are latched on the falling edge of the CLK

Fig. 9 Module is Master/Burst Mode/16 bits per Sample/Mono Mode/=1

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5.2.2. Module is Slave The Fig. 10 shows a timing diagram that refers to the codec in master configuration. In this case, the WAO and CLK signals are generated by the codec.

Fig. 10 Module is Slave/Burst Mode/N bits per Sample/Mono Mode

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Here are the lists of AT commands used to set the module in Slave Burst (PCM) Mode, and configure the codec in accordance with the current module setting. After each command is described the used parameters values meaning.

Configure the module in Slave Burst (PCM) Mode. AT#DVI=1,2,0 OK 1 enable DVI interface 2 use DVI port 2 (mandatory) 0 set the module as Slave AT#DVIEXT=0,0,0,0,1 OK 0 Burst Mode 0 sample rate 8 KHz (factory setting) 0 16 bits per sample (factory setting) 0 Mono Mode 1 the rising edge of the clock is used to shift out the next data to transmit, the received data bit is captured on the falling edge of the clock

Configure the codec in Master Burst (PCM) Mode. AT#I2CWR=X,Y,30,4,19 > 00101000A40A330000330C0C09092424400060 OK X GPIO number used as SDA Y GPIO number used as SCL 30 Device address on I2C 4 Register address from which start the writing 19 number of bytes to write >00101000…..refer to [2] AT#I2CWR=X,Y,30,17,1 >8A OK X GPIO number used as SDA Y GPIO number used as SCL 30 Device address on I2C 17 Register address where write data 1 number of bytes to write >8A refer to [2]

DVI bus

I2C bus

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The Fig. 11 shows the screenshot of the timing diagram, captured by a logic analyzer, using the above described module/codec setting. The CLK (384 KHz) and WAO signals are generated by the codec. : Data transitions occur on the rising edge of the CLK : Data are latched on the falling edge of the CLK

Fig. 11 Module is Slave/Burst Mode/16 bits per Sample/Mono Mode/=1

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6. ANNEX I2S Overview

This chapter provides a short description of the standard I2S bus. This standard suitably modified is used by the DVI interface implemented on the Telit’s modules. The standard I2S is an electrical serial bus designed for connecting digital audio devices. This popular serial bus has been developed by Philips® in 1986 as a 3-wire bus for interfacing to audio chips such as codecs. It is a simple data interface, without any form of address or device selection. Refer to Fig. 12: the I2S design handles audio data separately from clock signals. On an I2S bus, there is only one bus master and one transmitter. In high-quality audio applications involving a Codec, the Codec is typically the master so that it has precise control over the I2S bus clock. An I2S bus design consists of the following serial bus lines:

• SD: Serial Data • WS: Word Select • Serial Clock: SCK

The I2S bus carries two channels (left and right) 8 bit long, which are typically used to carry stereo audio data streams. The data alternates between left and right channels, as controlled by the word select signal driven by the bus master.

Fig. 12 I2S bus configurations

Transmitter

Receiver

clock SCK

word select WS

data SD

Transmitter = Master

Transmitter

Receiver

clock SCK

word select WS

data SD

Receiver = Master

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Schematic A schematic example of an interface between the Telit’s modules and the MAX9867 CODEC could be the following:

Fig. 13 Schematic for Reference Design

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7. DOCUMENT HISTORY

Revision Date Products/SW Versions Changes

0 2011-07-11 / First issue

1 2012-02-16 / The present revision supersedes Rev. 0

2 2013-05-31 / Updated all the screenshots of the timing diagrams. Added the AT commands list to set the codec in Slave-Burst (PCM) Mode configuration

3 2013-06-20 / The previous document title “HE910 Family Digital Voice Interface” has been changed in HE/UE910 Digital Voice Interface. In accordance with the new title, the Applicability Table has been updated.

4 2013-09-30 / The previous document title “HE/UE910 Digital Voice Interface” has been changed in “HE/UE910, UL865 Digital Voice Interface”.

Products added: UL865-EUR / 12.00.xx4 UL865-NAR / 12.00.xx4

/

5 2014-03-17 / In the Applicability Table have been corrected the wrong products, turning them into UL865-EUR / 12.00.xx4 and UL865-NAR / 12.00.xx4

Products added: UL865-N3G / 12.00.xx4

/

6 2014-04-16 / The note about the Echo canceller has been added in chapter 2. The chapters numbering/naming has been reorganized.

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7 2017-02-13 / 2017 Template applied

[01.2

017]

Mod. 0809 2017-01 Rev.8

NoticeCopyrightsComputer Software CopyrightsUsage and Disclosure RestrictionsAPPLICABILITY TABLECONTENTSFIGURES LISTTABLES LIST1. Introduction1.1. Scope1.2. Audience1.3. Contact Info and Support1.4. Text Conventions1.5. Related Documents

2. DVI Overview3. DVI Bus4. DVI AT Commands4.1. AT#DVI4.2. AT#DVIEXT

5. DVI AT Commands5.1. Normal Mode (I2S)5.1.1. Module is Master5.1.2. Module is Slave

5.2. Burst Mode (PCM)5.2.1. Module is Master5.2.2. Module is Slave

6. Annex6.1. I2S Overview6.2. Schematic

7. Document History