HDL Butterworth Filter

This example illustrates how to generate HDL code for a 5th order Butterw orth f ilter. The cutoff-frequency for this f ilter is very

low relative to the sample rate, leading to a f ilter that is diff icult to make practical. Also, small input (8-bit) and output (9-bit)

w ord sizes cause the quantized f ilter to require scaling to be realizable.

Design the Filter

Use the CD sampling rate of 44.1 kHz and a cut-off frequency of 500 Hz. First, create the f ilter design object, then create the

double-precision f ilter. Convert it from the default structure (DF2SOS) to the desired structure, DF1SOS. Finally, examine the

response in log frequency using fvtool.

Fs = 44100;

Fn = Fs/2;

F3db = 500;

filtdes = fdesign.lowpass('n,f3db', 5, F3db, Fs);

Hd = design(filtdes,'butter');

Hd = convert(Hd, 'df1sos');

fvtool(Hd, 'Fs', Fs, 'FrequencyScale', 'log');

Create the Quantized Filter

Set the f ilter object to f ixed-point mode to quantize it. Assume 8-bit f ixed-point input and output data w ith 12-bit coeff icients and

20-bit adders and states. Check the response w ith fvtool.

Hd.arithmetic = 'fixed';

Hd.InputWordLength = 8;

Hd.InputFracLength = 7;

Hd.OutputWordLength = 9;

Hd.OutputMode = 'SpecifyPrecision';

Hd.OutputFracLength = 7;

Hd.CoeffWordLength = 12;

Hd.AccumWordLength = 20;

Hd.NumStateWordLength = 20;

Hd.DenStateWordLength = 20;

Hd.CastBeforeSum = false;

Hd.RoundMode = 'nearest';

Hd.OverflowMode = 'wrap';

fvtool(Hd, 'Fs', Fs, 'FrequencyScale', 'log');

Requantize the Filter

In the plot above, fvtool show s that the quantized passband is approximately 2 dB low er than the desired response. Adjust the

coeff icient w ord length from 12 to 16 to get the quantized response closer to the reference double-precision response and

zoom in on the passband response. The quantized f ilter is now just over 0.1 dB low er than the reference f ilter.

Hd.CoeffWordLength = 16;

fvtool(Hd, 'Fs', Fs, 'FrequencyScale', 'log');

axis([0 1.0 -1 1]);

Examine the Scale Values

A key step for hardw are realization of the f ilter design is to check w hether the scale values are reasonable and adjust the

scale value if needed. First, examine the quantized scale values relative to the input specif ication--an 8-bit value w ith fraction

length of 7 bits. Since the f irst tw o scale values are smaller than the input settings, most of the input values are quantized

aw ay. To correct this, the f ilter needs to be scaled.

scales = Hd.scalevalues .* 2̂ Hd.InputFracLength

% Now scale the filter using the frequency domain infinity norm.

scale(Hd,'Linf');

% After scaling, the scale value are all one in this case.

scales = Hd.scalevalues

scales =

0.1589

0.1536

4.4043

128.0000

scales =

1

1

1

1

Generate HDL Code from the Quantized Filter

Starting w ith the correctly quantized f ilter, generate VHDL or Verilog code. You have the option of generating a VHDL or

Verilog test bench to verify that the HDL design matches the MATLAB filter.

Create a temporary w ork directory. Generate VHDL code for the f ilter and open the generated f ile in the editor.

To generate Verilog instead, change the value of the property 'TargetLanguage', from 'VHDL' to 'Verilog'.

workingdir = tempname;

generatehdl(Hd,'Name', 'hdlbutter', 'TargetLanguage', 'VHDL',...

'TargetDirectory', workingdir);

edit(fullfile(workingdir, 'hdlbutter.vhd'));

### Starting VHDL code generation process for filter: hdlbutter

### Starting VHDL code generation process for filter: hdlbutter

### Generating: <a

href="matlab:edit('C:\TEMP\R2013ad_470_3888\tp8a8b83fe_b7a9_42aa_a808_863b429e17b1\

hdlbutter.vhd')">C:\TEMP\R2013ad_470_3888\tp8a8b83fe_b7a9_42aa_a808_863b429e17b1\hd

lbutter.vhd</a>

### Starting generation of hdlbutter VHDL entity

### Starting generation of hdlbutter VHDL architecture

### First-order section, # 1

### Second-order section, # 2

### Second-order section, # 3

### HDL latency is 2 samples

### Successful completion of VHDL code generation process for filter: hdlbutter

Generate a Test Bench from the Quantized Filter

Since the passband of this f ilter is so low relative to the sampling rate, a custom input stimulus is a better w ay to test the f ilter

implementation. Build the test input w ith one cycle of each of 50 to 300 Hz in 50 Hz steps.

Generate a VHDL test bench to verify that the results match the MATLAB results exactly.

After generating the test bench, open the generated f ile in the editor.

userstim = [];

for n = [50, 100, 150, 200, 250, 300]

userstim = [ userstim, sin(2*pi*n/Fs*(0:Fs/n))];

end

generatehdl(Hd, 'Name', 'hdlbutter',...

'TargetLanguage', 'VHDL',...

'TargetDirectory', workingdir, ...

'GenerateHDLTestbench', 'on', ...

'TestBenchUserStimulus', userstim);

edit(fullfile(workingdir, 'hdlbutter_tb.vhd'));

### Starting VHDL code generation process for filter: hdlbutter

### Starting VHDL code generation process for filter: hdlbutter

### Generating: <a

href="matlab:edit('C:\TEMP\R2013ad_470_3888\tp8a8b83fe_b7a9_42aa_a808_863b429e17b1\

hdlbutter.vhd')">C:\TEMP\R2013ad_470_3888\tp8a8b83fe_b7a9_42aa_a808_863b429e17b1\hd

lbutter.vhd</a>

### Starting generation of hdlbutter VHDL entity

### Starting generation of hdlbutter VHDL architecture

### First-order section, # 1

### Second-order section, # 2

### Second-order section, # 3

### HDL latency is 2 samples

### Successful completion of VHDL code generation process for filter: hdlbutter

### Starting generation of VHDL Test Bench

### Generating input stimulus

### Done generating input stimulus; length 2166 samples.### Generating Test bench:

<a

href="matlab:edit('C:\TEMP\R2013ad_470_3888\tp8a8b83fe_b7a9_42aa_a808_863b429e17b1\

hdlbutter_tb.vhd')">C:\TEMP\R2013ad_470_3888\tp8a8b83fe_b7a9_42aa_a808_863b429e17b1

\hdlbutter_tb.vhd</a>

### Creating stimulus vectors...

### Done generating VHDL Test Bench

Generate HDL Code and Test Bench Using FDHDLTool

HDL code and its test bench can optionally be generated using the FDHDLTOOL command that opens the dialog that lets you

customize and generate Verilog or VHDL code and test benches for a copy of the quantized f ilter.

The GUI is customized to f ilter 'Hd' in such a w ay that only the relevant w idgets are available for setting. To generate HDL and

testbench you should f irst go to the w orking directory by cd(w orkingdir) and then call the FDHDLTOOL command.

fdhdltool(Hd)

You can modify the default settings and click Generate to generate HDL and/or testbench.

ModelSim Simulation Results

The follow ing display show s the ModelSim HDL simulator after running the VHDL test bench. Compare the ModelSim result w ith

the MATLAB result below .

xrange = (0:length(userstim) - 1);

y = filter(Hd, userstim);

subplot(2,1,1); plot(xrange, userstim);

axis([0 length(userstim) -1.1 1.1]);

title('HDL Butterworth filter in Stimulus.');

xlabel('Sample #');

subplot(2,1,2); plot(xrange, y);

axis([0 length(userstim) -1.1 1.1]);

title('HDL Butterworth filter out Response.');

xlabel('Sample #');

Conclusion

You designed a double-precision Butterw orth f ilter to meet the given specif ication. You then quantized the f ilter and discovered

problems. Requantizing the coeff icients and scaling the f ilter corrected these problems. You then generated VHDL filter code

and VHDL test bench.

You can use the ModelSim HDL Simulator, to verify these results. You can also experiment w ith VHDL and Verilog for both

filters and test benches.