hcs12 timer.pdf

102
Chapter 8 HCS12 Timer Functions

description

hcs12 timer, How to program HCS12 microcontroller

Transcript of hcs12 timer.pdf

Page 1: hcs12 timer.pdf

Chapter 8

HCS12 Timer Functions

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Why are Timer Functions Important?y p• It is very difficult and impossible to implement the

following applications without a timer function:g pp– Time delay creation and measurement– Period and pulse width measurement

Frequency measurement– Frequency measurement– Event counting– Arrival time comparison– Time-of-day tracking– Periodic interrupt generation– Waveform generationg

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The HCS12 Timer System (1 of 2)y• The HCS12 has a standard timer module (TIM) that consists of:

– Eight channels of multiplexed input capture and output compare functions.– 16-bit pulse accumulator Ap– 16-bit timer counter– The TIM block diagram is shown in Figure 8.1.

• The HCS12 devices in the automotive family have implemented an Enhanced Capture Timer module (ECT). The ECT module contains:p ( )

– All the features contained in the TIM module– One 16-bit buffer register for each of the input capture channels– Four 8-bit pulse accumulator– A 16-bit Modulus Down Counter with 4-bit prescalerp– Four user selectable delay counters for increasing input noise immunity

• The TIM (of course ECT also) shares the eight Port T pins (IOC0…IOC7).

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PrescalerInput Capture

Channel 0Bus clock

The HCS12 Timer System (2 of 2)

16-bit counter

Input CaptureOutput compare

Input CaptureOutput compare

Channel 1

Channel 2

IOC0

IOC1Timer overflow

interrupt

Input CaptureOutput compare

Channel 2

Input CaptureOutput compare

Channel 3

IOC2

IOC3

TC0 interrupt

TC1 interrupt

TC2 i t t Output compare

Input CaptureOutput compare

Channel 4

C

Channel 5

Registers

IOC4

TC2 interrupt

TC3 interrupt

TC4 interrupt

TC5 interrupt Input CaptureOutput compare

Input CaptureOutput compare

Channel 6

IOC5

IOC6

TC5 interrupt

TC6 interrupt

TC7 interrupt

PA overflowi t t

Input CaptureOutput compare

Channel 716-bit Pulseaccumulator A

IOC7

interruptPA inputinterrupt

Figure 8.1 HCS12 Standard Timer (TIM) block diagram

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Timer Counter Register (TCNT)g ( )• Required for input capture and output compare

functionsfunctions• Must be accessed in one 16-bit operation in

order to obtain the correct valueorder to obtain the correct value• Three other registers related to the operation of

the TCNT: TSCR1, TSCR2, TFLG2.the TCNT: TSCR1, TSCR2, TFLG2.

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7 6 5 4 3 2 1 0

Timer System Control Register 1 (TSCR1)TEN TSWAI TSFRZ TFFCA 0 0 0 0value

after reset 0 0 0 0 0 0 0 0

TEN -- timer enable bit

0 = disable timer; this can be used to save power consumption1 ll i f i ll

• The contents of TSCR1 are h i Fi 8 2 1 = allows timer to function normally

TSWAI -- timer stops while in wait mode bit0 = allows timer to continue running during wait mode1 = disables timer when MCU is in wait mode

TSFRZ -- timer and modulus counter stop while in freeze mode

shown in Figure 8.2.• Setting and clearing the bit 7

of TSCR1 will start and stop the counting of the TCNT 0 = allows timer and modulus counter to continue running while in

freeze mode1 = disables timer and modulus counter when MCU is in freeze mode

TFFCA -- timer fast flag clear all bit0 = allows timer flag clearing to function normally

the counting of the TCNT.• Setting the bit 4 will enable

fast timer flag clear function. If this bit is clear, then the user g g y

1 = For TFLG1, a read from an input capture or a write to the output compare channel causes the corresponding channel flag, CnF, to be cleared. For TFLG2, any access to the TCNT register clears the TOF flag. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the PAFLG

i t A t th PACN1 d PACN0 i t l th

,must write a one to a timer flag in order to clear it.

register. Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register.

Figure 8.2 Timer system control register 1 (TSCR1)

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Timer System Control Register 2 (TSCR2)(1 of 2)

• Bit 7 is the TCNT overflow interrupt enable bit• Bit 7 is the TCNT overflow interrupt enable bit.• TCNT can be reset to 0 when TCNT equals TC7 by

setting bit 3 of TSCR2.• The clock input to TCNT can be prescaled by a factor

selecting by bits 2 to 0 of TSCR2.Th t t f TSCR2 h i Fi 8 2• The contents of TSCR2 are shown in Figure 8.2.

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Timer System Control Register 2 (TSCR2)

7 6 5 4 3 2 1 0 Table 8.1 Timer counter prescale factor

y g ( )(2 of 2)

TOI 0 0 0 TCRE PR2 PR1 PR0valueafter reset 0 0 0 0 0 0 0 0

TOI -- timer overflow interrupt enable bit 0 = interrupt inhibited

1 = interrupt requested when TOF flag is set

PR2 PR1 PR0 Prescale Factor

0000

0011

0101

1248 1 = interrupt requested when TOF flag is set

TCRE -- timer counter reset enable bit 0 = counter reset inhibited and counter free runs 1 = counter reset by a successful output compare 7 If TC7 = $0000 and TCRE = 1, TCNT stays at $0000 continuously. If TC7 = $FFFF and TCRE = 1, TOF will never

b t h TCNT ll f $FFFF t $0000

1111

0011

0101

8163264

128

be set when TCNT rolls over from $FFFF to $0000.

Figure 8.3 Timer system control register 2 (TSCR2)

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Timer Interrupt Flag 2 Register (TFLG2)p g g ( )

• Only bit 7 (TOF) is implemented. Bit 7 will be set whenever TCNT overflows.

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Input Capture Functions (1 of 2)• Physical time is often represented by the contents of the main timer• Physical time is often represented by the contents of the main timer.• The occurrence of an event is represented by a signal edge (rising

or falling edge).• The time when an event occurs can be recorded by latching theThe time when an event occurs can be recorded by latching the

count of the main timer when a signal edge arrives as illustrated in Figure 8.4.

• The HCS12 has eight input capture channels. Each channel has a g p p16-bit capture register, an input pin, edge-detection logic, and interrupt generation logic.

• Input capture channels share most of the circuit with output compare f ti F thi th t b bl d i lt l

Rising edge Falling edge

or

functions. For this reason, they cannot be enabled simultaneously.

Figure 8.4 Events represented by signal edges

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Input Capture Functions (2 of 2)• The selection of input capture and output compare is done by programming• The selection of input capture and output compare is done by programming

the TIOS register. • The contents of the TIOS register are shown in Figure 8.5. Setting a bit

select the output compare function. Otherwise, the input capture function is selected.

7 6 5 4 3 2 1 0

IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0valueafter reset 0 0 0 0 0 0 0 0

IOS[7:0] -- Input capture or output compare channel configuration bits

selected.

Figure 8.5 Timer input capture/output compare select register (TIOS)

0 = The corresponding channel acts as an input capture 1 = The corresponding channel acts as an output compare

• The following instruction will enable the output compare channels 7...4 and g p pinput capture channel 3…0:

movb #$F0,TIOS

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Timer Port Pins • Each port pin can be used as a general I/O pin

when timer function is not selectedwhen timer function is not selected.• Pin 7 can be used as input capture 7, output

compare 7 action and pulse accumulator inputcompare 7 action, and pulse accumulator input.• When a timer port pin is used as a general I/O

pin, its direction is configured by the DDRTpin, its direction is configured by the DDRT register.

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Timer Control Register 3 and 47 6 5 4 3 2 1 0

EDG7 B EDG7 A EDG6 B EDG6 A EDG5 B EDG5 A EDG4 B EDG4 Avalueafte r rese t 0 0 0 0 0 0 0 0

• The signal edge to be captured is

7 6 5 4 3 2 1 0

EDG3 B EDG3 A EDG2 B EDG2 A EDG1 B EDG1 A EDG0 B EDG0 A

0 0 0 0 0 0 0 0

(a) Tim er co ntro l registe r 3 (TCTL3 )selected by TCTL3 and TCTL4.

• The edge to be captured is selected 0 0 0 0 0 0 0 0

(b) Tim er co ntro l regis te r 4 (TCTL4 )

EDGnB EDGnA -- Edge co nfiguratio n

0 0 C t di bl d

captured is selected by two bits. The user can choose to capture the rising

Figure 8 .5 Tim er co ntro l regis te r 3 and 4

0 0 : Capture disabled0 1 : Capture o n ris ing edges o nly1 0 : Capture o n falling edges o nly1 1 : Capture o n bo th edges

edge, falling edge, or both edges.

Figure 8 .5 Tim er co ntro l regis te r 3 and 4

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Timer Interrupt Enable Register (TIE)p g ( )• The arrival of a signal edge may optionally

generate an interrupt to the CPUgenerate an interrupt to the CPU. • The enabling of the interrupt is controlled by the

Timer Interrupt Enable Register

7 6 5 4 3 2 1 0

C7I C6I C5I C4I C3I C2I C1I C0I

Timer Interrupt Enable Register.

reset: 0 0 0 0 0 0 0 0

C7I-C0I: input capture/output compare interrupt enable bits 0 = interrupt disabled 1 = interrupt enabled

Figure 8.7 Timer interrupt enable register (TIE)

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Timer Interrupt Flag 1 Register (TFLG1)p g g ( )• Whenever a signal edge arrives, the associated

timer interrupt flag will be set to 1

7 6 5 4 3 2 1 0

timer interrupt flag will be set to 1.

C7F C6F C5F C4F C3F C2F C1F C0Freset: 0 0 0 0 0 0 0 0

CnF: input capture/output compare interrupt flag bits 0 = interrupt condition has not occurred 1 = interrupt condition has occurred

Figure 8.8 Timer interrupt flag register 1 (TFLG1)

1 = interrupt condition has occurred

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How to Clear a Timer Flag Bit• In normal mode write a 1 to the flag bit to be cleared• In normal mode, write a 1 to the flag bit to be cleared.• Method 1

– Use the BCLR instruction with a 0 at the bit position(s) corresponding to the flag(s) to be cleared. For example,

BCLR TFLG1, $FE

will clear the C0F flag. g• Method 2

– Use the movb instruction with a 1 at the bit position (s) corresponding to the flag (s) to be cleared. For example,

movb #$01,TFLG1

will clear the C0F flag.• When fast timer flag clear function is enabled, see Figure 8.1.

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one period

Applications of Input Capture FunctionE t i l ti p

(a) Capture two rising edges

• Event arrival time recording

• Period measurement: need to capture the main ( ) p g g

one periodneed to capture the main timer values corresponding to two consecutive rising or

(b) Capture two falling edges

Figure 8.9 Period measurement by capturing two consecutive edges

consecutive rising or falling edges

- Pulse width measurement: need to capture the rising and falling edgesPulse width

Rising edge Falling edge

Figure 8.10 Pulse-width measurement using input capture

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Input Capture• Interrupt generation: Each input capture function can be used as an edge-

sensitive interrupt source

e1 e2 e3 e4 ei ej... ...

sensitive interrupt source.• Event counting: count the number of signal edges arrived during a period

Start ofinterval

End ofinterval

Figure 8.11 Using an input-capture function for event counting

- Time reference: often used in conjunction with an output compare functionTime t0 Time t0 + delay

Time of reference Time to activate(set up by signal edge) output signal

(set up by output compare)Figure 8.12 A time reference application

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Duty Cycle Measurement

T

y y

ΔT

T

duty cycle =ΔT

T* 100%

Figure 8.13 Definition of duty cycle

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Phase Difference Measurement

T

ΔT

signal S1

ΔT

signal S2

phase difference =ΔT

* 360ophase difference T

360

Figure 8.14 Phase difference definition for two signals

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Period Measurement (1 of 2)• Example 8.2 Use the IC0 to measure the period of an unknown

signal. The period is known to be shorter than 128 ms. Assume that the E clock frequency is 24 MHz. Use the number of clock cycles as the unit of the period.

• Solution:• Solution: • Since the input-capture register is 16-bit, the longest period of the

signal that can be measured with the prescaler to TCNT set to 1 is: 216 ÷ 24 MHz = 216 x (1/24 MHz) = 2 73 ms Note: Period=(1/24 MHz)2 ÷ 24 MHz 2 x (1/24 MHz) 2.73 ms. Note: Period=(1/24 MHz)

• To measure a period that is equal to 128 ms, we have two options: – Set the prescale factor to 1 and keep track of the number of times the

timer counter overflows.– Set the prescale factor to 64 and do not keep track of the number of

times the timer counter overflows. • We will set the prescale factor to TCNT to 64. The logic flow for

measuring the signal period is shown in Figure 8 16measuring the signal period is shown in Figure 8.16.

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Start

Period Measurement (2 of 2)

Choose to capture the rising edgeSet the timer counter prescale factor to 16Enable the timer counter

Clear the C0F flagClear the C0F flag

C0F = 1?

yes

no

yes

Saved the captured first edgeClear the C0F flag

noC0F = 1?

no

yes

Take the difference of the second and thefirst captured edgesp g

Stop

Figure 8.16 Logic flow of period measurement program

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#include "c:\miniide\hcs12 inc"

Assembly Program for Period Measurement#include c:\miniide\hcs12.inc

org $1000edge1 ds.b 2 ; memory to hold the first edgeperiod ds.b 2 ; memory to store the period

org $1500org $1500movb #$90,TSCR1 ; enable timer counter and enable fast timer flags clearbclr TIOS,IOS0 ; enable input-capture 0movb #$06,TSCR2 ; disable TCNT overflow interrupt, set prescaler to 64movb #$01 TCTL4 ; capture the rising edge of PT0 signalmovb #$01,TCTL4 ; capture the rising edge of PT0 signalmovb #C0F,TFLG1 ; clear the C0F flagbrclr TFLG1,C0F,* ; wait for the arrival of the first rising edgeldd TC0 ; save the first edge and clear the C0F flagstd edge1std edge1brclr TFLG1,C0F,* ; wait for the arrival of the second edgeldd TC0subd edge1 ; compute the periodstd periodstd periodswiend

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C Program for Period Measurement#include "c:\egnu091\include\hcs12.h"void main(void){

g

{unsigned int edge1, period;TSCR1 = 0x90; /* enable timer counter, enable fast flag clear*/TIOS &= ~IOS0; /* enable input-capture 0 /TSCR2 = 0x06; /* disable TCNT overflow interrupt, set prescaler to 64 */TSCR2 0x06; / disable TCNT overflow interrupt, set prescaler to 64 /TCTL4 = 0x01; /* capture the rising edge of the PT0 pin */TFLG1 = C0F; /* clear the C0F flag */while (!(TFLG1 & C0F)); /* wait for the arrival of the first rising edge */edge1 = TC0; /* save the first captured edge and clear C0F flag */edge C0; / sa e e s cap u ed edge a d c ea C0 ag /while (!(TFLG1 & C0F)); /* wait for the arrival of the second rising edge */period = TC0 - edge1;asm ("swi");

}}

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• Example 8.3 Write a program to measure the pulse width of a signal connected to the PT0 pin. The E clock frequency is 24 MHz. Solution:• Solution:– Set the prescale factor to TCNT to 32. Use clock cycle as the unit of

measurement.– The pulse width may be longer than 216 clock cycles. We need to keep

t k f th b f ti th t th TCNT ti fl L ttrack of the number of times that the TCNT timer overflows. Let• ovcnt = TCNT counter overflow count• diff = the difference of two consecutive edges• edge1 = the captured time of the first edge

f

Case 1edge2 ≥ edge1

• edge2 = the captured time of the second edge– The pulse width can be calculated by the following equations:

g g

pulse width = ovcnt × 216 + diff

Case 2edge2 < edge 1

pulse width = (ovcnt – 1) × 216 + diff

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#include "c:\miniide\hcs12.inc"org $1000

edge1 ds.b 2overflow ds.b 2pulse_width ds.b 2

org $1500movw #tov_isr,UserTimerOvf ; set up TCNT overflow interrupt vectorlds #$1500 ; set up stack pointerlds #$1500 ; set up stack pointermovw #0,overflowmovb #$90,TSCR1 ; enable TCNT and fast timer flag clearmovb #$05,TSCR2 ; disable TCNT interrupt, set prescaler to 32bclr TIOS,IOS0 ; select IC0

b #$01 TCTL4 t i i dmovb #$01,TCTL4 ; capture rising edgemovb #C0F,TFLG1 ; clear C0F flag

wait1 brclr TFLG1,C0F,wait1 ; wait for the first rising edgemovw TC0,edge1 ; save the first edge & clear the C0F flagmovb #TOF,TFLG2 ; clear TOF flag, ; gbset TSCR2,$80 ; enable TCNT overflow interruptcli ; "movb #$02,TCTL4 ; capture the falling edge on PT0 pin

wait2 brclr TFLG1,C0F,wait2 ; wait for the arrival of the falling edgeldd TC0ldd TC0subd edge1

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std pulse_widthbcc next ; is the second edge smaller?ldx overflow ; second edge is smaller, so decrementdex ; overflow count by 1stx overflow ; "

next swinext swi

tov_isr movb #TOF,TFLG2 ; clear TOF flagldx overflowinx

flstx overflowrtiend

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C Program for Pulse Width Measurement#include <hcs12.h>#include <vectors12.h>#define INTERRUPT __attribute__((interrupt)) unsigned diff, edge1, overflow;unsigned long pulse_width;void INTERRUPT tovisr(void);void main(void){

U Ti O f ( i d h )& iUserTimerOvf = (unsigned short)&tovisr;overflow = 0;TSCR1 = 0x90; /* enable timer and fast flag clear */TSCR2 = 0x05; /* set prescaler to 32, no timer overflow interrupt */TIOS & IOS0 /* l t i t t 0 */TIOS &= ~IOS0; /* select input-capture 0 */TCTL4 = 0x01; /* prepare to capture the rising edge */TFLG1 = C0F; /* clear C0F flag */while(!(TFLG1 & C0F)); /* wait for the arrival of the rising edge */TFLG2 TOF /* l TOF fl */TFLG2 = TOF; /* clear TOF flag */

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TSCR2 |= 0x80; /* enable TCNT overflow interrupt */(" li")asm("cli");

edge1 = TC0; /* save the first edge */TCTL4 = 0x02; /* prepare to capture the falling edge */while (!(TFLG1 & C0F)); /* wait for the arrival of the falling edge */diff TC0 d 1diff = TC0 - edge1;if (TC0 < edge1)

overflow -= 1;pulse_width = overflow * 65536u + diff;

(" i")asm ("swi");}void INTERRUPT tovisr(void){

TFLG2 TOF /* clear TOF flag */TFLG2 = TOF; /* clear TOF flag */overflow = overflow + 1;

}

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Output Compare Functionp p• The HCS12 has eight output compare functions.• Each output compare channel consists ofEach output compare channel consists of

– A 16-bit comparator– A 16-bit compare register TCx (also used as inout capture

i t )register)– An output action pin (PTx, can be pulled high, pulled low, or

toggled)– An interrupt request circuit– A forced-compare function (CFOCx)– Control logic

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Operation of the Output-Compare Function (1 of 4)

• One of the applications of the output-compare function is to trigger an action at a specific timefunction is to trigger an action at a specific time in the future.

• To use an output-compare function, the user– Makes a copy of the current contents of the TCNT

register– Adds to this copy a value equal to the desired delayAdds to this copy a value equal to the desired delay– Stores the sum into an output-compare register (TCx,

x = 0..7)

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Operation of the Output-Compare Function (2 of 4)• The actions that can be activated on an output compare pin include

7 6 5 4 3 2 1 0

– Pull up to high– Pull down to low– Toggle

• The action is determined by the Timer Control Register 1 & 2 (TCTL1 & TCTL2):7 6 5 4 3 2 1 0

OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4valueafter reset 0 0 0 0 0 0 0 0

(a) TCTL1 register

7 6 5 4 3 2 1 0

OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0

0 0 0 0 0 0 0 0(b) TCTL2 register

valueafter reset

read: anytimewrite: anytime

(b) TCTL2 register

OMn OLn : output level0 0 no action (timer disconnected from output pin)

Figure 8.18 Timer control register 1 and 2 (TCTL1 & TCTL2)

011

101

toggle OCn pinclear OCn pin to 0set OCn pin to high

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Operation of the Output-Compare Function (3 of 4)• A successful compare will set the corresponding flag bit in theA successful compare will set the corresponding flag bit in the

TFLG1 register.• An interrupt may be optionally requested if the associated interrupt

enable bit in the TIE register is set.Example 8 4 Generate an active high 1 KHz digital waveform with• Example 8.4 Generate an active high 1 KHz digital waveform with 30 percent duty cycle from the PT0 pin. Use the polling method to check the success of the output compare operation. The frequency of the E clock is 24 MHz.S 1 f 30• Solution: An active high 1 KHz waveform with 30 percent duty cycle is shown in Figure 8.19. The logic flow of this problem is illustrated in Figure 8.20.– Setting the prescaler to the TCNT to 8, then the period of the clock

300 μs

g p , psignal to the TCNT will be 1/3 ms. The numbers of clock cycles that the signal is high and low are 900 and 2100, respectively.

700 μs

Figure 8.19 1 KHz 30 percent duty cycle waveform

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Operation of the Output-Compare Function (4 of 4)Start

Select pull high as pin action

Clear C0F flag

Start OC0 output comparewith a delay of 700 μs

C0F = 1?

Select pull low as pin actionClear C0F flagStart OC0 output compare

no

yes

Start OC0 output comparewith a delay of 300 μs

C0F = 1?no yes

Figure 8.20 The program logic flow for digital waveform generation

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#include "c:\miniide\hcs12.inc"hi_time equ 900l ti 2100lo_time equ 2100

org $1500movb #$90,TSCR1 ; enable TCNT with fast timer flag clearmovb #$03,TSCR2 ; disable TCNT interrupt, set prescaler to 8b t TIOS OC0 bl OC0bset TIOS,OC0 ; enable OC0movb #$03,TCTL2 ; select pull high as pin actionldd TCNT ; start an OC0 operation with 700 us as delay

repeat addd #lo_time ; "td TC0 "std TC0 ; "

low brclr TFLG1,C0F,low ; wait until OC0 pin go highmovb #$02,TCTL2 ; select pull low as pin actionldd TC0 ; start an OC operation with 300 us as delayddd #hi ti "addd #hi_time ; "

std TC0 ; "high brclr TFLG1,C0F,high ; wait until OC0 pin go low

movb #$03,TCTL2 ; select pull high as pin actionldd TC0ldd TC0bra repeatend

Page 37: hcs12 timer.pdf

C Program for Generating 1 KHz Digital Waveform

#include "c:\egnu091\include\hcs12.h"#define hi_time 900#define lo_time 2100void main (void)

g

void main (void){

TSCR1 = 0x90; /* enable TCNT and fast timer flag clear */TIOS |= OC0; /* enable OC0 function */TSCR2 = 0x03; /* disable TCNT interrupt, set prescaler to 8 */TSCR2 0x03; / disable TCNT interrupt, set prescaler to 8 /TCTL2 = 0x03; /* set OC0 action to be pull high */TC0 = TCNT + lo_time; /* start an OC0 operation */while(1) {

while(!(TFLG1 & C0F)); /* wait for PT0 to go high */while(!(TFLG1 & C0F)); / wait for PT0 to go high /TCTL2 = 0x02; /* set OC0 pin action to pull low */TC0 += hi_time; /* start a new OC0 operation */while(!(TFLG1 & C0F)); /* wait for PT0 pin to go low */TCTL2 = 0x03; /* set OC0 pin action to pull high */TCTL2 0x03; / set OC0 pin action to pull high /TC0 += lo_time; /* start a new OC0 operation */

}}

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• Example 8.5 Write a function to generate a time delay which is a multiple of 1 ms.

• Assume that the E clock frequency is 24 MHz. The number of millisecondsAssume that the E clock frequency is 24 MHz. The number of milliseconds is passed in Y. Also write an instruction sequence to test this function.

• Solution: One method to create 1 ms delay is as follows:– Set the prescaler to TCNT to 64– Perform the number of output-compare operations (given in Y) with each

delayby1ms pshd

Perform the number of output compare operations (given in Y) with each operation creating a 1-ms time delay.

– The number to be added to the copy of TCNT is 375. (375 × 64 ÷ 24000000 = 1 ms)

y y pmovb #$90,TSCR1 ; enable TCNT & fast flags clearmovb #$06,TSCR2 ; configure prescaler to 64bset TIOS,OC0 ; enable OC0ldd TCNT

again0 addd #375 ; start an output-compare operationstd TC0 ; with 1 ms time delay

wait_lp0 brclr TFLG1,OC0,wait_lp0ldd TC0dbne y,again0puldrts

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void delayby1ms(int k){{

int ix;TSCR1 = 0x90; /* enable TCNT and fast timer flag clear */TSCR2 = 0x06; /* disable timer interrupt, set prescaler to 64 */TIOS | OC0 /* bl OC0 */TIOS |= OC0; /* enable OC0 */TC0 = TCNT + 375;for (ix = 0; ix < k; ix++) {

while(!(TFLG1 & C0F));TC0 375TC0 += 375;

}TIOS &= ~OC0; /* disable OC0 */

}

Page 40: hcs12 timer.pdf

• Example 8.6 Use an input-capture and an output-compare functions to measure the frequency of the signal connected to the PT0 pin.

• Solution: To measure the frequency, we will

#include "c:\MiniIDE\hcs12.inc"$

q y– Use one of the output-compare function to create a one-second time base.– Keep track of the number of rising (or falling) edges that arrived at the PT0 pin

within one second.

CR equ $0DLF equ $0A

org $1000oc_cnt rmb 1frequencyrmb 2

org $1500movb #$90,TSCR1 ; enable TCNT and fast timer flags clearmovb #$02,TSCR2 ; set prescale factor to 4

$movb #$02,TIOS ; enable OC1 and IC0movb #100,oc_cnt ; prepare to perform 100 OC1 operation, each

; creates 10 ms delay and total 1 secondmovw #0,frequency ; initialize frequency count to 0

b #$01 TCTL4 h i i d f PT0movb #$01,TCTL4 ; prepare to capture the rising edges of PT0movb #C0F,TFLG1 ; clear the C0F flagbset TIE,IC0 ; enable IC0 interruptcli ; "

Page 41: hcs12 timer.pdf

ldd TCNT ; start an OC1 operation with 10 ms delaycontinue addd #60000 ; "

std TC1 ; "std TC1 ; w_lp brclr TFLG1,C1F,w_lp ; wait for 10 ms

ldd TC1dec oc_cntbne continuebne continueldd frequencypshdldd #msgjsr [printf PCR]jsr [printf,PCR]leas 2,spswi

msg db CR,LF,"The frequency is %d",CR,LF,0TC0 isr ldd TC0 ; clear C0F flagTC0_isr ldd TC0 ; clear C0F flag

ldx frequency ; increment frequency count by 1inx ; "stx frequency ; rtirtiorg $3E6E ; set up interrupt vector numberfdb TC0_isr ; for TC0end

Page 42: hcs12 timer.pdf

C Program for Frequency Measurement Using IC0

#include <hcs12.h>#include <vectors12.h>#include <convert.c>#include <stdio.c>#define INTERRUPT __attribute__((interrupt))unsigned int frequency;void INTERRUPT TC0_isr(void);void main(void){

char arr[7];char *msg = "Signal frequency is ";int i, oc_cnt;unsigned frequency;UserTimerCh0 = (unsigned short)&TC0_isr;TSCR1 = 0x90; /* enable TCNT and fast flag clear */TSCR2 = 0x02; /* set prescale factor to 4 */TIOS = 0x02; /* select OC1 and IC0 */oc_cnt = 100; /* prepare to perform 100 OC1 operations */frequency = 0;

Page 43: hcs12 timer.pdf

TCTL4 = 0x01; /* prepare to capture PT0 rising edge */TFLG1 = C0F; /* clear C0F flag */TIE |= IC0; /* enable IC0 interrupt */asm("cli");TC1 = TCNT + 60000;while (oc_cnt) {

while(!(TFLG1 & C1F));TC1 = TC1 + 60000;oc_cnt = oc_cnt - 1;

}int2alpha(frequency, arr);puts(msg);puts(&arr[0]);asm("swi");

}void INTERRUPT TC0_isr(void){

TFLG1 = C0F; /* clear C0F flag */frequency ++;

}

Page 44: hcs12 timer.pdf

Making Sound Using the Output-Compare Functionp p

• A sound can be generated by creating a digital waveform with appropriate frequency and using it to drive a speaker or a buzzer.

• The circuit connection for a buzzer is shown in Figure 8.21.

HCS12DP256

8.21.• The simplest song is a two-tone siren.

PT5

3.3 μF

Buzzer

Figure 8.21 Circuit connection for a buzzer

Page 45: hcs12 timer.pdf

Algorithm for Generating a Siren• Step 1• Step 1

– Enable an output compare channel to drive the buzzer (or speaker).• Step 2

– Start an output compare operation with a delay count equal to half the period of the siren and enable the OC interruptthe siren and enable the OC interrupt.

• Step 3– Wait for the duration of the siren tone (say half a second). During the waiting

period, interrupts will be requested many times by the output compare function. The interrupt service routine simply restart the output compare operation.The interrupt service routine simply restart the output compare operation.

• Step 4– At the end of the siren tone duration, choose a different delay count for the

output compare operation so that the siren sound may have a different frequency.

• Step 5– Wait for the same duration as in Step 3. During this period, many interrupts will

be requested by the output compare operation. • Step 6

– Go to Step 2.

Page 46: hcs12 timer.pdf

• Example 8.7 Write a program to generate a two-tone siren that oscillates between 300 Hz and 1200 Hz.S l ti• Solution:– Set the prescaler to TCNT to 1:8.– The delay count for the low frequency tone is (24000000 ÷ 8) ÷

300 ÷ 2 = 5000

#include "c:\miniide\hcs12.inc"

300 ÷ 2 = 5000.– The delay count for the high frequency tone is (24000000 ÷ 8) ÷

1200 ÷ 2 = 1250.

hi_freq equ 1250 ; delay count for 1200 Hz (with 1:8 prescaler)lo_freq equ 5000 ; delay count for 300 Hz (with 1:8 prescaler)toggle equ $04 ; value to toggle the TC5 pin

org $1000delay ds.w 1 ; store the delay for output-compare operation

org $1500lds #$1500movw #oc5_isr,UserTimerCh5 ; initialize the interrupt vector entrymovb #$90,TSCR1 ; enable TCNT, fast timer flag clearmovb #$03,TSCR2 ; set main timer prescaler to 8

Page 47: hcs12 timer.pdf

bset TIOS,OC5 ; enable OC5movb #toggle,TCTL1 ; select toggle for OC5 pin actionmovw #hi freq delay ; use high frequency delay count firstmovw #hi_freq,delay ; use high frequency delay count firstldd TCNT ; start the low frequency soundaddd delay ; "std TC5 ; "bset TIE OC5 ; enable OC5 interruptbset TIE,OC5 ; enable OC5 interruptcli ; "

forever ldy #5 ; wait for half a secondjsr delayby100ms ; "movw #lo freq delay ; switch to low frequency delay countmovw #lo_freq,delay ; switch to low frequency delay countldy #5jsr delayby100msmovw #hi_freq,delay ; switch to high frequency delay countbra foreverbra forever

oc5_isr ldd TC5addd delaystd TC5rtirti

#include c:\miniide\delay.asm”end

Page 48: hcs12 timer.pdf

#include "c:\egnu091\include\hcs12.h"

C Program for Siren Generation (1 of 2)#include c:\egnu091\include\hcs12.h#include "c:\egnu091\include\delay.c"#include "c:\egnu091\include\v`ectors12.h"#define INTERRUPT __attribute__((interrupt))#define HiFreq 1250#define HiFreq 1250#define LoFreq 5000int delay; /* delay count for OC5 operation */void INTERRUPT oc5ISR(void);int main(void)int main(void){

UserTimerCh5 = (unsigned short)&oc5ISR;TSCR1 = 0x90; /* enable TCNT and fast timer flag clear */TSCR2 = 0x03; /* set prescaler to TCNT to 1:8 */TSCR2 0x03; / set prescaler to TCNT to 1:8 /TIOS |= BIT5; /* enable OC5 */TCTL1 = 0x04; /* select toggle for OC5 pin action */delay = HiFreq; /* use high frequency delay count first */TC5 = TCNT + delay; /* start an OC5 operation */y; pTIE |= BIT5; /* enable TC5 interrupt */asm("cli");

Page 49: hcs12 timer.pdf

C Program for Siren Generation (2 of 2)

while(1) {delayby100ms(5); /* wait for half a second */delay = LoFreq; /* switch to low frequency tone */delay = LoFreq; /* switch to low frequency tone */delayby100ms(5); /* wait for half a second */delay = HiFreq; /* switch to high frequency tone */

}return 0;return 0;

}void INTERRUPT oc5ISR(void){

TC5 += delay;TC5 += delay;}

Page 50: hcs12 timer.pdf

Playing Songs Using the OC Function

• Place the frequencies and durations of all notes in a tablein a table.

• For every note, use the output-compare function to generate the digital waveform with theto generate the digital waveform with the specified frequency and duration.

• The next example plays the US national anthem.The next example plays the US national anthem.

Page 51: hcs12 timer.pdf

#include "c:\miniide\hcs12.inc"G3 equ 7653 ; delay count to generate G3 note (with 1:8 prescaler)G3 equ 7653 ; delay count to generate G3 note (with 1:8 prescaler)B3 equ 6074 ; delay count to generate B3 note (with 1:8 prescaler)C4 equ 5733 ; delay count to generate C4 note (with 1:8 prescaler)C4S equ 5412 ; delay count to generate C4S (sharp) noteD4 equ 5108 ; delay count to generate D4 note (with 1:8 prescaler)D4 equ 5108 ; delay count to generate D4 note (with 1:8 prescaler)E4 equ 4551 ; delay count to generate E4 note (with 1:8 prescaler)F4 equ 4295 ; delay count to generate F4 note (with 1:8 prescaler)F4S equ 4054 ; delay count to generate F4S note (with 1:8 prescaler)G4 equ 3827 ; delay count to generate G4 note (with 1:8 prescaler)G4 equ 3827 ; delay count to generate G4 note (with 1:8 prescaler)A4 equ 3409 ; delay count to generate A4 note (with 1:8 prescaler)B4F equ 3218 ; delay count to generate B4F note (with 1:8 prescaler)B4 equ 3037 ; delay count to generate B4 note (with 1:8 prescaler)C5 equ 2867 ; delay count to generate C5 note (with 1:8 prescaler)C5 equ 2867 ; delay count to generate C5 note (with 1:8 prescaler)D5 equ 2554 ; delay count to generate D5 note (with 1:8 prescaler)E5 equ 2275 ; delay count to generate E5 note (with 1:8 prescaler)F5 equ 2148 ; delay count to generate F5 note (with 1:8 prescaler)notes equ 101notes equ 101toggle equ $04 ; value to toggle the TC5 pin

Page 52: hcs12 timer.pdf

org $1000delay ds.w 1 ; store the delay for output-compare operationrep cnt ds.b 1 ; repeat the song this many timesp_ ; p g yip ds.b 1 ; remaining notes to be played

org $1500lds #$1500

; establish the SRAM vector address for OC5;movw #oc5_isr,UserTimerCh5movb #$90,TSCR1 ; enable TCNT, fast timer flag clearmovb #$03,TSCR2 ; set main timer prescaler to 8bset TIOS,OC5 ; enable OC5movb #toggle,tctl1 ; select toggle for OC5 pin actionldx #score ; use as a pointer to score tableldy #duration ; points to duration tablemovb #1,rep_cnt ; play the song twicep_ p y gmovb #notes,ipmovw 2,x+,delay ; start with zeroth noteldd TCNT ; play the first noteaddd delay ; "ystd TC5 ; "bset TIE,C5I ; enable OC5 interruptcli ; "

Page 53: hcs12 timer.pdf

forever pshy ; save duration table pointer in stackldy 0,y ; get the duration of the current notejsr delayby10ms ; "puly ; get the duration pointer from stackiny ; move the duration pointeriny ; "ldd 2,x+ ; get the next note, move pointerstd delay ; "dec ipbne foreverdec rep_cntbeq done ; if not finish playing, re-establishldx #score ; pointers and loop countldy #duration ; "movb #notes,ip ; "movw 0,x,delay ; get the first note delay countldd TCNT ; play the first noteaddd #delay ; "std TC5bra forever

done swi

Page 54: hcs12 timer.pdf

oc5 isr ldd TC5oc5_isr ldd TC5addd delaystd TC5rti

; ************************************************************************************; ; The following subroutine creates a time delay which is equal to [Y] times; 10 ms. The timer prescaler is 1:8.; ************************************************************************************delayby10msde ayby 0 s

bset TIOS,OC0 ; enable OC0ldd TCNT

again1 addd #30000 ; start an output-compare operationstd TC0 ; with 10 ms time delay; y

wait_lp1 brclr TFLG1,C0F,wait_lp1ldd TC0dbne y,again1bclr TIOS,OC0 ; disable OC0, ;rts

Page 55: hcs12 timer.pdf

score dw D4,B3,G3,B3,D4,G4,B4,A4,G4,B3,C4Sdw D4 D4 D4 B4 A4 G4 F4S E4 F4S G4 G4 D4 B3 G3dw D4,D4,D4,B4,A4,G4,F4S,E4,F4S,G4,G4,D4,B3,G3dw D4,B3,G3,B3,D4,G4,B4,A4,G4,B3,C4S,D4,D4,D4dw B4,A4,G4,F4S,E4,F4S,G4,G4,D4,B3,G3,B4,B4dw B4,C5,D5,D5,C5,B4,A4,B4,C5,C5,C5,B4,A4,G4dw F4S E4 F4S G4 B3 C4S D4 D4 G4 G4 G4 F4Sdw F4S,E4,F4S,G4,B3,C4S,D4,D4,G4,G4,G4,F4Sdw E4,E4,E4,A4,C5,B4,A4,G4,G4,F4S,D4,D4dw G4,A4,B4,C5,D5,G4,A4,B4,C5,A4,G4

; **************************************************************************************; Each of the following entries multiplied by 10 ms gives the duration of a note; Each of the following entries multiplied by 10 ms gives the duration of a note.; **************************************************************************************duration dw 30,10,40,40,40,80,30,10,40,40,40

dw 80,20,20,60,20,40,80,20,20,40,40,40,40,40dw 30 10 40 40 40 80 30 10 40 40 40 80 20 20dw 30,10,40,40,40,80,30,10,40,40,40,80,20,20dw 60,20,40,80,20,20,40,40,40,40,40,20,20dw 40,40,40,80,20,20,40,40,40,80,40,60,20,40dw 80,20,20,40,40,40,80,40,40,40,20,20dw 40 40 40 40 20 20 20 20 40 40 20 20dw 40,40,40,40,20,20,20,20,40,40,20,20dw 60,20,20,20,80,20,20,60,20,40,80end

Page 56: hcs12 timer.pdf

#include “c:\egnu091\include\hcs12.h”#include “c:\egnu091\include\vectors12.h”#define G3 7653 ; delay count to be added to TC5#d fi B3 6074 t t th i t#define B3 6074 ; to generate the given note#define C4 5733#define C4S 5412#define D4 5108#d fi E4 4551#define E4 4551#define F4 4295#define F4S 4054#define G4 3827#d fi A4 3409#define A4 3409#define B4F 3218#define B4 3037#define C5 2867#d fi D5 2554#define D5 2554#define E5 2275#define F5 2148#define notes 101#d fi t l 0 04#define toggle 0x04#define INTERRUPT __attribute__((interrupt))int delay;

Page 57: hcs12 timer.pdf

void delayby10ms(int kk);void delayby10ms(int kk);void INTERRUPT oc5isr(void);unsigned int score [101] = {D4,B3,G3,B3,D4,G4,B4,A4,G4,B3,C4S,

D4,D4,D4,B4,A4,G4,F4S,E4,F4S,G4,G4,D4,B3,G3,D4 B3 G3 B3 D4 G4 B4 A4 G4 B3 C4S D4 D4 D4D4,B3,G3,B3,D4,G4,B4,A4,G4,B3,C4S,D4,D4,D4,B4,A4,G4,F4S,E4,F4S,G4,G4,D4,B3,G3,B4,B4,B4,C5,D5,D5,C5,B4,A4,B4,C5,C5,C5,B4,A4,G4,F4S,E4,F4S,G4,B3,C4S,D4,D4,G4,G4,G4,F4S,E4 E4 E4 A4 C5 B4 A4 G4 G4 F4S D4 D4E4,E4,E4,A4,C5,B4,A4,G4,G4,F4S,D4,D4,G4,A4,B4,C5,D5,G4,A4,B4,C5,A4,G4};

unsigned int dur [101] = {30,10,40,40,40,80,30,10,40,40,40,80,20,20,60,20,40,80,20,20,40,40,40,40,40,30 10 40 40 40 80 30 10 40 40 40 80 20 2030,10,40,40,40,80,30,10,40,40,40,80,20,20,60,20,40,80,20,20,40,40,40,40,40,20,20,40,40,40,80,20,20,40,40,40,80,40,60,20,40,80,20,20,40,40,40,80,40,40,40,20,20,40 40 40 40 20 20 20 20 40 40 20 2040,40,40,40,20,20,20,20,40,40,20,20,60,20,20,20,80,20,20,60,20,40,80};

Page 58: hcs12 timer.pdf

main (void){

int j;j;UserTimerCh5 = (unsigned short)&oc5isr;TSCR1 = 0x90; /* enable TCNT, fast timer flag clear */TSCR2 = 0x03; /* set TCNT prescaler to 8 */TFLG1 = 0xFF; /* clear all TxF flags */; gTIE |= C5I; /* enable TC5 interrupt */TIOS |= OC5; /* enable OC5 function */TCTL1 = toggle; /* select toggle as OC5 pin action */asm(" cli "); /* enable TC5 interrupt */( ); pj = 0;delay = score[0];TC5 = TCNT + delay; /* play the first note */while (j < notes) { /* play the song once */(j ) { p y g

delay = score[j]; /* play the jth note */delayby10ms(dur[j]);j++;

}}TIOS &= ~OC5; /* stop playing the song */asm ("swi"); /* return to D-Bug12 monitor */

}

Page 59: hcs12 timer.pdf

void delayby10ms(int kk){{

int i;TIOS |= OC0; /* enable OC0 */TC0 = TCNT + 30000; /* start one OC0 operation */for (i 0 i < kk i++) {for (i = 0; i < kk; i++) {

while(!(TFLG1 & C0F));TC0 += 30000;

}TIOS &= OC0;TIOS &= ~OC0;

}void INTERRUPT oc5isr(void){

TC5 += delay;TC5 += delay;}

Page 60: hcs12 timer.pdf

Drawback of the Song Algorithmg g• Contiguous identical notes become one note

C t h d d d d ff t• Cannot show crescendo and decrescendo effect• Cannot provide loudness control

Page 61: hcs12 timer.pdf

Using OC7 to Control Multiple OC Functions• OC7 can control up to eight channels of OC functions• OC7 can control up to eight channels of OC functions.• The register OC7M specifies which OC channels are controlled by OC7.• The register OC7D specifies the value that any PTx pin to assume when the

OC7 operation succeeds.OC OC OC ( ) f OC

7 6 5 4 3 2 1 0

• For OC0 to OC6, when the OC7Mn (n = 0,…,6) bit is set, a successful OC7 compare overrides a successful OC0…OC6 compare pin action during the same cycle.

reset 0 0 0 0 0 0 0 0

OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0

OC7Mn n = 0..7

0 = PTn pin is not affected by OC7 function1 = A successful OC7 action will override a successful OC6-OC01 A successful OC7 action will override a successful OC6 OC0 compare action during the same cycle and the OCn action taken will depend on the corresponding OC7D bit.

Figure 8.22 Output Compare 7 Mask Register (OC7M)

7 6 5 4 3 2 1 0

reset 0 0 0 0 0 0 0 0

O C7D7 O C7D6 O C7D5 O C7D4 O C7D3 O C7D2 O C7D1 O C7D0

Figure 8.23 Output Com pare 7 Data Register (OC7D)

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• Example 8 9 What value should be written into OC7M• Example 8.9 What value should be written into OC7M and OC7D if one wants pins PT2, PT3, and PT4 to assume the values of 1, 0, and 1, respectively when OC7 compare succeeds?OC7 compare succeeds?

• Solution: – 4, 3, and 2 of OC7M must be set to 1, and bits 4, 3, 2, of OC7D

h ld b t t 1 0 d 1 ti lshould be set to 1, 0, and 1, respectively. – The following instruction sequence will achieve the desired

effect:b #$1C OC7Mmovb #$1C,OC7M

movb #$14,OC7D

Page 63: hcs12 timer.pdf

Forced Output-Compare (1 of 2)• There are applications in which the user wants an outputThere are applications in which the user wants an output

compare in action to occur immediately instead of waiting for a match between the TCNT and the proper output compare register.p p g

• This situation arises in the spark plug timing control and some automotive engine control applications.

• To force an output compare operation, write ones to theTo force an output compare operation, write ones to the corresponding bit in the CFORC register.

• At the next timer count after the write to the CFORC register, the forced channels will trigger their

7 6 5 4 3 2 1 0

FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0

g , ggprogrammed pin actions to occur.

reset: 0 0 0 0 0 0 0 0

Figure 8.24 Contents of the CFORC register

Page 64: hcs12 timer.pdf

Forced Output-Compare (2 of 2)• Example 8.12 Suppose that the contents of the TCTL1 and TCTL2

registers are $D6 and $6E respecti el The contents of the TFLG1registers are $D6 and $6E, respectively. The contents of the TFLG1 are $00. What would occur on pins PT7 to PT0 on the next clock cycle if the value $7F is written into the CFORC register?

• Solution: – The TCTL1 and TCTL2 configure the output-compare actions as shown

in Table8.2.– The TFLG1 register indicates that none of the started output-compare

operations have succeeded yet.

Table 8.2 Pin actions on PT7-PT0 pins

Register Bit positions Value Action to be triggered

TCTL1 7 6 1 1 h PT7 i hi h

p y– The actions indicated in Table 8.2 will be forced to occur immediately.

TCTL1

TCTL2

7 65 43 21 0

7 65 4

1 10 10 11 0

0 11 0

set the PT7 pin to hightoggle the PT6 pintoggle the PT5 pinpull the PT4 pin to low

toggle the PT3 pinpull the PT2 pin to low5 4

3 21 0

1 01 11 0

pull the PT2 pin to lowset the PT1 pin to highpull the PT0 pin to low

Page 65: hcs12 timer.pdf

How to determine the DC voltage?g( )v t

2T

( )

( )

1DC Voltage = average value =

The light blue area = (2 ) the light green area =( 2 )2 2

T

v t dtT

T Tx x− × = − − ×

2 2

(2 ) ( 2) 0 V.2 2T Tx x x− × = + × ⇒ =

Page 66: hcs12 timer.pdf

How to determine the DC voltage?g( )v t 5

8T 3

8T

( )

( )

1DC Voltage = average value =

3 5The light blue area = (2 ) the light green area =( 2 )8 8

T

v t dtTT Tx x− × = − − ×

( ) ( ) ( )

3 5(2 ) ( 2)8 8

3 2 5 2 3 5 10 6 0.5V

T Tx x

x x x x

− × = + ×

− = + ⇒ − − = − ⇒ = −

Page 67: hcs12 timer.pdf

Pulse Width Modulation (PWM)M li i i h i f di i l f• Many applications require the generation of digital waveform.

• Output compare function can be used to generate digital waveform but incur too much overhead.

• Pulse width modulation requires only the initial setup of period and duty cycle for generating the digital waveform.

• The MC9S12DP256 has an 8-channel PWM module.• Each PWM channel has a period register, a duty cycle register, a control

register, and a dedicated counter to support waveform generation.g pp g• The clock input to PWM is programmable through a two-stage circuitry.• There are four possible clock sources for the PWM module: clock A, clock

SA, clock B, and clock SB.• Clock SA is derived by dividing the clock A by an even number ranging fromClock SA is derived by dividing the clock A by an even number ranging from

2 to 512.• Clock SB is derived by dividing the clock B by an even number ranging from

2 to 512.• Clock A and clock B are derived by dividing the E clock by a power of 2Clock A and clock B are derived by dividing the E clock by a power of 2.

The power can range from 0 to 7.

Page 68: hcs12 timer.pdf

Channel 7

Period and duty Counter

PWM ChannelsPWM Module

PWM7

Channel 6

Period and duty Counter

Channel 5

Period and duty Counter

Clock select

Control

PWMclockBus clock

PWM6

PWM5

Channel 4

Period and duty Counter

Channel 3

Enable PWM4

Period and duty Counter

Channel 2

Period and duty Counter

Polarity

Alignment

PWM3

PWM2

Channel 1

Period and duty Counter

Channel 0

Period and duty Counter

PWM1

PWM0y

Figure 8.38 HCS12 PWM block diagram

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PWM Clock Generation• The SA clock takes clock A as one of its inputs and divides it further with a

bl l (f 1 t 256) d th di id it b 2user-programmable value (from 1 to 256) and then divides it by 2..• Clock SA is derived by dividing clock A by the value of the PWMSCLA

register and then dividing by 2. • Clock SB is derived by dividing clock B by the value of the PWMSCLB

i t d th di idi b 2

7 6 5 4 3 2 1 0

0 PCKB2 PCKB1 PCKB0 0 PCKA2 PCKA1 PCKA0

register and then dividing by 2. • The clock source selection is controlled by the PWMCLK register.

reset: 0 00 0 0 0 0 0

Table 8.3 Clock B prescaler selects

PCKB2 PCKB1 PCKB0 value of clockB

0 0 0 E l k

Table 8.4 Clock A prescaler selects

PCKA2 PCKA1 PCKA0 value of clockA

0 0 0 E l k0000111

0011001

0101010

E clockE clock/2E clock/4E clock/8E clock/16E clock/32E clock/64

0000111

0011001

0101010

E clockE clock/2E clock/4E clock/8E clock/16E clock/32E clock/641

111

01

E clock/64E clock/128

11

11

01

E clock/64E clock/128

Figure 8.41 PWM prescale clock select register (PWMPRCLK)

Page 70: hcs12 timer.pdf

Clock Scale• When PWMSCLA = $00, the PWMSCLA value is considered a

full-scale of 256.

Clock AClock SA =2 PWMSCLA×

• When PWMSCLB = $00, the PWMSCLB value is considered a full-scale of 256.

Clock BClock BClock SB =2 PWMSCLB×

Page 71: hcs12 timer.pdf

7 6 5 4 3 2 1 0

PCLK7 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0

reset: 0 00 0 0 0 0 0

PCLK PWM h l l k l t ( 7 6 3 2)PCLKx: PWM channel x clock select (x = 7, 6, 3, 2) 0 = clock B as the clock source 1 = clock SB as the clock sourcePCLKy: PWM channel y clock select (y = 5, 4, 1, 0) 0 = clock A as the clock source 1 = clock SA as the clock source

Figure 8.42 PWM clock select register (PWMCLK)

PWM Channel Timers• The main part of each PWM channel x consists of an 8-bit counter (PWMCNTx), an

8-bit period register (PWMPERx), and an 8-bit duty cycle register (PWMDTYx).• The waveform output period is controlled by the match between the PWMPERx

register and PWMCNTx register.• The waveform output duty cycle is controlled by the match of the PWMDTYx register• The waveform output duty cycle is controlled by the match of the PWMDTYx register

and the PWMCNTx register.• The starting polarity of the output is selectable on a per channel basis by

programming the PWMPOL register.• A PWM channel must be enabled by setting the proper bit of the PWME register.y g g• The overall operation of the PWM module is shown in Figure 8.44.

Page 72: hcs12 timer.pdf

7 6 5 4 3 2 1 0

PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0

reset: 0 00 0 0 0 0 0

PPOLx: PWM channel x polarity 0 = PWM channel x output is low at the start of a period, then goes high when the

d h d

Figure 8.43 PWM polarity register (PWMPOL)

duty count is reached. 1 = PWM channel x output is high at the start of a period, then goes low when the duty count is reached.

7 6 5 4 3 2 1 0

PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0

reset: 0 00 0 0 0 0 0

Figure 8.45 PWM enable register (PWME)

PWMEx: PWM channel x enable 0 = PWM channel x disabled. 1 = PWM channel x enabled.

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GATE8-bit counter

clocksource

PWMCNTx

8-bit compare=

From port PTPdata register(clock edge sync)

up/down re

set

p

PWMDTYx

8 bit compare=

T Q

QR

MUX

MUX

to pindriver

PPOLx8-bit compare=

PWMPERx

T

R

CAExQ

Q

PWMExFigure 8.44 PWM channel block diagram

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PWM Waveform AlignmentPWM Waveform Alignment• PWM output waveform can be left-aligned or

t li dcenter-aligned. • The choice of alignment is controlled by the

PWMCAE registerPWMCAE register.

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Left-Aligned Outputg p• The PWMCNTx counter is configured as a count-up counter.

– PWMx frequency = Clock(A, B, SA, SB frequency) ÷ PWMPERx– Polarity = 0– PWMx duty cycle = [(PWMPERx – PWMDTYx) ÷ PWMPERx] × 100%– Polarity = 1– PWMx duty cycle = [PWMDTYx ÷ PWMPERx] × 100%

PPOLx = 0

PWMDTYxPeriod = PWMPERx

PPOLx = 1

Figure 8.47 PWM left-aligned output waveformg g p

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Center-Aligned Modeg• PWM counter operates as an up/down counter and is set to count

up whenever the counter is equal to $00.Wh th t t h th d t i t th t t fli fl• When the counter matches the duty register the output flip-flop changes state causing the PWM output to also change state.

• A match between the PWM counter and the period register changes the counter direction from an up-count to a down-countthe counter direction from an up-count to a down-count.

• When the PWM counter decrements and matches the duty register again, the output flip-flop changes state causing the PWM output to also change state.g

• When the PWM counter decrements to 0, the counter direction changes from a down-count back to an up-count and the period and duty registers are reloaded from their buffers.

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In Center-Aligned ModePWMx frequency = Clock (A, B, SA, or SB) frequency ÷ (2 × PWMPERx)Note: Period = 2 × PWMPERx

When polarity = 0When polarity = 0,PWMx duty cycle = [(PWMPERx – PWMDTYx) ÷ PWMPERx] × 100%

When polarity = 1,PWMx duty cycle = [PWMDTYx ÷ PWMPERx] × 100%PWMx duty cycle = [PWMDTYx ÷ PWMPERx] × 100%

PPOLx = 0

PPOLx = 1PWMDTYx PWMDTYx

PWMPERx PWMPERx

Period = PWMPERx * 2Figure 8.48 PWM center aligned output waveform

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PWM 16-bit Mode (1 of 2)

• Two adjacent PWM channels can be concatenated into a 16-bit PWM channel.Th t ti f PWM h l t ll d b th PWMCTL• The concatenation of PWM channels are controlled by the PWMCTL register.

• The 16-bit PWM system is illustrated in Figure 8.49. When channel k and k+1 are concatenated channel k is the high• When channel k and k+1 are concatenated, channel k is the high-order channel, whereas channel k+1 is the lower channel. (k is even number). A 16-bit channel outputs from the lower-order channel pin and is also enabled by the lower-order channel.y

• Both left-aligned and center-aligned mode apply to the 16-bit mode.

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PWM 16-bit Mode (2 of 2)

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PWMCNT6 PWMCNT7

Clock source 7high low

Period/Duty compare PWM7

PWMCNT4 PWMCNT5

Clock source 5high low

PWMCNT4 PWMCNT5

Period/Duty compare PWM5

Cl k 3

PWMCNT2 PWMCNT3

Period/Duty compare PWM3

Clock source 3high low

Period/Duty compare PWM3

PWMCNT0 PWMCNT1

Clock source 1high low

Period/Duty compare PWM1

Figure 8.49 PWM 16-bit mode

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PWM Counters• Each channel has a dedicated 8-bit up-down counter that runs at the rate of

the selected clock source.Th t i d t th d t d i d i t i h l k• The counter is compared to the duty and period registers in each clock cycle.

• When the counter matches the duty register, the output flip-flop changes state causing the PWM waveform to change statestate, causing the PWM waveform to change state.

• When the counter matches the period register, the PWM depends on the selected polarity in the polarity register (starts with low or high level).

• In concatenated mode, writes to the 16-bit counter either the low- or high-In concatenated mode, writes to the 16 bit counter either the low or highorder byte of the counter will reset the 16-bit counter.

• In concatenated mode, reads of the 16-bit counter must be made by a 16-bit access to main data coherency.

Page 82: hcs12 timer.pdf

• Example 8.21 Write an instruction sequence to generate a 100 KHz waveform with 50% duty cycle from the PWM0 pin (PP0). Assume that the % y y p ( )E clock frequency is 24 MHz.

• Solution: Use the following setting:– Select clock A as the clock source to PWM0 and set its prescaler to 2.– Select left-aligned mode.

#include “c:\miniide\hcs12.inc”

Select left aligned mode.– Load the value 120 into the PWMPER0 register (= 24000000 ÷100000 ÷2)– Load the value 60 into the PWMDTY0 register (= 120 × 50%)

…bset PWME,PWME0 ; enable PWM channel 0movb #1,PWMPOL ; channel 0 output high at the start of the periodmovb #0,PWMCLK ; select clock A as the clock source for PWM0movb #1,PWMPRCLK ; set clock A prescaler to 2 movb #0,PWMCAE ; select left-aligned modemovb #$0C,PWMCTL ; 8-bit mode, stop PWM in wait and freeze modesmovb #0,PWMCNT0 ; reset the PWM0 countermovb #120,PWMPER0 ; set period valuemovb #60,PWMDTY0 ; set duty value

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bset PWME,PWME0 ; enable PWM channel 0OR movb #1,PWME ; enable PWM channel 0

movb #1,PWMPOL ; channel 0 output high at the start of the periodmovb #0,PWMCLK ; select clock A as the clock source for PWM0movb #1,PWMPRCLK ; set clock A prescaler to 2 movb #0,PWMCAE ; select left-aligned modemovb #$0C,PWMCTL ; 8-bit mode, stop PWM in wait and freeze modesmovb #0,PWMCNT0 ; reset the PWM0 countermovb #120 PWMPER0 ; set period valuemovb #120,PWMPER0 ; set period valuemovb #60,PWMDTY0 ; set duty value

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Calculation• Example 8.21 Write an instruction sequence to generate a 100KHz waveform with

50% duty cycle from the PWM0 pin (PP0). Assume that the E clock frequency is 24 MHz.MHz.

E clock is @ 24 MHz, and the prescaler = 2 ⇒ Clock A is @ 12 MHz

1 1Waveform frequency = 100 KHz, then half of the period =

# of co nt for Clock A for half of the period 5 s

65

1 1 5 10 510 2

sμ−× = × =

66 65 10 5 10 12 10 60

−−×# of count for Clock A for half of the period, 5 μs =

[ PWMPER0 ] = 120 and [ PWMDTY0 ] = 60

6 6

6

5 10 12 10 60112 10

= × × × =

×

[ PWMPER0 ] 120 and [ PWMDTY0 ] 60

Page 85: hcs12 timer.pdf

• Example 8.22a Write an instruction sequence to generate a square wave with 20 μs period and 60% duty cycle from PWM0 and use center-aligned mode.

• Solution: – Select clock A as the clock source and set its prescaler to 2.p– Load the value 120 into PWMPER0 register (period = 2 × PWMPER0)– PWMPER0 = (20 × 24,000,000 ÷ 1000,000) ÷ 2 ÷ 2 = 120– PWMDTY0 = PWMPER0 × 60% = 72.

bset PWME,PWME0 ; enable PWM channel 0OR movb #1,PWME ; enable PWM channel 0

movb #1,PWMPOL ; set PWM0 output to start with high levelmovb #0,PWMCLK ; select clock A as the clock sourcemovb #0,PWMCLK ; select clock A as the clock source movb #1,PWMPRCLK ; set the PWM0 prescaler to clock A to 2movb #1,PWMCAE ; select PWM0 center-aligned modemovb #$0C,PWMCTL ; select 8-bit mode, stop PWM in wait and freeze modesmovb #0, PWMCNT0 ; reset PWM0 countermovb #0, PWMCNT0 ; reset PWM0 counter movb #120,PWMPER0 ; set period valuemovb #72,PWMDTY0 ; set duty value

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bset PWME,PWME0 ; enable PWM channel 0OR b #1 PWME bl PWM h l 0OR movb #1,PWME ; enable PWM channel 0

movb #1,PWMPOL ; set PWM0 output to start with high levelmovb #0,PWMCLK ; select clock A as the clock source movb #1,PWMPRCLK ; set the PWM0 prescaler to clock A to 2movb #1,PWMCAE ; select PWM0 center-aligned modemovb #$0C PWMCTL ; select 8-bit mode stop PWM in wait and freeze modesmovb #$0C,PWMCTL ; select 8 bit mode, stop PWM in wait and freeze modesmovb #0, PWMCNT0 ; reset PWM0 counter movb #120,PWMPER0 ; set period valuemovb #72,PWMDTY0 ; set duty value

Page 87: hcs12 timer.pdf

Calculation• Example 8.22a Write an instruction sequence to generate a square wave with 20 μs

period and 60% duty cycle from PWM0 and use center-aligned mode.

E clock is @ 24 MHz and the prescaler = 2 ⇒ Clock A is @ 12 MHzE clock is @ 24 MHz, and the prescaler = 2 ⇒ Clock A is @ 12 MHz

The square wave has a 20 μs period.620 10−×

# of count for Clock A for the period, 20 μs =

Note: For center-aligned mode: 2 × PWMPER0 = 240

6 6

6

20 10 20 10 12 10 240112 10

−×= × × × =

×

Note: For center aligned mode: 2 PWMPER0 240

[ PWMPER0 ] = 120 and [ PWMDTY0 ] = 120×60% = 72

Page 88: hcs12 timer.pdf

• Example 8.22b Write an instruction sequence to generate a square wave with 20 μs period and 60% duty cycle from PWM2 and use center-alignedmode.

• Solution: – Select clock B as the clock source and set its prescaler to 2.p– Load the value 120 into PWMPER2 register (period = 2 × PWMPER0)– PWMPER2 = (20 × 24,000,000 ÷ 1000,000) ÷ 4 ÷ 2 = 60– PWMDTY2 = PWMPER0 × 60% = 36.

bset PWME,PWME2 ; enable PWM channel 2OR movb #4,PWME ; enable PWM channel 2

movb #4,PWMPOL ; set PWM2 output to start with high levelmovb #0 PWMCLK ; select clock B as the clock sourcemovb #0,PWMCLK ; select clock B as the clock source movb #$20,PWMPRCLK ; set the PWM2 prescaler to clock B to 4movb #4,PWMCAE ; select PWM2 center-aligned modemovb #$0C,PWMCTL ; select 8-bit mode, stop PWM in wait and freeze modesmovb #0, PWMCNT2 ; reset PWM2 countermovb #0, PWMCNT2 ; reset PWM2 counter movb #60,PWMPER2 ; set period valuemovb #36,PWMDTY2 ; set duty value

Page 89: hcs12 timer.pdf

bset PWME,PWME2 ; enable PWM channel 2OR b #4 PWME bl PWM h l 2OR movb #4,PWME ; enable PWM channel 2

movb #4,PWMPOL ; set PWM2 output to start with high levelmovb #0,PWMCLK ; select clock B as the clock source movb #$20,PWMPRCLK ; set the PWM2 prescaler to clock B to 4movb #4,PWMCAE ; select PWM2 center-aligned modemovb #$0C PWMCTL ; select 8-bit mode stop PWM in wait and freeze modesmovb #$0C,PWMCTL ; select 8 bit mode, stop PWM in wait and freeze modesmovb #0, PWMCNT2 ; reset PWM2 counter movb #60,PWMPER2 ; set period valuemovb #36,PWMDTY2 ; set duty value

Page 90: hcs12 timer.pdf

Calculation• Example 8.22b Write an instruction sequence to generate a square wave with 20 μs

period and 60% duty cycle from PWM2 and use center-aligned mode.

E clock is @ 24 MHz and the prescaler = 4 ⇒ Clock B is @ 6 MHzE clock is @ 24 MHz, and the prescaler = 4 ⇒ Clock B is @ 6 MHz

The square wave has a 20 μs period.620 10−×

# of count for Clock B within 20 μs =

Note: For center-aligned mode: 2 × PWMPER2 = 120

6 6

6

20 10 20 10 6 10 12016 10

−×= × × × =

×

Note: For center aligned mode: 2 × PWMPER2 120

[ PWMPER2 ] = 60 and [ PWMDTY2 ] = 60×60% = 36

Page 91: hcs12 timer.pdf

• Example 8.23 Write an instruction sequence to generate a 50 Hz digital waveform with 80% duty cycle using the 16-bit mode from the g y y gPWM1 output pin.

• Solution: Using the following setting:– Select clock A as the clock source and set its prescaler to 16Select clock A as the clock source and set its prescaler to 16.– Select left aligned mode and select polarity 1.– Load the value 30000 into the PWMPER0:PWMPER1 register.– Load the value 24000 into the PWMDTY0:PWMDTY1 register.

bset PWME,PWME1 ; enable PWM0:PWM1movb #2,PWMPOL ; set PWM0:PWM1 output to start with high levelmovb #0,PWMCLK ; select clock A as the clock source

g

movb #4,PWMPRCLK ; set prescaler to 16movb #$1C,PWMCTL ; concat. PWM0:PWM1, stop PWM in wait and freeze modesmovb #0,PWMCAE ; select left align modemovb #0,PWMCNT1 ; reset PWM1 countermovw #30000,PWMPER0 ; set period valuemovw #24000,PWMDTY0 ; set duty value

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bset PWME,PWME1 ; enable PWM0:PWM1b #2 PWMPOL t PWM0 PWM1 t t t t t ith hi h l lmovb #2,PWMPOL ; set PWM0:PWM1 output to start with high level

movb #0,PWMCLK ; select clock A as the clock sourcemovb #4,PWMPRCLK ; set prescaler to 16movb #$1C,PWMCTL ; concat. PWM0:PWM1, stop PWM in wait and freeze modesmovb #0,PWMCAE ; select left align modemovb #0 PWMCNT1 ; reset PWM1 countermovb #0,PWMCNT1 ; reset PWM1 countermovw #30000,PWMPER0 ; set period valuemovw #24000,PWMDTY0 ; set duty value

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Calculation• Example 8.23 Write an instruction sequence to generate a 50 Hz digital

waveform with 80% duty cycle using the 16-bit mode from the PWM1 output pin.

E clock is @ 24 MHz, and the prescaler = 16 ⇒ Clock A is @ 1.5 MHz

Waveform frequency = 50 Hz, then the period =1 0.02 20

50ms= =

# of count for the period, 20 ms = 6 6

6

0.02 0.02 1.5 10 0.03 10 30,00011.5 10

= × × = × =

×

[ PWMPER0 ] = 30,000 and [ PWMDTY0 ] = 30,000×80% = 24,000

Page 94: hcs12 timer.pdf

• Example 24: Write an instruction sequence to generate a 20 Hzdigital waveform with 50% duty cycle using the 16-bit mode from thePWM1 output pin Use left aligned modePWM1 output pin. Use left aligned mode.

• Solution: Using the following setting:– Select SA as the clock source, set 50 as its down count value– Set clock A prescale factor to 16– Set clock A prescale factor to 16.– Select center aligned mode and select polarity 1.– Load the value 750 into the PWMPER0:PWMPER1 register.– Load the value 375 into the PWMDTY0:PWMDTY1 register.

bset PWME,PWME1 ; enable PWM0:PWM1movb #2,PWMPOL ; set PWM1 output high at the start of the periodmovb #2,PWMCLK ; select SA as the clock source of PWM0, PWM1

b #4 PWMPRCLK t l t l k A t 16movb #4,PWMPRCLK ; set prescaler to clock A to 16movb #0,PWMCAE ; select left align modemovb #$1C,PWMCTL ; set CON01, stop PWM in wait and freeze modesmovb #50,PWMSCLA ; set SCLA down count value to 50

b #0 PWMCNT1 t PWM1 d PWM0 tmovb #0,PWMCNT1 ; reset PWM1 and PWM0 countermovw #750,PWMPER0 ; set period valuemovw #375,PWMDTY0 ; set duty cycle value

Page 95: hcs12 timer.pdf

bset PWME,PWME1 ; enable PWM0:PWM1b #2 PWMPOL t PWM1 t t hi h t th t t f th i dmovb #2,PWMPOL ; set PWM1 output high at the start of the period

movb #2,PWMCLK ; select SA as the clock source of PWM0, PWM1movb #4,PWMPRCLK ; set prescaler to clock A to 16movb #0,PWMCAE ; select left align modemovb #$1C,PWMCTL ; set CON01, stop PWM in wait and freeze modesmovb #50 PWMSCLA ; set SCLA down count value to 50movb #50,PWMSCLA ; set SCLA down count value to 50movb #0,PWMCNT1 ; reset PWM1 and PWM0 countermovw #750,PWMPER0 ; set period valuemovw #375,PWMDTY0 ; set duty cycle value

Page 96: hcs12 timer.pdf

Calculation• Example 24: Write an instruction sequence to generate a 20 Hz digital• Example 24: Write an instruction sequence to generate a 20 Hz digital

waveform with 50% duty cycle using the 16-bit mode from the PWM1 outputpin. Use left aligned mode.

The generated waveform is @ 20 Hz, then period = 1/20 = 0.05 sec.E clock is @ 24 MHz, assume the prescale factor is @ 16.

624 MHz 1 21 5 MHz Period 10 secE l k−= ⇒ = = ×

( )6

6

1.5 MHz Period 10 sec16 1.5 MHz 3

0.05# of counts within 0.05 sec. = 1.5 0.05 10 75,0002 3 10

E clock

⇒ ×

= × × =×

[ PWMPER0 ] = 750 and [ PWMDTY0 ] = 750 × 50% = 375

( )75,000 2 50 750= × ×

Page 97: hcs12 timer.pdf

• Example 25: Write an instruction sequence to generate a 20 Hzdigital waveform with 50% duty cycle using the 16-bit mode from thePWM3 output pin Use center aligned modePWM3 output pin. Use center aligned mode.

• Solution: Using the following setting:– Select SB as the clock source and use 50 as its down count value.

Set clock B prescale factor to 16– Set clock B prescale factor to 16.– Select center aligned mode and select polarity 1.– Load the value 750 into the PWMPER0:PWMPER1 register.– Load the value 375 into the PWMDTY0:PWMDTY1 register.

bset PWME,PWME3 ; enable PWM2:PWM3move #8,PWMPOL ; set PWM3 output high at the start of the period movb #8,PWMCLK ; select SB as the clock source of PWM3, PWM2movb #$40 PWMPRCLK ; set prescaler to clock B to 16movb #$40,PWMPRCLK ; set prescaler to clock B to 16movb #8,PWMCAE ; select center aligned modemovb #$2C,PWMCTL ; set CON23, stop PWM in wait and freeze modesmovb #50,PWMSCLB ; set SCLB down count value to 50movb #0 PWMCNT3 ; reset PWM3 and PWM2 countermovb #0,PWMCNT3 ; reset PWM3 and PWM2 countermovw #750,PWMPER2 ; set period valuemovw #375,PWMDTY2 ; set duty cycle value

Page 98: hcs12 timer.pdf

bset PWME,PWME3 ; enable PWM2:PWM3move #8 PWMPOL ; set PWM3 output high at the start of the periodmove #8,PWMPOL ; set PWM3 output high at the start of the periodmovb #8,PWMCLK ; select SB as the clock source of PWM3, PWM2movb #$40,PWMPRCLK ; set prescaler to clock B to 16movb #8,PWMCAE ; select center aligned modemovb #$2C,PWMCTL ; set CON23, stop PWM in wait and freeze modesmovb #50,PWMSCLB ; set SCLB down count value to 50o b #50, SC ; set SC do cou t a ue to 50movb #0,PWMCNT3 ; reset PWM3 and PWM2 countermovw #750,PWMPER2 ; set period valuemovw #375,PWMDTY2 ; set duty cycle value

Page 99: hcs12 timer.pdf

Calculation• Example 25: Write an instruction sequence to generate a 20 Hz digital

waveform with 50% duty cycle using the 16-bit mode from the PWM3 outputpin. Use center aligned mode.

The generated waveform is @ 20 Hz, then period = 1/20 = 0.05 sec.E clock is @ 24 MHz, assume the prescale factor is @ 16.

624 MHz 1 21 5 MH P i d 10−

( )

6

66

1.5 MHz Period 10 sec16 1.5 MHz 3

0.05# of counts within 0.05 sec. = 1.5 0.05 10 75,0002 3 10

E clock

= ⇒ = = ×

= × × =×

[ PWMPER0 ] = 750 and [ PWMDTY0 ] = 750 × 50% = 375

( )2 3 1075,000 2 50 750

×

= × ×

[ PWMPER0 ] 750 and [ PWMDTY0 ] 750 × 50% 375

Page 100: hcs12 timer.pdf

• Example 8.24 Use PWM to dim the light bulb. Assume that we use the PWM0 output to control the brightness of a light bulb. Write a C p g gprogram to dim the light to 10% brightness gradually in five seconds.

• The E clock frequency is 24 MHz.q y

• Solution:– Set duty cycle to 100% at the beginning.y y g g– Dim the brightness by 10% in the first second and then 20% per second

in the following four seconds.– Load 100 into the PWMPER0 register at the beginning.

D t PWMPER0 b 1 100 d i th fi t d d– Decrement PWMPER0 by 1 every 100 ms during the first second and decrement PWMPER0 by 2 every 100 ms in the following four seconds.

Page 101: hcs12 timer.pdf

• #include “c:\egnu091\include\hcs12.h”• #include “c:\egnuo91\include\delay.c”

void main ()• void main ()• {• int dim_cnt;• PWMCLK = 0; /* select clock A as the clock source */PWMCLK 0; / select clock A as the clock source /• PWMPOL = 1; /* make waveform to start with high level */• PWMCTL = 0x0C; /* select 8-bit mode */• PWMPRCLK = 2; /* set clock A prescaler to 4 */• PWMCAE = 0; /* select left-aligned mode */• PWMPER0 = 100; /* set period of PWM0 to 0.1 ms */• PWMDTY0 = 100; /* set duty cycle to 100% */• PWME = 0x01; /* enable PWM0 channel */• PWME = 0x01; /* enable PWM0 channel */

/* reduce duty cycle 1 % per 100 ms in the first second */• for (dim_cnt = 0; dim_cnt < 10 ; dim_cnt ++) {• delayby100ms(1);y y ( );• PWMDTY0--;• }

Page 102: hcs12 timer.pdf

• /* reduce duty cycle 2% per 100 ms in the next 4 seconds */• for (dim cnt = 0; dim cnt < 40; dim cnt ++) {• for (dim_cnt = 0; dim_cnt < 40; dim_cnt ++) {• delayby100ms(1);• PWMDTY0 -= 2;• }• asm ("swi");• }