Hardware/Software co-development From Architecture Models ... · From Architecture Models to...

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Hardware/Software co-development From Architecture Models to Synthesis Patrick FARAIL / Philippe CUENOT 26 th of Novembre 2015

Transcript of Hardware/Software co-development From Architecture Models ... · From Architecture Models to...

Page 1: Hardware/Software co-development From Architecture Models ... · From Architecture Models to Synthesis Patrick FARAIL / Philippe CUENOT 26th of Novembre 2015. ... co-engineering agile

Hardware/Software co-developmentFrom Architecture Models to Synthesis

Patrick FARAIL / Philippe CUENOT26th of Novembre 2015

Page 2: Hardware/Software co-development From Architecture Models ... · From Architecture Models to Synthesis Patrick FARAIL / Philippe CUENOT 26th of Novembre 2015. ... co-engineering agile

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Welcome

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AGENDA: 8h30 – 17h30

30’ - IRT Saint-Exupéry – P. Cuenot/P. Farail : INGEQUIP project processes overview

45’ - ISAE – J. Hugues / Space Co-design - F. Montero : Architecture exploration using AADL and link to virtual platform using SpaceStudio

45’ - STM – L. Maillet-Contoz : SystemC - Architecture exploration and design of digital electronic

10h30 : Break 30 min.

45’ - Fraunhofer – S. Schulz/M. Dietrich : SystemC-AMS – Arch. exploration for mixed signal systems

45’ - LAAS – A. Nketsa: Co-validation state of the art for HW-SW Codesign

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AGENDA: 8h30 – 17h30

12h30 – 14h : Lunch and discussions

Room just in front of the desktop

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AGENDA: 8h30 – 17h30

45’ - ASTC Design Partners – E. Faure/ N. Broueilh : Use of virtual platform for verification and validation of an electronic system design

45’ - Fraunhofer – S. Schulz/T. Vörtler: UVM and verification of a system design

15h30 : Break 30 mi.

45’ - Lab-STICC – P. Coussy : Design Space Exploration and High Level Synthesis

45’ – Panel discussion driven by M. Burton : needed works and future collaborations

End at 17h30

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INGEQUIP – Project Processes overview

What is « Institut de Recherche Technologique Saint-Exupéry»?

What is « Ingequip »?

What are we trying to address?

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Public-Private

partnerships 50-50 long-term commitment of major

industrial and public partners

Technological

Research Programs derived from the roadmaps in the field

(competitivity clusters, CORAC, etc.)

Skills

development and

training supportTechnological platforms

accelerating technological

innovation and transfer to

industry

Integrated

collaborative

environment fitting into the public and

industrial research landscape

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Excellence CenterWorld class in 3 key technology domains

for Aeronautics, Space and Embedded Systems

More Electrical Platforms Embedded Systems

Materialsmultifunctional / high performance

Products / Marketsdevelopment

BasicResearch

Indu

stry

Pub

lic R

esea

rch

*TechnologyReadiness Level © IRT AESE “Saint Exupéry” - All rights reserved Confidential and proprietary document

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The INGEQUIP Project

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INGEQUIP Project

Define Methods & Integrate Tools to get equipment, software & hardware and product architecture

right first, safe earlier

30% gain on cycle and cost

Integrate Industrial & Research products in a

co-engineering agile development process

WP 1 : HW/SW co-design

WP 2 : Components based approaches

WP3 : V&V means

09/2014 -> 12/2016 - 260 p.m

The INGEQUIP Project

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The INGEQUIP Project

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Localisation (LOC)

Mission Management (MMS)

Platform management (PMS)

EMS – Energy Management

MOP – Motor Power Management

MOC – Motor Control

MOM – Mode Management

RCS – Rover Remote Control

DAL – Data Loading

Guidance (GUID)

Be open

Be neutral but representative of

industrial domains

Be representative of actual systems

Be simple but non trivial

Provide a nice “guinea pig” for the

project’s methods and tools

“Mission” control

Power control- motors- power converter

twIRTee DemonstratorThree Wheeled Integrated Rover Testbench for Equipment Engineering

Be robust to design changes

Support heterogeneous objectives, methods,

tools

Be manageable

Be the ground for collaborative work

Be a "honeypot" for external collaborations

Be a basis for future activities…

Support for Hardware/Software co-developmentFrom Architecture Models to Synthesis

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Equipment Architecture Iterative process

Prototype

Design

Safety

Resources

Functions

Physical Pre-architecture

Resources prediction

Physical Architecture

Resources Evaluation

Logical Architecture

Resources Verification and

Validation

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AADL model

Beh.annex

Errorannex

CapellaModel

SystemC-TLMModel

SystemC

IPXACTInterchange

SystemC-AMSModel

OSATESchedulability analysisStructural verificationsDependability evaluationBehavioral verification(Infras. code generation)

Export to other toolsVLAB Works, SpaceStudio, Qbox-Greenlib

VLAB Works, SpaceStudio, Qbox-GreenlibPerformance evaluationSimulation(Synthesis - Vivado)

T

T

VHDL

TToolSpecific feature traduction

Verification objective

Refinement

Design objective

T

T

Design and Verification activitiestool relation

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Loosely Timed (LT)Untimed (U)

Approximated Timed (AT) CABA

SystemC

terminology

TLM LT

TLM AT

CA BA

Computation(Transactional

style)

Communication

interface(TLM 2.0)

CABA

TLM_AT

TLM_LT

FU

Functional UntimedFT

Functional Timed

FTR

Functional Timed

Register Interface

No Archi decomposition

A

Archi decomposition

Register Interface

Timed

CABA

Cycle Accurate

Bit Accurate

B

C

D

E

(with TLM transactor)

A: Logical architecture (Simulink like)

B: Physical Pre-Architecture (architecture simulation)

C: Physical Architecture (hardware loosely time simulation)

D: Physical Architecture (hardware approximate time simulation)

E: Physical Architecture (hardware cycle accurate simulation)

A

Model

Accuracy

INGEQUIP

terminology

SystemC modeling style for simulation

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data memory, pessimisticcommunication,software driver

decomposition, bus sizing,software driveroptimisation

verification

operation, data flow, algorithmy, allocation

Loosely Timed (LT)Untimed (U)

Approximated Timed (AT) CABA

SystemC

terminology

TLM LT

TLM AT

CA BA

Computation(Transactional

style)

Communication

interface(TLM 2.0)

CABA

TLM_AT

TLM_LT

FU

Functional UntimedFT

Functional TimedFTR

Functional Timed

Register Interface

No Archi decomposition

A

Archi decomposition

Register Interface

Timed

CABA

Cycle Accurate

Bit Accurate

B

C

D

E

(with TLM transactor)

A

INGEQUIP

terminology

Proof of concept analysis

Ressource and Interface analysis

Microarchitecture analysis

Detailed analysis

Activities at different abstraction level

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Questions ???Thanks a lot for your attention