Hardware-Software Implementation With Model-Based Design€¦ · Hardware-Software Implementation...
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© 2007 The MathWorks, Inc. ® ® Hardware-Software Implementation With Model-Based Design Sudhir Sharma Product Manager, HDL Code Generation And Verification The MathWorks
Transcript of Hardware-Software Implementation With Model-Based Design€¦ · Hardware-Software Implementation...
©20
07 T
he M
athW
orks
, Inc
.
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Hardware-Software Implementation With Model-Based Design
Sudhir SharmaProduct Manager,HDL Code Generation And VerificationThe MathWorks
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Agenda
What is the System Design ChallengeSolutions for Embedded Software Development
Automatic Code GenerationVerification
Solutions for Hardware DevelopmentAutomatic Code GenerationVerification
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System design to implementation gap
C
Algorithm and System DesignAlgorithm and System DesignAlgorithm and System Design
MCU DSP FPGA ASIC
HDL
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Integrated Design Flow for Embedded Software and Hardware
Design, simulate, and validate system models and algorithms in MATLAB and Simulink
Automatically generate production software for embedded processors
Verify the software implementation against the system model
Verify the hardware implementation against the system model C
MATLAB® and Simulink®
Algorithm and System DesignMATLABMATLAB®® and Simulinkand Simulink®®
Algorithm and System DesignAlgorithm and System Design
Real-Time WorkshopEmbedded Coder,
Targets, Links
RealReal--Time WorkshopTime WorkshopEmbedded Coder,Embedded Coder,
Targets, LinksTargets, Links
Verif
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Simulink HDL CoderCo-simulation links
Simulink HDL CoderSimulink HDL CoderCoCo--simulation linkssimulation links
MCU DSP FPGA ASIC
HDL
Generate
Verif
y
Generate
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Case Study: Sobel Edge Detection Algorithm
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Floating-Point System Specification
Start by developing a golden specification
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Fixed-Point Modeling
Fixed-point model
Fixed-point model
Floating-point model
Floating-point model
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Fixed-Point Modeling
Fixed-point model
Fixed-point model
Floating-point model
Floating-point model
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Implementation on DSP, GPP, or an FPGA?
Fixed-point model
Fixed-point model
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Agenda
What is the System Design ChallengeSolutions for Embedded Software Development
Automatic Code GenerationVerification
Solutions for Hardware DevelopmentAutomatic Code GenerationVerification
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Fixed-point modelFixed-point model
Code generation options
and preferences
Code generation options
and preferences
Select target or flavor of generated code
Select target or flavor of generated code
Implementation on DSP and GPP
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Build and executeAuto-generate ‘C’ and ASM
Integrate RTOS and scheduler
Create full CCS project
Invoke compiler, linker, and download code
Run on target
Profile code performance
System profiling includes entire DSP
application code
System profiling includes entire DSP
application code Subsystem profilingSubsystem profiling
Code Execution on Target and Profiling
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Design Verification and Visualization:Simulink as verification test bench
Processor and hardware-in-the-loop testing, simulation,
visualization, and verification of embedded software with Simulink
Processor and hardware-in-the-loop testing, simulation,
visualization, and verification of embedded software with Simulink
Device or design under test (DUT)Device or design under test (DUT)
Simulink system design embedded on DSP
Simulink system design embedded on DSP
Simulink test benchSimulink test bench
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Code GenerationReal Time Workshop – ANSI/ISO C code for rapid prototyping, accelerationReal Time Workshop Embedded Coder – Embedded deployment
LinksLink for Altium TASKING Link for Analog Devices VisualDSP++Link for TI Code Composer Studio
TargetsTarget for TI C6000 DSPTarget for TI C2000 DSPTarget for Infineon C166 MicrocontrollersTarget for Freescale MPC5xx Microcontrollers
New!
Review: Code Generation for Embedded Software
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Agenda
What is the System Design ChallengeSolutions for Embedded Software Development
Automatic Code GenerationVerification
Solutions for Hardware DevelopmentAutomatic Code GenerationVerification
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Code Generation for Hardware
Simulinkdata path
Stateflowcontrol logic
Generated Verilog codeSimulink HDL Coder
Correct-by-constructionVHDL and Verilog code
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Fixed-point model
Fixed-point model
Floating-point model
Floating-point model
Hardware specific model
Hardware specific model
Fixed-Point Implementation on an FPGA
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Design Space Exploration
SpeedHow fast can this design run?
AreaCan I use a smaller chip?
PowerCan I target a mobile device?
Implementation AlternativesSum & Product: Linear, Cascade, and TreeGain: Multiplier, CSD, Factored-CSDMinimum/Maximum: Tree and CascadeLookup Table: Inline or hierarchical
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Select subsystem, target language, directory
Select subsystem, target language, directory
Select output optionsSelect output options
Check model for errorsCheck model for errors Generate HDL CodeGenerate HDL Code
Code Generation Options
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Select reset andclock options
Select reset andclock options
Set language-specific options: input/output datatypes, timescale
directives, …
Set language-specific options: input/output datatypes, timescale
directives, …
More Code Generation Options
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Self-checking HDL test bench compares Simulink results to HDL results
Self-checking HDL test bench compares Simulink results to HDL results
Generate HDL Test Bench
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AutomaticHDL
AutomaticHDL
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AutomaticHDL
AutomaticHDL
HandCustomized
HDL
HandCustomized
HDLCo-SimulateCo-Simulate
Reference code for HDL engineers
‘Correct-by-construction’Matches Fixed-Point System ModelFaster design implementationReduces verification burden
Benefits Include:
Automatic HDL Code Generation
Rapid FPGA implementation
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Verification with system specification
Link for ModelSimLink for ModelSim
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Promotes parallelism in design and verification tasksImproves focus on critical areas
Verify InterfacesVerify Interfaces
System metricsSystem metrics
Making full use of the system model
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Promotes parallelism in design and verification tasksImproves focus on critical areasAccelerates verification at all levels
Making full use of the system model
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Promotes parallelism in design and verification tasksImproves focus on critical areasAccelerates verification at all levelsSupports re-use and “what-if” scenarios
Making full use of the system model
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Implementation on an FPGA
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Review: Code Generation for Hardware
Code GenerationSimulink® HDL Coder – FPGA and ASIC deployment using VHDL and VerilogFilter Design HDL Coder – Filter implementation from MATLAB
LinksLink for Mentor ModelSimLink for Cadence® Incisive® New!
New!
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C
MATLAB® and Simulink®
Algorithm and System DesignMATLABMATLAB®® and Simulinkand Simulink®®
Algorithm and System DesignAlgorithm and System Design
Real-Time WorkshopEmbedded Coder,
Targets, Links
RealReal--Time WorkshopTime WorkshopEmbedded Coder,Embedded Coder,
Targets, LinksTargets, Links
Verif
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Simulink HDL CoderLink for ModelSim®
Link for Cadence® Incisive®
Simulink HDL CoderSimulink HDL CoderLink for ModelSimLink for ModelSim®®
Link for CadenceLink for Cadence®® IncisiveIncisive®®
MCU DSP FPGA ASIC
HDL
Generate
Verif
y
Generate
Design and verify software and hardwarefrom MATLAB and Simulink
Accelerate product development using Model-Based Design
Summary
