Hamming Presentation

8/3/2019 Hamming Presentation

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Hamming Code Circuit(Detection)

Mike RaCaroline Choi

Thuy Nguyen

Christopher Gobok

Advisor: Dave Parent

May 11, 2005


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Agenda

Introduction to Hamming Code

Project Specifications

Project Details (Schematic, Layout, etc.)

Cost Analysis

Conclusion/Lessons Learned


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What is Hamming Code?

Error detection scheme

Utilizes multiple parity bits to generate a

codeword that corresponds to the errorbit. (Consistent with other error correction

and detection schemes, where there is an

increase in overhead).

Correction is possible through hardware or

software


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Block Diagram

4 74

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ENCODER DECODER


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Specifications:

Encoder: input 4 data bits

output 7 data bits

Circuit Specs:

Clock Frequency : 200Mhz Supply Voltage : 5 V

Load Capacitance : 30fF

Decoder: input 7 data bits

output 4 data bits &

3 codeword bits


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Longest Path Calculations

Note: All widths are in micronsand capacitances in fF

XPHL= XPLH = (5ns)/(14LL) = 0.35ns

LogicLevel

Gate Cg toDrive

#CDn #CDp Nsn Nsp Wn Wp Cg ofGate

1 Sub_X_1 30.00 4 6 2 2 6.26 10.90 29.2

2 Inv_1 29.20 1 1 1 1 2.05 2.75 8.16

3 Sub_X_2 8.16 4 6 2 2 3.04 5.59 14.3

4 Inv_2 14.30 1 1 1 1 2.36 3.08 10.5

5 Sub_X_3 10.50 4 6 2 2 3.39 5.91 15.9

6 Inv_3 15.90 1 1 1 1 2.16 2.84 8.55

7 Sub_X_4 8.55 4 6 2 2 3.10 5.39 14.5

8 Inv_4 14.50 1 1 1 1 2.91 3.25 9.32

9 Sub_X_5 9.32 4 6 2 2 3.21 5.59 15.1

10 Inv_5 15.10 1 1 1 1 2.19 2.95 8.8


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Schematic


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Layout


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Verification


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Verification


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Simulation


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Simulation


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Cost Analysis

# of hours spent

Verifying logic 12

Verifying timing 25

Layout 40Post extracted timing 3

------------------

Total = 80 hours

@ a rate of $150/hr, this project would have cost $12,000!


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Summary

Complete Circuit:

Clock Frequency :315 Mhz

Area : 289.95 x 151.5 microns

Power : 3.78 mW

Load Capacitance : 30 fF


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Conclusion/Lessons Learned

Start Early

Expose yourself to the tool before starting

Layout Design in blocks (cell based) andthen instantiate them to minimize error

Test at every different phase

Ask other students with experience for help


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Acknowledgements /References

Thanks to Dr. Parent

Thanks to John (Dr. Parents T.A.)

Fellow Students

Ando, Hisashige & Fujibu Ltd. F4 Microprocessor Design Forum.

Robust Design Solutions for Nano-scale Circuits. 2005

Rowan University. Electronics II VLSI Design Lab 6 TheDesign and Layout of an Encoder/Decoder that Simulates theHamming

Error Correcting Code.http://users.rowan.edu/~head/spring05/vlsi/

ADK_HAMMING_Lab6_S05.doc

Unv. Of New Brunswick. EE4253 Digital Communications.

Error Correction and the Hamming Code. http://www.ee.unb.ca/

/tervo/ee4253/hamming.htm. 2002

Hamming Presentation

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