H. Huang Transparency No.9-1 The HCS12/MC9S12 Microcontroller Copyright © 2010 Delmar Cengage...

H. Huang Transparency No.9-1

The HCS12/MC9S12 Microcontroller

Copyright © 2010 Delmar Cengage Learning

Chapter 9: Serial Communication Interface – SCI

The HCS12 Microcontroller

Han-Way Huang

Minnesota State University, Mankato

September 2009




Why Serial Communication? Parallel data transfer requires many I/O pins. This requirement prevents the

microcontroller from interfacing with as many devices as desired in the application. Many I/O devices do not have high data rate to justify the use of parallel data transfer. Data synchronization for parallel transfer is difficult to achieve over a long distance.

This requirement is one of the reasons that data communications are always using serial transfer.

Cost consideration

What is SCI? An interface designed to transfer data only in asynchronous mode that utilizes the EIA-

232 standard.




Asynchronous Serial Data Communication

Often used in data communication between a DTE and a DCE with or without a modem. DTE stands for data terminal equipment and can be either a computer or a terminal. DCE stands for data communication equipment. A modem is a DCE. A basic data communication link is shown in Figure 9.0.

There are three kinds of data communication links:

1. Simplex link2. Half-duplex link3. Full-duplex link

DTE DTEDCE DCE

Computeror terminal

Computeror terminal

Modem Modem

Communication link

Figure 9.0 A data communication system




Types of communication link configuration

The RS232 Standard

Was the most widely used physical level interface for data communication Specifies 25 interchange circuits for DTE/DCE use Established in 1960 by Electronics Industry Association (EIA) Revised to RS232C in 1969 Revised to RS232D in 1987 Revised to RS232E in 1992 and renamed as EIA-232-E Revised and renamed to TIA-232F in 1997 there are four aspects: electrical, functional, procedural, and mechanical.

(a) Point-to-point Station Station

Master

Slave 1 Slave 2 Slave n......

(b) Multi-drop

Figure 9P.2 Point-to-point and multi-drop communication links




The EIA-232E Electrical Specifications

The interface is rated at a signal rate of < 20 kbps The signal can transfer correctly within 15 meters The maximum driver output voltage (with circuit open) is -25 V to +25 V The minimum driver output voltage (loaded output) is -25 V to -5 V and +5 V to +25

V The minimum driver output resistance when power is off is 300 W The receiver input voltage range is -25 V to +25 V The receiver output is high when input is open circuit A voltage more negative than -3 V at the receiver input is interpreted as a logic 1 A voltage more positive than +3 V at the receiver input is interpreted as a logic 0




Table 9.1 Functions of EIA-232E signals

Pin No. Circuit Description

1 - Shield2 BA Transmitted data3 BB Received data4 CA/CJ Request to send/ready for receiving1

5 CB Clear to send6 CC DCE ready7 AB Signal common8 CF Received line signal detector9 - (reserved for testing)10 - (reserved for testing)11 - unassigned3

12 SCF/CI Secondary received line signal detection/data rate selector (DCE source)2

13 SCB Secondary clear to send14 SBA Secondary transmitted data15 DB Transmitter signal element timing (DCE source)16 SBB Secondary received data17 DD Receiver signal element timing18 LL Local loopback19 SCA Secondary request to send20 CD DTE ready21 RL/CG Remote loopback/signal quality detector22 CE Ring indicator23 CH/CI Data signal rate selector (DTE/DCE source)2

24 DA Transmitter signal element timing (DTE source)25 TM Test mode

1. When hardware flow control is required, circuit CA may take on the functionality of circuit CJ. This is one change from the former TIA-232.2. For designs using interchange circuit SCF, interchange circuits CH and CI are assigned to pin 23. If SCF is not used, CI is assigned to pin 12.3. Pin 11 is unassigned. It will not be assigned in future versions of TIA-232. However, in international standard ISO 2110, this pin is assigned to select transmit frequency.




Mechanical Specification

Signal Name

Protective groundTransmitted dataReceived dataRequest to sendClear to sendData set readySignal ground

Carrier detectReservedReserved

Secondary carrier detect

Secondary clear to send

Secondary transmitted dataTransmit clock

Secondary received dataReceiver clock

Unassigned Secondary request to send

Data terminal ready

Signal quality detectRing indicatorData rate select

Transmit clockUnassigned

Signal Name Signal Direction

Both

to DCE

to DTEto DCEto DTEto DTEBoth

to DTE

to DTEto DTE

Both

to DCEto DTE

Signal Direction

to DTEto DTE

to DCE

to DCE

to DTEto DTE

to DCE

Figure 9.1a TIA-232F DB25 connector and pin assignment

123456789

10111213

141516171819202122232425

Unassigned

Ground5

4

3

2

1

9

8

7

6

DTE ready

Transmitted data

Received data

Received line signal detectDCE ready

Request to send

Clear to send

Ring indicator

Figure 9.1b TIA-232F DB9 connector and signal assignment




Data format for asynchronous data communication

Data is transmitted character by character bit-serially A character consists of

1. one start bit (0), 2. 7 to 8 data bits,

3. an optional parity bit, 4. one, or one and a half, or two stop bits (1)5. least significant bit is transmitted first6. most significant bit is transmitted last

Startbit

0 1 2 3 4 5 6 7 Stopbit 1

Stopbit 2

Figure 9.4 The format of a character




How to Detect the Arrival of Start Bit?

Use a clock signal with frequency at least 16 times that of the data rate to sample the RxD signal.

When the RxD pin is idle (high) for at least three sampling times and a falling edge follows, the SCI circuit checks the third, fifth, and seventh samples after the first sample. If the majority of them are low, then the start bit is considered detected.

How to Determine the Logic Value of a Data Bit?

Use a clock signal with frequency at least 16 times that of the data rate to sample the

incoming data. Take the majority function of the eighth, ninth, and tenth samples. If the majority of them

are 1s, then the logic value is determined to be 1.




Example 9.1 Sketch the output of the letter g when it is transmitted using the format of onestart bit, 8 data bit, and 1 stop bit.Solution:The ASCII code of letter g is $67 or %01100111. This code will be followed by a stopbit. The output from the DTE should be:

0 1 1 0 0 11 1 10

(a) output waveform on microcontroller interface

0 1 1 1 0 0 0 1 10

(b) output waveform on EIA-232-E interface

Figure 9.6 Data format for letter g




The HCS12 SCI Subsystem

A HCS12 device may have one or two serial communication interface. These two SCI

interfaces are referred to as SCI0 and SCI1. The block diagram is shown in Figure 9.7. The SCI uses the data format of one start, eight or nine data bits, and one stop bit. The

collection of the start bit, eight or nine data bits, and the stop bit is called a frame. The SCI function supports parity checking. This option requires the use of 9-bit data

format. One SCI channel uses two signal pins from Port S. The SCI0 shares the use of

PS0 (RxD0) and PS1 (TxD0), whereas SCI1 shares the use of PS2 (RxD1) and PS3 (TxD1). The SCI has the capability to send break to attract the attention of the other party of

communications. A break is defined as the transmission or reception of logic 0 for a frame or longer

time. The SCI supports hardware parity for transmission and reception. The SCI supports idling line and address mark wakeup, which is useful in multi-drop

environment to reduce the software overhead.




SCI data register

Receive shift register

Receive and wakeup control

BA

UD

gene

rato

r

16 Data format control

Transmit control

Transmit shift register

SCI data register

E clock

RxD

Interruptgeneration

Interruptgeneration

IdleIRQ

RDRF/ORIRQ

TDREIRQ

TCIRQ

ORIRQto CPU

TxD

Figure 9.7 HCS12 SCI block diagram




Baud Rate Generation The HCS12 SCI module uses a 13-bit counter to generate this clock signal. This circuit is

called baud rate generator. The baud rate generator divides down the E clock to derive the clock signal for reception

and transmission. The user writes an appropriate value into the SCIxBDH and SCIxBDL (x = 0 or 1)

register pair to set the baud rate.

7 6 5 4 3 2 1 0

reset: 0 0 0 0 0 0 0 0

SBR12 SBR11 SBR10 SBR90 0 0 SBR8

Figure 9.8 SCI baud rate control register

7 6 5 4 3 2 1 0

0 0 0 0 0 1 0 0

SBR4 SBR3 SBR2 SBR1SBR7 SBR6 SBR5 SBR0

(a) SCI baud rate control register high (SCI0BDH/SCI1BDH)

(b) SCI baud rate control register low (SCI0BDL/SCI1BDL)

reset:




The value to be written into the baud rate generator register is the rounding of the following expression:

SBR = fE 16 baud rate

Table 9.3 Baud rate generation

Desired SCIBaud Rate

Baud Rate Divisor forfE = 24 MHz

Baud Rate Divisor forfE = 16 MHz

300600

1200240048009600

14,40019,20038,400

5000250012506253131561047839

33331667833417208104695226




The SCI Control Registers

7 6 5 4 3 2 1 0

M WAKE ILT PELOOPS SCISWAI RSRC PT

Figure 9.9 SCI control register 1 (SCI0CR1/SCI1CR1)

LOOPS: loop select bit 0 = loop operation disabled. 1 = loop operation enabled.SCISWAI: SCI stop in wait mode 0 = SCI enabled in wait mode. 1 = SCI disabled in wait mode.RSRC: receiver source bit When LOOPS = 1, the RSRC bit determines the source for the receiver shift register 0 = receiver input connected to the transmitter internally (not TxD pin). 1 = receiver input connected externally to the transmitter (TxD pin).M: data format mode bit 0 = one start bit, eight data bits, one stop bit 1 = one start bit, nine data bits, one stop bitWAKE: wakeup condition bit 0 = idle line wakeup 1 = address mark wakeup (last data bit set)ILT: idle line type bit 0 = idle character bit count begins after start bit. 1 = idle character bit count begins after stop bit.PE: parity enable bit 0 = parity disabled. 1 = parity enabled.PT: parity type bit (for both transmit and receive) 0 = even parity selected. 1 = odd parity selected.

Reset value= 0x00




7 6 5 4 3 2 1 0

ILIE TE RE RWUTIE TCIE RIE SBK

Figure 9.10 SCI control register 2 (SCI0CR2/SCI1CR2)

TIE: transmit interrupt enable bit 0 = TDRE interrupt disabled. 1 = TDRE interrupt enabled.TCIE: transmit complete interrupt enable bit 0 = TC interrupt disabled. 1 = TC interrupt enabled.RIE: receiver full interrupt enable bit 0 = RDRF and OR interrupts disabled. 1 = RDRF and OR interrupt enabled.ILIE: idle line interrupt enable bit 0 = IDLE interrupt disabled. 1 = IDLE interrupt enabled.TE: transmitter enable bit 0 = transmitter disabled. 1 = transmitter enabled.RE: receiver enable 0 = receiver disabled. 1 = receiver enabled.RWU: receiver wakeup bit 0 = normal SCI receiver. 1 = enables the wakeup function and inhibits further receiver interrupts. Normally, hardware wakes up the receiver by automatically clearing this bit.SBK: send break bit 0 = no break characters. 1 = generate a break code, at least 10 or 11 contiguous 0s. As long as SBK remains set, the transmitter sends 0s.

Reset value= 0x00




SCI Status Registers7 6 5 4 3 2 1 0

IDLE OR NF FETDRE TC RDRF PF

Figure 9.12 SCI status register 1 (SCI0SR1/SCI1SR1)

TDRE: transmit data register empty flag 0 = no byte was transferred to the transmit shift register. 1 = transmit data register is empty.TC: transmit complete flag 0 = transmission in progress 1 = no transmission in progressRDRF: receiver data register full flag 0 = SCIxDR empty 1 = SCIxDR fullIDLE: idle line detected flag 0 = RxD line active 1 = RxD line becomes idleOR: overrun error flag 0 = no overrun 1 = overrun detectedNF: noise error flag Set during the same cycle as the RDRF bit but not set in the case of an overrun (OR). 0 = no noise 1 = noiseFE: framing error flag Set when a 0 is detected where a stop bit was expected. 0 = no framing error 1 = framing errorPF: Parity error flag 0 = parity correct 1 = incorrect parity detected

Reset value= 0xC0




7 6 5 4 3 2 1 0

0 0 BK13 TXDIR0 0 0 RAF

Figure 9.13 SCI status register 2 (SCI0SR2/SCI1SR2)

BK13: break transmit character length 0 = break character is 10- or 11-bit long. 1 = break character is 13- or 14-bit long.TXDIR: transmit pin data direction in single-wire mode 0 = TxD pin to be used as an input in single-wire mode. 1 = TxD pin to be used as an output in single-wire mode.RAF: receiver active flag RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character. 0 = no reception in progress 1 = reception in progress

Reset value= 0x00




Character Transmission

The block diagram of the SCI transmitter is shown in Figure 9.11. To transmit a character from the SCI module, the user writes the data bits into the

SCIxDRH and SCIxDRL registers. The data bits in SCIxDRH and SCIxDRL registers will be transferred to the transmit shift

register and shifted out serially from the TxD pin. Each time the SCI transfers data from the buffer SCIxDRH/L to the transmit shift register,

it also sets the TDRE flag in the SCIxSR1 register. The setting of the TDRE flag indicates that the MCU can write new data into the SCI data

register. When the transmit shift register is not transmitting data, the TxD signal goes to idle state. When both the transmit data registers and shift register are empty, the TC flag in

the SCIxSR1 register is set to 1. An interrupt may be requested to the MCU if the TDRE or TC flag is set to 1.




BAUD dividerBus

clock

SBR12-SBR0

16 SCI Data Register

H 8 7 6 5 3 2 1 0 L

ST

OP

ST

AR

T

M

T8

Paritygeneration

PEPT

Transmitter control

load

fro

m S

CID

R

Shi

ft e

nabl

e

prea

mbl

e (a

ll 1

s)

Bre

aks

(all

0s)

TESBK

TDRETIE

TCTCIE

TDRE interrupt request

TC interrupt request

LoopControl

LoopsRSRC

To RxD

TxD

Figure 9.11 SCI transmitter block diagram

Internal Bus

MS

B

4




Character Reception The block diagram of the SCI receiver is shown in Figure 9.14. The SCI receiver can handle either 8- or 9-bit characters. When receiving 9-bit data, the R8 bit of the SCIxDRH register holds the ninth bit. During an SCI reception, the receive shift register shifts in a frame from the RxD pin. After a complete frame is shifted into the receive shift register, the data portion of the

frame is transferred to the SCI data register. The receive data register full flag in the SCIxSR1 register is set to 1.

An interrupt may be requested to the MCU if it is enabled.




BAUD dividerBus

clock

SBR12-SBR0 SCI Data Register

H 8 7 6 5 3 2 1 0 L

STO

P

STA

RT

PEPT

IDLEILIE

RIE

IDLE interrupt request

RDRF/OR interrupt request

Figure 9.14 SCI receiver block diagram

Internal Bus

11-bit receive shift register

4

FENFPE

RWU

Wakeuplogic

Paritychecking

R8

RDRFOR

All

ones

MSB

WAKEILT

M

RERAF

Datarecovery

RxD

Loopcontrol

FromTxD

LOOPSRSRC




Single-Wire Operation In this operation, the RxD pin is disconnected from the SCI module. The SCI module uses the TxD pin for both receiving and transmitting as illustrated in

Figure 9.15. Single-wire operation is enabled by setting the LOOPS and the RSRC bits in the

SCIxCR1 register. Setting the LOOPS bit disables the path from the RxD pin to the receiver. Setting the

RSRC bit connects the receiver input to the output of the TxD pin driver. Both transmitter and receiver must be enabled. The TXDIR bit determines whether the TxD pin is going to be used as an input (TXDIR

= 0) or output (TXDIR = 1) in this mode of operation.

Transmitter

Receiver

TxD

RxD

Figure 9.15 Single-wire operation




Flow Control of UART in Asynchronous Mode

The SCI module will transmit data as fast as the baud rate allows. In some circumstances, the software may not be able to read data as fast as the data is

received. There is a need for the MCU to tell the transmitting device to suspend transmission of

data temporarily. Similarly, the HCS12 may need to be told to suspend transmission temporarily. This is

done by flow control. There are two common methods of flow control: XON/XOFF and hardware. XON/XOFF is implemented completely in software but requires a full-duplex

communication. When incoming data needs to be suspended, am XOFF byte is transmitted back to the

other device that is transmitting. To start the other device transmitting again, an XON character is transmitted. The XON and XOFF characters have the ASCII code of 0x11 and 0x13, respectively. Hardware flow control requires the use of extra signals. Generally, an input pin of the

transmitter is controlled by the receiver. Before transmitting any character, the transmitter needs to test the flow control input pin.




Example 9.2 Write an instruction sequence to configure the SCI0 to operate with the following parameters: 9600 baud (E clock is 24 MHz) one start bit, 8 data bits, one stop bit no interrupt address mark wakeup disable wakeup initially long idle line mode enable transmit and receive no loop back disable parity checkingSolution: The following instruction sequence will configure the SCI0 properly:

movb #$00,SC0BDH ; set up baud ratemovb #156,SC0BDL ; “movb #$4C,SC0CR1 ; select 8 data bits, address mark wakeupmovb #$0C,SC0CR2 ; enable transmitter and receiver




Example 9.4 Write a subroutine to output the character in accumulator A to the SCI0 channel using the polling method.Solution: - The subroutine will wait until the bit 7 of SCI0SR1 register is set before sending out the

character in accumulator A.

#include "c:\miniide\hcs12.inc"putcSCI0 brclr SCI0SR1,TDRE,* ; wait for TDRE to be set

staa SCI0DRL ; output the characterrts

void putcSCI0 (char cx){

while (!(SCI0SR1 & TDRE));SCI0DRL = cx;

}




Example 9.5 Write a subroutine to read a character from SCI0 using the polling method. Return the character in accumulator A.Solution:

#include "c:\miniide\hcs12.inc"getcSCI0 brclr SCI0SR1,RDRF,* ; wait until RDRF bit is set

ldaa SCI0DRL ; read the characterrts

char getcSCI0 (void){

while(!(SCI0SR1 & RDRF));return (SCI0DRL);

}




Example 9.6 Write a subroutine to output a string pointed to by index register X to the SCI0 using the polling method.

Solution: This subroutine will call putcSCI0( ) repeatedly until all characters have been sent.

putsSCI0 ldaa 1,x+ ; get a character and move the pointerbeq donep ; is this the end of the stringjsr putcSCI0bra putsSCI0

donep rts

void putsSCI0 (char *cx){

while (!(*cx)) {putcSCI0(*cx);cx++;

}}




Example 9.7 Write a subroutine to input a string from SCI0. The string is terminated by the carriage return character and must be stored in a buffer pointed to by index register X.

Solution: This subroutine will call getcSCI0( ) repeatedly until the carriage return character is

getsSCI0 jsr getchcmpa #CR ; is it a carriage returnbeq qistaa 0,x ; save the character and increment the pointerjsr putch ; echo it back to SCI0cmpa #BS ; is it a backspace character? (ASCII code is 0x08)bne nc ; no, continuedex ; decrement the input buffer pointerldaa #WS ; wipe out the previous character (ASCII code of WS is 0x20)jsr putchldaa #BSjsr putchbra gets

nc inxbra gets

qi clr 0,x ; terminate the string by a NULL characterrts




int gets(char *ptr){ char cx; while ((cx = getch()) != 0x0D) { *ptr = cx; putch(cx); if (cx == 0x08) { // is it a backspace character? ptr--; // move back the string pointer putch(0x20);// output a space putch(0x08);// output another backspace character }

ptr++; // move buffer pointer } *ptr = 0; // terminate the string with a NULL character return 0;}

H. Huang Transparency No.9-1 The HCS12/MC9S12 Microcontroller Copyright © 2010 Delmar Cengage...

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Transcript of H. Huang Transparency No.9-1 The HCS12/MC9S12 Microcontroller Copyright © 2010 Delmar Cengage...