Guide Manual1

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Technical Guide Manual

Alvaro M. Combo

2012/05/18 : 14:51:24


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List of Figures

1.1 SFP Connectors and Cable Assemblies. . . . . . . . . . . . . 131.2 Eclipse General Text Preferences window. . . . . . . . . . . . 23

2.1 Channel architecture of reads. . . . . . . . . . . . . . . . . . . 332.2 Channel architecture of writes. . . . . . . . . . . . . . . . . . 342.3 AXI Interface and Interconnect. . . . . . . . . . . . . . . . . . 342.4 Molex QSFP+ Solutions. . . . . . . . . . . . . . . . . . . . . 43

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4 LIST OF FIGURES


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Part I

PART I: Theoretical

Foundations

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Part II

PART II: Practical Guides

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Chapter 1

Hardware Practical Guides

1.0.1 Introduction

This section is devoted to keep updated information regarding Hardwaredesign issues that may arise on every design cycle. It is intended to pro-vide guidelines for selection or discarding solutions in an decision scheme assimple and clear as possible.

The Hardware Practical Guides focus on already implemented, tested orotherwise evaluated solutions presenting the initial requirements and devel-opment constraints and conclusions.

1.0.2 Hardware Guides Context

These guidelines have a wide range of application and span trough all hard-ware development and application. From Powering systems, Signal Integrity,High pin-count chips, Soldering, Interconnection, Electrical and Optical In-terfaces and a myriad of other areas that are involved in the hardware De-sign.

1.0.3 Hardware Design Guidelines

1.0.3.1 Boards and Systems Cabled Interconnection

The interconnection between two boards and/or systems or sub-systems maybe achieved trough some kind of cable connection or trough air in wirelesscommunications. This section is devoted to the former by clarifying thetypes and existing solutions for connecting systems that can be physicallydetached. This means that interconnection inside a PCB, for instance, willnot be addressed, but plugin-like connection will.

1.0.3.1.1 Types of Interconnection There are three basic intercon-nection schemes that depend on physical distance of sub-components, re-quired electric isolation, required robustness, required speed and of course

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10 CHAPTER 1. HARDWARE PRACTICAL GUIDES

cost. These interconnection can be defined as Connector-Connector, Copper

Cable and Fiber Optic cable.The Connector-Connector is only available when boards are closer. Ex-

amples of these interconnection are Piggy-back, Cards on crates (with abackplane) or edge-fingers to PCB connections. The scope of this kind ofinterconnection is really wide and goes from very slow signals to very-highspeed like is typical in backplanes.

Connector-Connector type is almost always trough copper. The selectionof connector is usually based on signal speed (and corresponding allowedcrosstalk), signal attenuation or Standardization . This is usually prettystrait forward since these characteristics are generally available from themanufacturers.

When sub-components are far the some king of cabled interconnectionis required. In this situation there are many issues to consider:

What type of data is to be transmitted (analogue or digital).

Data rate required (for digital transmission) or signal bandwidth (foranalogue signals)

Thus signal transmission requires a transceiver or a driver/receiver.

For analogue signals, evaluate special characteristics like SNR, type oftransmission (single ended, differential, current, voltage, range. . . ).

Thus the system requires galvanic isolation.

Specific interfaces requirements like a specific connector type or specificrequest for optical/electric interconnection.

Required interchangeable flexibility like the possibility of using copperor fibre.

Adherence to existing standards and their compatibility.

1.0.3.1.2 Signal Driving/Receiving On this (extremely) short pre-

sentation we will not go into details on Signal transmission, which is a VASTfield. We just will point out some aspects that must be considered (andevaluated) when interconnecting sub-components of a system with respectsignal integrity to assure that what is received contains the same relevantinformation that was transmitted.

NOTE: Note that we have used the expression the same relevantinformation. This is of key importance in understanding the actual system.When developing some application it is required a good knowledge of thesystem and specifically What is the Relevant Information?, because NOSYSTEM will pass ALL information. An analogue signal will be attenuated,


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11

may suffer reflections, dispersion, interference and other possible effects that

change the information content. The role of the developer is to maintainthat change within acceptable limits AND to understand WHAT THOSELIMITS are.

In this context, Signal driver/receiver applies only to electrical signalsthat maintain their main characteristics. In this view the following aspectsmust be evaluated.

General Application Scope: There are two main areas of interest for thiskind of transmission

Digital Signal: In the case of Digital signals the scope is restricted to

low/medium speeds and depends on distance. The transmissionis highly dependant of signal standard used. For TTL signals onlylow speeds and distances are attainable. Higher speeds requireLVDS or other differential transmission. In this case the mostimportant aspects are the impedance matching between sourcetransmission and destination and the EMI.

Analogue Signals: For analogue signals there are multiple parame-ters that need fully evaluation.

Type of signal transmission: Current, Voltage or Power. ThePower transmission is rarely used. Current transmission isusually used for small signals and Voltage transmission in all

the remaining situations.

Signal Bandwith: It is important to define the signal band-with of interest, since transmission must be optimized forthat frequency band.

1.0.3.1.3 PCB Connectors and Cable/Fibre Connectors The sig-nal transmission requires the physical attachment of PCB modules to cablesand fibres. While there is an enormous variety in connectors and cablesthere was a tendency in the last years to have some kind of standardiza-

tion for interconnecting ultra-high-speed signals. This process is focused onphysical dimensions and basic infrastructure managing.

The most successfully standardization movement occurred with the SFFCommittee (Small Form Factor Committee) formed in 1990, which is anad-hoc electronic group that defines interoperability specifications (See acomplete list here).

This group has defined several important form factors for importantapplications like HDDs and other drives and telecommunications intercon-nection. The SFF Committee has devised a called Multi-Source Agreement(MSA) were there is not a formal standardization process but an ad-hoc
http://www.sffcommittee.org/iehttp://www.sffcommittee.org/ieftp://ftp.seagate.com/sff/8000_PRJ.HTMftp://ftp.seagate.com/sff/8000_PRJ.HTMhttp://www.sffcommittee.org/iehttp://www.sffcommittee.org/ie


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process where the members propose solutions to be adopted by others as

a standard. Trough this process there were adopted several definitions andother groups were formed (see CFP Multi-Source Agreement).

In addition to form factors SFF Committee also specifies some low levelinfrastructure management. It follows a list of most relevant specifica-tions that can be downloaded here. It also presented the future opticaltransceivers for 40 Gbit/s and 100 Gbit/s applications (including Ethernet).

SFP: SFPs support speeds up to 4.25 Gbps and are generally used for FastEthernet or Gigabit Ethernet applications.

SFP+: The expanded SFP standard, SFP+, supports speeds of 10 Gbpsor higher over fiber.

QSFP:

QSFP+:

CFP2: 40 Gbit/s

CFP4: 100 Gbit/s

XFP: This is a separate standard that is similar to Small Form-factorPluggable (SFP) and Enhanced Small Form-factor Pluggable (SFP+)that also supports 10-G/

sGbps speeds.The primary difference between

SFP+ and the slightly older 10 Gbits Small Form-factor Pluggable(XFP) standard is that SFP+ moves the chip for clock and data re-covery into a line card on the host device. This makes an SFP+ smallerthan an XFP, enabling greater port density.

1.0.3.1.4 Signal Transceivers Specially for digital transmission, butno limited to it1 and when high speed or any special feature is requiredtransceivers are used. We use here transceivers in a broader sense, meaningany device that either converts electrical signals into optical (and vice versa)or that encode/decode digital signals in order to transmit.

1.0.3.2 Ultra-High Speed System Interconnection

In this section we will look into the interconnection between different systemsusing ultra-high speed (above GHz) that are used in things like PCIe, SATAand others.

1.0.3.2.1 PCB Connectors

1Optical transceivers are commonly used in Analogue Transmissions were galvanicisolation is required. They are limited to low speed signals since their operation is quitedifferent from their counterpart used in digital transmission.
http://www.cfp-msa.org/ftp://ftp.seagate.com/sff/ftp://ftp.seagate.com/sff/http://www.cfp-msa.org/


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1.1. FIRMWARE PRACTICAL GUIDES 13

1.0.3.2.2 Copper Cable vs. Optical Fiber The wired interconnec-

tion between systems can be done trough copper cable or over fibre. Thereare fundamental differences between the two types of interconnection thatmust be evaluated.

Mechanical Interface: There are many mechanical standards that canbe used in multiple applications. Some of them are restricted in thefrequency range they operate, others in the number of lanes or wiresthey support. It follows a list of most common mechanical interfaces.

SFPSFP+: These two cases are similar and are separated bythe fact that SFP+ supports rates over 10 Gbit. In Figure 1.1

is presented two different SFP connectors which have a com-mon physical description but have distinct interfaces. It

(a) Optical Interface SFP (b) Copper Interface SFP (c) Optical Cable with pas-sive interface

Figure 1.1: SFP Connectors and Cable Assemblies.

worth mentioning that SFP and SFP+ follow a concept wherethe transceiver is independent of the connector itself and mustaccommodated by it. Thus any type of transceiver can, in prin-ciple, be inserted in an SFP connector

Electric Isolation:

Signal Attenuation:

1.0.3.2.2.1 ggg ggh

1.1 Firmware Practical Guides

1.1.1 Introduction

This section is devoted several aspects of Firmware implementation. This in-cludes, but not limited to, core design and implementation, specific settingsand bugs.


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1.1.2 Firmware Guides Context

PCIexpress endpoint in Virtex6 Field Programmable Gate Array (FPGA)platform.

1.1.3 PCI-Express Endpoint: Virtex-6

Xilinx VIrtex-6 has a hard coded Peripheral Component Interconnect Ex-press (PCIe) endpoint. This endpoint can be instantiated trough a coregenerated by CoreGen. This core is highly customizable and allows the useof several type of fabric user interface.

For the most recent designs Xilinx advices the users to use an AdvancedeXtensible Interface (AXI)2 interface

1.2 Software Practical Guides

1.2.1 Introduction

This section is devoted.

1.2.2 Software Guides Context

1.2.3 Software Design Guidelines

1.2.3.1 Boards and Systems Cabled Interconnection

2AXI is a sub-set of the Advanced Microcontroller Bus Architecture (AMBA) specifi-cations from ARM.


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Part III

PART III: Languages

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1.3. LATEX GUIDE 17

1.3 Latex Guide

This section is devoted to the LATEX.

1.3.1 Description

LATEXis some kind o

1.3.2 LATEXResources

Here is a list of resources that can be helpful for leaning and create docu-ments using LATEX.

Packages

easylist: Package designed for typesetting lists of numbered items.

Manual - CTAN: easylistPackage.

graphicx or graphics: Manipulation of external graphics Package.There is a sligth difference between these two packages, beinggraphics a legacy package. graphicx is an extension that pro-vides optional arguments according to the new LATEX concept(See Packages: graphics vs graphicx).

Manual - CTAN: graphics and graphicx Packages.

Tutorial - Max-Planck: graphics and graphicx Packages.WIKIBOOKS

This is an excellent site that contains an extensive and clear online-book about LATEX that can also be downloaded in pdf format. Thesite contains also other books.

It is accessible in WIKIBOOKS:LATEX.

New item

1.3.2.1 LATEX related Issues

wrapfig and list environment incompatibilitiesThe package wrapfig package CANNOT be used inside a list envi-ronment. This issue is package related and is described in LATEXUsersGroup: Text wrapping in enumerate environment

Second Issue This is the second issue.
ftp://ctan.tug.org/tex-archive/macros/latex/contrib/easylist/easylist-doc.pdfftp://ctan.tug.org/tex-archive/macros/latex/contrib/easylist/easylist-doc.pdfhttp://tex.stackexchange.com/questions/23075/packages-graphics-vs-graphicxftp://www.ctan.org/ctan/macros/latex/required/graphics/grfguide.pdfftp://www.ctan.org/ctan/macros/latex/required/graphics/grfguide.pdfhttp://www.mps.mpg.de/homes/daly/latex/grf.pdfhttp://www.mps.mpg.de/homes/daly/latex/grf.pdfhttp://en.wikibooks.org/wiki/LaTeXhttp://en.wikibooks.org/wiki/LaTeXhttp://en.wikibooks.org/wiki/LaTeXhttp://en.wikibooks.org/wiki/LaTeXhttp://en.wikibooks.org/wiki/LaTeXhttp://en.wikibooks.org/wiki/LaTeXhttp://groups.google.com/group/latexusersgroup/browse_thread/thread/c6ed6da4cdf07995?pli=1http://groups.google.com/group/latexusersgroup/browse_thread/thread/c6ed6da4cdf07995?pli=1http://groups.google.com/group/latexusersgroup/browse_thread/thread/c6ed6da4cdf07995?pli=1http://groups.google.com/group/latexusersgroup/browse_thread/thread/c6ed6da4cdf07995?pli=1http://groups.google.com/group/latexusersgroup/browse_thread/thread/c6ed6da4cdf07995?pli=1http://groups.google.com/group/latexusersgroup/browse_thread/thread/c6ed6da4cdf07995?pli=1http://groups.google.com/group/latexusersgroup/browse_thread/thread/c6ed6da4cdf07995?pli=1http://groups.google.com/group/latexusersgroup/browse_thread/thread/c6ed6da4cdf07995?pli=1http://en.wikibooks.org/wiki/LaTeXhttp://www.mps.mpg.de/homes/daly/latex/grf.pdfftp://www.ctan.org/ctan/macros/latex/required/graphics/grfguide.pdfhttp://tex.stackexchange.com/questions/23075/packages-graphics-vs-graphicxftp://ctan.tug.org/tex-archive/macros/latex/contrib/easylist/easylist-doc.pdf


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Part IV

PART IV: Tools

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1.4. XILINX TOOLS 21

1.4 Xilinx Tools

1.4.1 ISE

1.4.2 Coregenerator

The Coregenerator is a tool for providing customizable cores for each FPGAand a wide range application that may use specific FPGA features.

1.4.3 MET- Memory Endpoint Test Driver

1.4.3.1 Description

Xilinx Provides a special tool named Memory Endpoint Test Driver (MET).This tool allows the implementation of test suites on the Programmed In-put/Output (PIO) design examples for the Xilinx PCIe Endpoint Cores.

It is important to notice that this is not a generic or skeleton driverthat could be used in generic user designs. It is tailored for use ONLY oncore design examples and requires some customization of those cores, thuslimiting the core use in other applications. In addition the source code ofthe driver/application is not available.

The documentation for this demonstration driver can be found in XAPP1022(v2.0) November 20, 2009.

To be able to use and test the generated PIO design example the follow-

ing steps are required (described in XAPP1022).

Core Customization: When generating the core (and corresponding PIO)it is required to follow some rules and settings like the use of a singleMemory Base Address Register (BAR) among others.

Core Implementation: The default settings of the PIO design examplesare able to access trough multiple access types but when using METit is recommended to change the source (.vhdl) files foe accessing onlytrough 32-bit addressable memory space.

Driver Installation: It is required to install the specific driver for the

PCIe endpoints.

Using MET application: MET application can run in several modes: Com-mand Line, Interactive Command Line, running an .ini test suite ortrough a Graphical User Interface (GUI).

1.4.3.2 Application

MET has several modes of operation (as seen previously). For increasedusability the following procedure should be followed.
http://www.xilinx.com/support/documentation/application_notes/xapp1022.pdfhttp://www.xilinx.com/support/documentation/application_notes/xapp1022.pdfhttp://www.xilinx.com/support/documentation/application_notes/xapp1022.pdfhttp://www.xilinx.com/support/documentation/application_notes/xapp1022.pdf


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1. Define individual WRITE procedures: Each individual write

procedure should be laid down in and individual .ini file. With thisprocedure the control over what is written is good. The followingfeature are available (see XAPP1022):

Execute multiple tests.

Set the base address and length of the data block written.

Select different types of access to selected memory or IO space(Write, Read and Write with Readback).

Data Pattern selection (Walking 0, Walking 1, All 0, All 1,Alternating 1/0 pattern and random). In addition custom valuesare also permitted.

MET can call directly the .ini file, but in this case the tests run inCONTINOUS MODE. This is not the usual test required, so thesefiles serve as a support for running scripts.

2. Create Scripts: Running MET using a scripts provides a much pow-erful control over the tests. The scripts may write or read for everyaccessible space and in addition are able to call .ini testfiles and run-ning them ONLY ONCE. This is a key feature that determines theuse of this mode. Scripting allows also to dump the results into a logfile, documenting the tests for later view.

1.5 Eclipse Guide

This section is devoted to Eclipse.

1.5.1 Eclipse Description

1.5.1.1 Eclipse Settings

Editor Font SizeThe default settings for Eclipse Editor Consolas 12 10pt. In somecases these settings are not desirable. To change them go to Window Preferences and changed them like presented in Figure 1.2.

Second Issue This is the second issue.


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1.5. ECLIPSE GUIDE 23

Figure 1.2: Eclipse General Text Preferences window.


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Part V

PART V: Resources

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1.6. SOME RESOURCES AVAILABLE TO USE 27

1.6 Some resources available to use


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Part VI

PART VI: Standards

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Chapter 2

Standards

2.1 AMBA

2.1.1 AXI Interface

(Paragraph is obsolete and should be moved.) This section describes theAXI interface with limited detail, as required by implementation of Xilinxcores and interfaces.

2.1.1.1 AXI Standard

The AXI-4 is part of a larger Open Specification for on-chip interconnection

that was develped by ARM and is named AMBA.There are three versions of AXI-4.

AXI4: The AXI4 protocol is an update to AXI3 to enhance the performanceand utilization of the interconnect when used by multiple masters. Itincludes the following enhancements:

Support for burst lengths up to 256 beats

Quality of Service signalling

Support for multiple region interfaces

AXI4-Lite: AXI4-Lite is a subset of the AXI4 protocol intended for com-munication with simpler, smaller control register-style interfaces incomponents. The key features of the AXI4-Lite interface are:

All transactions are burst length of one

All data accesses are the same size as the width of the data bus

Exclusive accesses are not supported

AXI4-Stream: The AXI4-Stream protocol is designed for unidirectionaldata transfers from master to slave with greatly reduced signal routing.Key features of the protocol are:

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32 CHAPTER 2. STANDARDS

Supports single and multiple data streams using the same set of

shared wires Support for multiple data widths within the same interconnect

Ideal for implementation in FPGA

The following description os AXI standard is based on the specificationsgiven in ARM Documentation Center.

2.1.1.2 Basic Description

The AMBA-AXI protocol is a high performance protocol that is suited forhighly flexible interconnection architectures.

The main features of the protocol are:

separate address/control and data phases

support for unaligned data transfers, using byte strobes

uses burst-based transactions with only the start address issued

separate read and write data channels, that can provide low-cost DirectMemory Access (DMA)

support for issuing multiple outstanding addresses

support for out-of-order transaction completion

permits easy addition of register stages to provide timing closure.

There are a number of sub-sets and extensions that allow the optimiza-tion of AXI according to specific application. The most important of theseare:

Advanced eXtensible Interface (Version 4) - Lite specifications (AXI4-Lite): This is a simplified version of AXI.

AMBA 4 AXI Coherency Extensions (ACE): This is an extension formaintaining system coherence on memory access trough multiple AXIsystems. This extension has also a Lite version.

2.1.1.3 Basic Architecture

AXI is based on a Master-Slave architecture communicating trough a set oindependent or common set of Channels. The concept of Channel is ofkey importance in AXI. In addition to Master and Slave AXI also definesthe Interconnect, that is a logical interface that provides connection between
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022d/index.htmlhttp://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022d/index.html


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2.1. AMBA 33

multiple Masters and Slaves. Each device at the Interconnect mimics the

symmetrical device.A Channel in the AXI context is a logical (and physical) set of signal

that perform a given function with a given direction, either from Masterto Slave or Slave to Master. The Channels are defined standard and areindependent. Depict their independence, the devices may require to complya some kind of requirements.

AXI defines FIVE Transaction Channels:

Read Address: When a Master whats to read some data, it will ISSUEthe corresponding READ ADDRESS on this channel. There data ISNO transferred trough this channel. The flow direction in this channel

if FROM Master TO Slave.

Write Address: When a Master whats to Write some data, it will ISSUEthe corresponding WRITE ADDRESS on this channel. There data ISNO transferred trough this channel. The flow direction in this channelif FROM Master TO Slave.

Read Data: All data, requested by a Master is sent by the Slave on thischannel. The flow direction in this channel if FROM Slave TO Master.

Write Data: When a Master wants to write some data to a Slave, it sendALL data trough this channel. The flow direction in this channel if

FROM Master TO Slave.

Write Response: This channel is exclusively used by Slave to signal Mas-ter that it has received the data after a Write from the Master to theSlave. The flow direction in this channel if FROM Slave TO Master.

The Channels described above serve the only two access types that aredefined READS (Figure 2.1) and WRITES (Figure ??).

Figure 2.1: Channel architecture of reads.

In the operation analysis of AXI there a few aspects that differentiatethis protocol from others commonly used.


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Figure 2.2: Channel architecture of writes.

Figure 2.3: AXI Interface and Interconnect.

Point-to-Point Connection: AXI only defines connection (Interface) be-tween ONE Master and ONE Slave. This means that read/write op-erations are always between TWO well-known components.

The Interconnect: Generally, there is required to have more than oneMaster and/or Slave. In these conditions it is required to have anInterconnect which mimics the symmetrical device (see Figure ??).Note that there are no assumptions or requirement on HOW the In-terconnect should be implemented.

The Topology: Within a system with multiple Master and/or Slaves it

would seem complex to devise a topology that is effective. But moreimportant that the restriction imposed by the previous two items,is the freedom that they allow. Depict there is a requirement for aMaster-Slave interface, there is NO restriction on sharing channelsbetween multiple devices. This means that One Master can write toMultiple Slaves or send data to multiple devices. This sharing of chan-nels allow the definition in a per-system basis of the best topology andstill maintain protocol architecture. The sharing of channels is definedat system development time and is not bound to any restrictions. Still,there are some topologies that are most often used:


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2.1. AMBA 35

Shared address and data buses.

Shared address buses and multiple data buses.

Multilayer, with multiple address and data buses.

Register Slicing: The Channel operation (that is UNIDIRECTIONAL)and independence, means that each channel register can be sliced orextended without any penalty in performance of individual transfers.

2.1.1.4 AXI Signal Description

In Table 2.1 is presented the AXI signal list. It contains global signals (thatare not part of any channel) and a per-channel listing. It also emphasis on

the sub-set of signals that are used in AXI4-Lite and the handshake signalsused in every transaction channel.

The detailed description of all signal can be found in the Standard defi-nition.

Table 2.1: AXI4 Interface Signals. In gray are presented the AXI4-Litesub-set. In pink the channel handshake signals.

GlobalLow-power

Write ad-dress chan-nel

Write datachannel

Write re-sponsechannel

Read ad-dress chan-nel

Read datachannel

ACLK AWID WID BID ARID RID

ARESETn AWADDR WDATA BRESP ARADDR RDATA

CSYSREQ AWLEN WSTRB BUSER ARLEN RRESP

CSYSACK AWSIZE WLAST BVALID ARSIZE RLAST

CACTIVE AWBURST WUSER BREADY ARBURST RUSER

AWLOCK WVALID ARLOCK RVALID

AWCACHE WREADY ARCACHE RREADY

AWPROT ARPROT

AWQOS ARQOS

AWREGION ARREGION

AWUSER ARUSER

AWVALID ARVALIDAWREADY ARREADY

2.1.1.5 AXI Interface

As we have seen so far AXI only defines a Master-Slave interface. Has wealso have seen this interface is done trough five transaction channels that arecompletely independent and thus they all require (and have) an handshakeprocess. This


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2.1.1.6 AXI-Lite Standard

Table 2.2: AXI4-Lite Interface Signals

Global Write ad-dress chan-nel

Write datachannel

Write re-sponsechannel

Read ad-dress chan-nel

Read datachannel

ACLK AWVALID WVALID BVALID ARVALID RVALID

ARESETn AWREADY WREADY BREADY ARREADY RREADY

AWADDR WDATA BRESP ARADDR RDATA

AWPROT WSTRB ARPROT RRESP


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Part VII

PART VII: Projects

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2.2. TECHNICAL PROJECTS 39

2.2 Technical Projects

This is the section???

2.2.1 ATCA-PTSW-AMC4 RTMO

2.2.1.1 Introduction

[o Purpose o Scope o Definitions, Acronyms And Abbreviations o Referenceso Overview /1 Section 1 is the introduction and includes a description of theproject, applicable and reference documents. /2 Section 2 provides a systemoverview. /3 Section 3 contains the system context. /4 Section 4 describesthe system design method, standards and conventions. /5 Section 5 con-

tains the component descriptions. /6 Section 6 includes the RequirementsTraceability Matrix. ]

This section describes the ATCA-PTSW-AMC4 RTMO module develop-ment and features. It was developed under the Fast Plant System Controller(FPSC) project for Latin word for journey or way. (Former acronym for In-ternational Thermonuclear Experimental Reactor.) (ITER)1 undertakenby Instituto de Plasmas e Fusao Nuclear (IPFN).

The ATCA-PTSW-AMC4 RTMO module is intended to extend connec-tivity of the In-House developed Advanced Telecom Computing Architecture(AdvancedTCA) front Boards, allowing remote host control over optical fi-bre cable.

2.2.1.2 System Overview

[o System Characteristics o System Architecture o Infrastructure Servicesa. Security b. Audit c. Performance monitoring and reporting d. ErrorHandling e. Debugging f. Logging. ]

[Include System Context]

2.2.1.3 System Design

[o Design Methods and Standards o Documentation Standards (DocumentTemplates) o Naming Conventions - DNA o Programming Standards (pro-

gramming style) - DNA o Software Development Tools - DNA o OutstandingIssues o Decomposition Description ]

1ITER (originally an acronym of International Thermonuclear Experimental Reactor)is an international nuclear fusion research and engineering project, which is currently build-ing the worlds largest and most advanced experimental tokamak nuclear fusion reactorat Cadarache in the south of France. The ITER project aims to make the long-awaitedtransition from experimental studies of plasma physics to full-scale electricity-producingfusion power plants. The project is funded and run by seven member entities the Euro-pean Union (EU), India, Japan, the Peoples Republic of China, Russia, South Korea andthe United States. The EU, as host party for the ITER complex, is contributing 45% ofthe cost, with the other six parties contributing 9% each.


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2.2.1.3.1 Design Methods and Standards

2.2.1.3.2 Outstanding Issues

2.2.1.3.3 Block Diagram

2.2.1.4 PCI Express Host Interface

[5.n Component identifier o 5.n.1 Type o 5.n.2 Purpose o 5.n.3 Function o5.n.4 Subordinates o 5.n.5 Dependencies o 5.n.6 Interfaces o 5.n.7 Resourceso 5.n.8 References o 5.n.9 Processing o 5.n.10 Data ]

The PCIe Host Interface block contains four quad-lanes optical inter-

faces. The ATCA-PTSW-AMC4 RTMO module acts as a downstream forall interfaces allowing multiple hosts controlling the AdvancedTCA frontboard. There is a direct connection and mapping from the PCIe lanes fromthe upstream connectors and the Advanced Rear Transition Module (RTM)connector.

Due to some design decision there were made it follows a set of issuesmust be separately evaluated and fully described.

Architectural Decisions: There are few solution for interconnecting thePCIe that supports multiple lanes and Gen1, Gen2 and possibly Gen3versions. The adopted solution is the one that seems to be the mostwide spread is the Quad Small Form-Factor Pluggable (QSFP) or

Quad Small Form-Factor Pluggable Plus (QSFP+) (for higher speeds).This standard is adopted trough a Multi-Source Agreement (MSA)from the major connector and interconnection vendors.

Depict this still remains some open options because QSFP+ only de-fines a cage and a connector. It not defines if the required transceiveris independent or part of the cabling system. Actually the two optionsare offered by many manufacturers. This lead to the problem of defin-ing the interface from the transceiver to the cable system. For this itwas decided (when required) to follow Multiple-Fiber Push-On/Pull-off; Multiple-Tuned-Fiber Push-On/Pull-off (MPO/MTP) standard,

basically for two main reasons: The selected transceiver (AFBR-79EQDZ) follows this standard.

This interface type is standardized by nternational Electrotech-nical Commission (IEC) under IEC 61754-7; Fibre optic inter-connecting devices and passive components Fibre optic connec-tor interfaces Part 7: Type MPO connector family; Edition 3.02008-03 (IEC-61754-7).

Since the adopted solutions provide a broad spectrum of actual imple-mentations, the respective possibilities should be made aware.


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2.2. TECHNICAL PROJECTS 41

PCB Connector: The selection of QSFP+ for interconnection fully de-

fine the connector (and respective cage). Several manufacturers canprovide connectors and cages:

Molex: QSFP+ Solutions. This includes Cages (EMI Cage Com-ponents) and PCB Connector (38 circuit iPass SMT Host Con-nector).

Transceiver (Optical or Electrical):

Connection Medium: Molex: QSFP+ and MPO/MTP Solutions.This includes Active Optical Cable Assemblies (QSFP+), PassiveCopper Assemblies, Passive Optical Assemblies (named OpticalJumper - MPO/MTP) and optical and copper loopbacks.

Card Design: The card (ATCA-PTSW-AMC4 RTMO) design followed theguidelines of the optical transceiver selected (AFBR-79EQDZ 2). Thismeans that PCIe lanes have no coupling capacitors, re-drivers or any

other type of active or passive electronics. The lines comply with a100 differential impedance.

Regarding side-band signal for PCIe they were implemented also ac-cording the transceiver specifications which is slightly different fromQSFP+ specifications. The adopted solution is described here (Issue#50).

The transceiver management trough I2C is kept and fully compliantwith QSFP+ specifications.

The following table presents some of the manufacturers that providesome solutions for using with QSFP+ interconnections. Note that someo these manufacturers usually have also support for other supports thatwe have not selected like SFP+, XFP and 10 Gigabit Ethernet (10 GbE)transceiver modules (XENPAK) among others.

2AFBR-79EQDZ transceiver from Avago Technologies (Avago Tech.) specificationscan be found in http://www.avagotech.com
http://www.molex.com/molex/products/family?key=quad_small_formfactor_pluggable_plus_qsfp_interconnect_solution&channel=products&chanName=family&pageTitle=Introductionhttp://www.molex.com/molex/products/family?key=quad_small_formfactor_pluggable_plus_qsfp_interconnect_solution&channel=products&chanName=family&pageTitle=Introductionhttps://sourceforge.net/userapps/mantisbt/acombo/view.php?id=50http://www.avagotech.com/pages/en/fiber_optics/parallel_optics/4-channel_transceivers/afbr-79eqdz/http://www.avagotech.com/pages/en/fiber_optics/parallel_optics/4-channel_transceivers/afbr-79eqdz/https://sourceforge.net/userapps/mantisbt/acombo/view.php?id=50http://www.molex.com/molex/products/family?key=quad_small_formfactor_pluggable_plus_qsfp_interconnect_solution&channel=products&chanName=family&pageTitle=Introductionhttp://www.molex.com/molex/products/family?key=quad_small_formfactor_pluggable_plus_qsfp_interconnect_solution&channel=products&chanName=family&pageTitle=Introduction


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42

Table 2.3: QSFP+ Manufacturer solutions.

PCBInfras-truc-ture

InterconnectionInfras-truc-ture

ManufacturerQSFP+Connector OpticalTransceiver(QSFP+?MPO/MTP)

Active Copper Cable (QSFP+) HostAdapters

AmphenolFCI QSFP+Full kit(10117436-001LF)

DNA DNA (10093084-1005LF)QSFP+CableAssem-bly, 32AWG,0.5meters

40Gbit/sQSFP-QSFPAOCICD040GVP1630-XY,ICD040GVP163D-XY

DNA DNA

Melanox ONLY

QSFP

ONLY

QSFPMolex 38CircuitiPass(ref.75586)

Singlecage(ref.74750).HeatSinksandlightpipes(ref.

74750).Mul-tipleoptionsexist.

MTP*/MPOAdaptersandCableAssem-blies

OneStopSystems DNA PCIeCableOSS-PCIe-CBL-x4

(alsoavail-lablex1; x8andx16ver-sions)

OSS-PCIe-CBL-ACT-x4

PCIeCableFiberOpticCableOSS-

PCIe-CBL-x4-100M-OPTICOSS-PCIe-CBL-

SeveralAdapters:http://www


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2.3. SECTION1 43

Figure 2.4: Molex QSFP+ Solutions.

2.2.2 DUMMY

2.3 section1

2.4 section2

2.4.1 subsection1

Notes for My Paper

Dont forget to include examples of topicalization. They look like this:

(car (cons 1 (2)))

Listing 1: Example of a listing.

Listing 1 contains an example of a listing.

1 int main() {2 printf("hello, world");

3 return 0;

4 }

his is a C function code.

Listing 2: T

Listing 2 contains an example of a listing Again.


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44

a new

1 from django.db import models2 from django.contrib.auth.models import User3

4 class TxtEntry(models.Model):5 short = models.CharField(max_length=100)6 addtime = models.DateTimeField(auto_now_add=True)7 chgtime = models.DateTimeField(auto_now=True)8 user = models.ForeignKey(User, blank=True, null=True, related_name=+)9 textin = models.TextField()

this is it ff t

1 entity spec_top is2 generic(3 -- link_gn4124 : boolean := false; --! Temporary removal of GNGN4124 (ACombo)4 PCIe_TYPE : string := "EX_DES"; -- PCIe Interface ("GN4124" | "ENDPOINT" | "EX_DES")5 TAR_ADDR_WDTH : integer := 13; --! Not used for this project6 g_SET_FPGA : string := "Virtex-6"; --! Set Virtex-6 FPGA Platform.7 PCIe_TYPE : string := "EX_DES" -- PCIe Interface "GN4124ENDPOINT" EX_DE

8 ); port9 (

10 -- Global ports11 clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock12

13 clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference14 clk_125m_pllref_n_i : in std_logic;15

16 --! PCI Express Region17 --! From GN4124 Local bus; Refurbished for PCIe from Coregen.18 L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)19 L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)20

21 L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)

22

23 -- General Purpose Interface24 GPIO : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO825 -- GPIO[1] -> GN4124 GPIO926

27 -- PCIe to Local [Inbound Data] - RX

28 P2L_RDY : out std_logic; -- Rx Buffer Full Flag

29 P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-30 P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+31 P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data32 P2L_DFRAME : in std_logic; -- Receive Frame33 P2L_VALID : in std_logic; -- Receive Data Valid

34

35 --! V6 Integrated PCIe Endpoint36 pcie_rxp : in std_logic_vector (0 downto 0) := "";37 pcie_rxn : in std_logic_vector (0 downto 0);38 pcie_txp : out std_logic_vector (0 downto 0);39 pcie_txn : out std_logic_vector (0 downto 0);40

41 -- Inbound Buffer Request/Status42 P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request43 P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready44 RX_ERROR : out std_logic; -- Receive Error45

46 -- Local to Parallel [Outbound Data] - TX47 L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data48 L2P_DFRAME : out std_logic; -- Transmit Data Frame49 L2P_VALID : out std_logic; -- Transmit Data Valid50

L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-51 L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+

52 L2P_EDB : out std_logic; -- Packet termination and discard53

54 -- Outbound Buffer Status55 L2P_RDY : in std_logic; -- Tx Buffer Full Flag56 L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write57 P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready58 TX_ERROR : in std_logic; -- Transmit Error59 VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready60

61 -- Font panel LEDs62 LED_RED : out std_logic;63 LED_GREEN : out std_logic;64

65 dac_sclk_o : out std_logic;66 dac_din_o : out std_logic;67 dac_clr_n_o : out std_logic;68 dac_cs1_n_o : out std_logic;


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2.4. SECTION2 45

69 dac_cs2_n_o : out std_logic := X"FUFFFF80";;70

7172 sfp_txp_o : out std_logic;73 sfp_txn_o : out std_logic;74

75 sfp_rxp_i : in std_logic;76 sfp_rxn_i : in std_logic;77

78 fpga_scl_b: inout std_logic;79 fpga_sda_b: inout std_logic;80

81 button1_i: inout std_logic;82 button2_i: inout std_logic;83

84 sfp_mod_def0_b : inout std_logic; -- rate_select85 sfp_mod_def1_b : inout std_logic; -- scl86 sfp_mod_def2_b : inout std_logic; -- sda87 sfp_rate_select_b : inout std_logic;88 sfp_tx_fault_i : in std_logic;89 sfp_tx_disable_o : out std_logic;90 sfp_los_i : in std_logic;91

92dio_o : out std_logic_vector(3 downto 0);

93 dio_en_n_o : out std_logic;94 dio_dir_o : out std_logic95

96 );97

98 end spec_top;99

100

101 cmp_dmtd_clk_pll : PLL_BASE102 generic map (103 BANDWIDTH => "OPTIMIZED",104 -- CLK_FEEDBACK => "CLKFBOUT",105 COMPENSATION => "INTERNAL",106 DIVCLK_DIVIDE => 1,107 CLKFBOUT_MULT => 50,108 CLKFBOUT_PHASE => 0.000,109 CLKOUT0_DIVIDE => 8, -- 62.5 MHz110 CLKOUT0_PHASE => 0.000,111 CLKOUT0_DUTY_CYCLE => 0.500,112 CLKOUT1_DIVIDE => 8, -- 125 MHz113 CLKOUT1_PHASE => 0.000,114 CLKOUT1_DUTY_CYCLE => 0.500,115 CLKOUT2_DIVIDE => 8,116 CLKOUT2_PHASE => 0.000,117 CLKOUT2_DUTY_CYCLE => 0.500,118 CLKIN_PERIOD => 50.0,119 REF_JITTER => 0.016)120 port map (121 CLKFBOUT => pllout_clk_fb_dmtd,122 CLKOUT0 => pllout_clk_dmtd,123 CLKOUT1 => open,124 CLKOUT2 => open,125 CLKOUT3 => open,126 CLKOUT4 => open,127 CLKOUT5 => open,128 LOCKED => open,129 RST => 0,130 CLKFBIN => pllout_clk_fb_dmtd,131 CLKIN => clk_20m_vcxo_buf);

This is after minted

(1) Topicalization from sentential subject:a Johni [a kltukl [el l-oltoir er ngiii a Mary]]

R-clear comp IR.3s-love P himJohn, (its) clear that Mary loves (him).

How to handle topicalization

Ill just assume a tree structure like (2).


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46

(2) Structure of A Projections:

CP

Spec C

C SAgrP

Mood

Mood changes when there is a topic, as well as when there is WH-movement.Irrealis is the mood when there is a non-subject topic or WH-phrase inComp. Realis is the mood when there is a subject topic or WH-phrase.

Guide Manual1

Documents

Transcript of Guide Manual1