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Green Transistor for 10X Lower IC Power ? Chenming Hu University of California, Berkeley Supported by: DARPA STEEP, FCRP-MSD Slide 2 Electronics Infrastructure 6/2009 Chenming Hu the world enabled IC chips fabs transistors electronic systems $ Slide 3 Expectation: ICs will be even more.. Affordable (size reduction..): manufacturing, device physics limit, Useful (speed, density..): natural human interface, bio-medical sensing Usable (low power): heat management, portability, global energy conservation 6/2009 Chenming Hu Slide 4 Power Consumption Problems 1.Thermal management/package issues may limit integration density. 2.IC usage of electricity at an inflection point. ICs use a few % of worlds electricity today and growing exponentially. Power per chip is growing. IC units in use also growing. 3.Need to reduce IC power consumption with architecture and circuit innovations, and a low voltage transistor. 6/2009 Chenming Hu Slide 5 Because power consumption V dd 2 and V dd (operation voltage) scaling has slowed. High Performance ITRS Roadmap Technology Node 0.25 m 0.18 m 0.13 m 90 nm 65 nm 45 nm 32 nm 22 nm 16 nm V dd 2.5 V1.8 V1.3 V1.2 V1.1 V1.0 V0.9 V0.8 V0.7 V IC Power Consumption Rising Much Faster Than Past Trend 6/2009 Chenming Hu Slide 6 Why V dd scaling slowed We used to control power by scaling V dd and maintain good speed by reducing T ox. But, T ox can not be reduced much more, not even with high-k dielectrics. But new materials will raise the mobility, 1.2 nm SiO 2 Speed transistor current ( V dd V t ) / T ox 6/2009 Chenming Hu Slide 7 New material, e.g. Ge film on Si substrate Industry is also funding InGaAs, InAs, and graphene MOSFET research. Oxide Silicon Drain Source Gate 3nm Ge film 6/2009 Chenming Hu Slide 8 How to Reduce Power by 20X Two steps to reduce V dd to 0.2V for 20x power reduction? 1. Reduce V dd V t to < 0.15V with high- mobility-channel material (Ge, III-V, graphene...), etc. 2. Reduce V t to 50mV. But, there is the fundamental 60mV/decade turn-off limit .. 6/2009 Chenming Hu Slide 9 9 Lowering V t by 60mV increases the leakage current (power) by 10 times. Source: Intel Corporation 6/2009 Chenming Hu VtVt Drain Current, I DS (A/ m) Gate Voltage, V GS (V) 0.00.30.60.9 10 -11 10 -9 10 -7 10 -5 10 -3 Lower V t I off Limit - 60mV/decade Swing Slide 10 The fundamental 60mV/decade Limit Electrons go over a potential barrier. Leakage current is determined by the Boltzmann distribution or 60 mV/decade, limiting MOSFET, bipolar, graphene MOSFET How to overcome the limit: Let electrons go through the energy barrier, not over it tunneling 10 6/2009 Chenming Hu EcEc EvEv C OX VGVG SourceChannelDrain Slide 11 Semiconductor Band-to-Band Tunneling ECEC EVEV 6/2009 Chenming Hu A known mechanism of leakage current since 1985. J. Chen, P. Ko, C. Hu, IEDM 1985 Called Gate Induce Drain Leakage (GIDL) because the current depends on the gate voltage. Slide 12 Basic Tunnel Transistor Structure Some references ~100X less current than MOSFET Need a more optimal tunneling transistor structure. P+ DrainN+ Source P- 12 W. Reddick, G. Amaratunga, Appl. Phys. Letters, vol. 67, 1994. W. M. Reddick, et al., Appl. Phys. Lett., vol. 67(4), pp. 494-497, 1995. C. Aydin, A. Zaslavsky, et al., Appl. Phys. Lett., vol. 84(10), pp. 1780-82, 2004. WY. Choi et al., Tech. Dig. Int. Electron Device Meet, pp. 955-958, 2005. K. K Bhuwalka, et al., Jpn. J. of Appl. Phys., vol. 45(4B), pp. 3106-3109, 2006. Th. Nirschl, et al., Electron Device Letters, vol. 28(4), p. 315, 2007. 6/2009 Chenming Hu Slide 13 Large field, good capacitive coupling between gate and pocket, abrupt turn-on due to over-lap of valence/conduction bands, adjustable tun-on voltage. Green Transistor (gFET)--Simulation 13 Energy band diagram Simulated carrier generation rates Hole flow Electron flow N+ Source P+ Pocket Gate P+ Drain N+P+ Buried Oxide P+ Pocket P- 6/2009 Chenming Hu C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008 G DS Slide 14 gFET vs Basic Tunnel FET-simulation * K. K Bhuwalka, et al., Jpn. J. of Appl. Phys., vol. 45(4B), pp. 3106-3109, 2006 EOT= 1 nm V DD =1V Lg=40nm Gate Voltage, V GS (V) gFET EOT= 4.5 nm V DD =4V Drain Current, I DS (A/m) Basic Tunnel FET * 6/2009 Chenming Hu C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008 Slide 15 Simulated I d -V d of 0.5V Ge gFET Good output resistance and DIBL. Lg = 40nm Drain-Source Voltage, V DS (V) Drain Current, I DS (A/m) EOT=0.5nm 6/2009 Chenming Hu C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008 Slide 16 Vdd (Power) Scaling Path: Reduce Band Gap C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008 6/2009 Chenming Hu 1E-11 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 1E-02 0.00.20.40.60.81.0 Ids (A/um) Eg=0.36eV (InAs) Eg=0.69eV (Ge) Silicon Eg=0.36eV, Vdd=0.2V, EOT=5 , CV/I=0.42pS Eg=0.69eV, Vdd=0.5V, EOT=7 , CV/I=2.2pS Eg=1.1eV, Vdd=1V, EOT=10 , CV/I=4.2pS Gate Voltage, V GS (V) Drain Current, I DS (/m) Lg=40nm Slide 17 P+ SourceN+ Drain B Substrate Gate A ECEC EVEV Gate Oxide Gate A B E geff Hetero-tunneling gFET In lieu of low E g semiconductor, a heterojunction can provide a very small effective tunneling band gap, E geff. Egeff is 0.3eV for Si/Ge hetero-tunneling gFET. 6/2009 Chenming Hu A. Bownder et al., 8th International workshop Junction Technology, Extended Abstracts, p.93, 2008. Also IEEE Silicon Nanoelectronics Workshop, 2008. Slide 18 Compound Semiconductors 18 E geff Example: InAs-AlGaSb provides tunable E geff from positive to negative values. Very low voltage gFET may be possible. Wide choices of heterojunction materials, band engineering and strain engineering. 6/2009 Chenming Hu Slide 19 Source SiO2 Si N+ Si Drain P+ Ge Gate I D [A/ m] Experiment Model V GS [V] Ge-Source Tunnel Transistor S. Kim et al., VLSI Tech Symp., 2009 Es = |V GS +Vtunnel|/(Tox ge/ ox) Vtunnel ~ 0.6V S [mV/dec] I D [A/ m] V D =0.5V L G =5 m W=0.33 m Slide 20 Greens Function Based Simulation Sayeef Salahudin Slide 21 ICs use of worlds electricity is several % and growing fast. A low voltage transistor can slow the growth. Green Transistor may potentially provide orders-of-magnitude IC power reduction. Summary 6/2009 Chenming Hu