Graduate Institute of Electronics Engineering National Taiwan University...

Graduate Institute of Electronics Engineering

National Taiwan University

國立台灣大學電子工程學研究所

Short TalkShort Talk

Optimal Designs of CMOS Circuits via Optimal Designs of CMOS Circuits via Geometric ProgrammingGeometric Programming

Yu-Shun Wang

Dec. 27th 2007

NTU GIEE Graduate Institute of Electronics Engineering



OutlineOutline Introduction Convex Optimizing

Geometric Form GP solver

Applications RFIC - LNA Operating Amplifier Adder

Future Challenge

2



國立台灣大學電子工程學研究所3

ThinkingThinking When a designer has a good idea,

a new topology or a new design theory will be born in few days. But the designer has to tune all performance well for weeks.

Including parasitic resistors and capacitors, the performance won’t be predictable easily. So the ineffective fine tune will take 80% effort in a circuit.

If unfortunately, the idea doesn’t work…and time goes by.

So a good automatic optimization EDA tool is necessary.

New Idea

Well Design

Compared with Design Goal

Deciding Topology

Handy Calculation

Fine Tune !!




AdvantagesAdvantages

1. A lot of develop time can be saved.

2. We can change specification easily.

3. By only updating the transistor data, we can

port a design to a new process immediately.

4. Geometric programming encapsulates the

experienced designer’s knowledge.






Applications Operating Amplifier LNA Adder

Future Challenge

5




Fundamental ConceptFundamental Concept

Convex form

yFyFyyF 11




Fundamental ConceptFundamental Concept Quasi convex function

7




Convex standard From

where , are convex functions.

Fundamental ConceptFundamental Concept

8

xf0 mixf i ,...,2,1,1

pixg i ,...,2,1,1

nixi ,...,2,1,0

Minimize

Subject to

xfi xgi




Geometric ProgrammingGeometric Programming

Geometric Program Standard From A geometric program is an optimization problem

where are posynomial function, and are monomial function.

Convex Form ?

t

k

kan

kakakn

nxxxcxxf1

211 ...,..., 21

xf0 mixf i ,...,2,1,1

pixg i ,...,2,1,1

nixi ,...,2,1,0

Minimize

Subject to

xfi xgi





How can Geometric Program be Solved To convert geometric program to convex optimization

Assume ,we minimize ,then

iyi ex

mief yi ,...,2,1,0log

pieg yi ,...,2,1,0log

Minimize

Subject to

yef0log

yef0log





How can Geometric Program be Solved Therefore, if

Under the transformation, it becomes

Assume ,then for any y, and any with

, then Geometric Program can convert to convex standard form.

In term of original posynominal f, the convex form is following

Posynomial !!

yefyF 0log

yFyFyyF 11

10

nny xaxacef loglogloglog 11

nan

aa xxcxxf ...2121

nnnn xxfxxfxxxxf ~,,~,,~,,~11

1111







Future Challenge

12




GP solverGP solver1. Define target (Min or Max something)

2. Define constraint

3. http://www.stanford.edu/~boyd/ggplab/

4. Rewrite formula in matrix format

5. Feed Matlab with matrix.m

13




GP solverGP solver

14

matrix.m

Matlab.mat




GP solverGP solver

15

Assign variable

Constraint matrix

Call function

Rewrite performance

Objective matrix




GP solverGP solver

16

Rewrite performance

iterations

Solved results






Applications RFIC – LNA Operating Amplifier Adder

Future Challenge

17




RFIC - LNARFIC - LNA




Low Noise Amplifier (LNA)Low Noise Amplifier (LNA)

RF Circuits using Geometric Programming

50

1

gsGS

gs

Smin C

LLjC

LgZ

11

11

1

111

ir EEa

bS 1

112

1

221

ir EEa

bS

12

11

2

112

ir EEa

bS 1

212

2

222

ir EEa

bS

2

01

Tsd

S

G

S

L RgR

R

R

RNF

1. Input Impedance

2. S-parameter (S11 、 S21, 、 S12 、 S22)

3. NF (Noise Figure)

50111 gsSm CLg

5.05.0 gsSG CLL

12200

1 TSdSGL RgRRRNF

Posynomial !!

Posynomial !!

Signomial -> Posynomial !!




LNALNA

13

22

3

22

122

1.9

1100

23

50.8

12

12

1.7

1)(2

10

102log10

10log10.6

12255

39.0

155

9.0

155

9.0

1.050

50

1050

50log10.5

18.0.4

118.0

18.0.3

4.0.2

14.0

4.0.1

111

11

211

11

1

2

22

12

111

11

15.01

5.01

5.0

111

111

11

2

2

15.01

5.01

5.0

1

1

21

111

11

15.01

5.01

1

111

11

2

11

2

11

SoxGox

SgsGgs

gsSG

oxSDox

gsSm

DTGSox

TGSoxD

DD

ox

DDox

Om

oxSDox

gsSm

in

in

in

in

in

LCLWf

LCLWf

LCfLCf

CLL

CLWLLWIC

CLg

ILWVVC

VVL

WCI

LjLWIC

LjL

WIC

RgS

CLWLLWIC

CLg

Z

Z

Z

Z

ZS

umL

LumL

umW

WumWtosubject

IVDDnimizemi




LNALNA

]10110[

]01110[3

]015.15.05.0[2

]00111[1

]015.05.05.0[4

]015.05.11[3

]00100[2

]00010[1

]00001[0

11

G

G

G

A

A

A

A

A

LLLWIdVar GS

1;1*Cox/1e12*1e9)^2/3*2.4*3.1415*(2*23

0/CoxCox)^2/500*Un*(2*3*1e122

Vt)^2-(Vgs*Cox*Un*0.51

dCox)^0.5/L*Un*10/(24

oxCox)^0.5/C*Un*(2*3/55/2*0.9*1e123

18.02

4.01

0

11

H

H

H

B

B

B

B

VddB

LLLWIdVar GS




Experience ResultExperience Result

Target Optimize

Technology － 0.18-μm CMOS

Frequency 2.4 2.4

W1 >0.4 0.4

L1 >0.18 0.397

Supply Voltage 3 3

Power Dissipation minimum 7.56

S21 >23 23

S11 =-∞ -355







Future Challenge

23




Maria del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee, “Optimal Design of a CMOS Op-Amp via Geometric Program ming,” IEEE Transactions on Computer-aided Design of Inte grated Circuits and Systems, vol. 20, no. 1, Jan. 2001.

24

2-Stage Operating Amplifier2-Stage Operating Amplifier

Output

Input+ Input-




Small Signal ModelSmall Signal Model

DnDS

do IV

Ir

1

1

or

25




Small Signal ModelSmall Signal Model

26

or

DnDS

do IV

Ir

1

1




First performance: Gain

27


766422 oomoomv rrgrrgA

DnDnDoxn

DnDnDoxn IIL

WIC

IIL

WIC

1

||1

21

||1

22

2

2

2

7162

622

2

IILL

WWCpn

pn

ox




Second performance: Pole

28


4321

1111

1

ps

ps

ps

ps

AsH V

TLCTLC

Cm

CCCCCC

Cgp

11

62

143

33

gdgsgs

m

CCC

gp

426

64

gdgdgs

m

CCC

gp

VCo ACCRp

1

1

111

VC

m

VCo AC

g

ACR1

1

1





Performance Formula

2531

31

13

31 22

ILL

WWC

gg

ggCMRR pn

ppn

ox

oo

mm

TLCC CC

I

C

IRateSlew 71 ,

2min

567342

632

2

2

omomoo

mmm

gggggg

gggPSRRPositive

21

642

62

11

1

ps

psggg

ggPSRRNegative

ooo

mm

Posynomial !!

Posynomial !!

Inverse

Posynomial !!




Optimization of OP-AmpOptimization of OP-Amp




Optimization of OP-AmpOptimization of OP-Amp

Constraint

maxmin LLL i maxmin WWW i

iico LWCArea 21 maxmin AAA v

Maximize Chip size

Subject to

dBILL

WWC

gg

ggCMRR pn

ppn

ox

oo

mm 6022

2531

31

13

31

dBIILL

WWCrrgrrgA pn

pn

oxoomoomv 80

2

7162

622766421




ConstraintConstraint

bias

bias

biasDD

DD

c

IH

IH

H

IVPower

VB

GianB

B

B

B

B

B

B

B

B

B

C

B

3

2

21

1

111

var_

1010

29

28

27

26

8.05

8.04

8.03

8.02

8.01

1

1

1

2

2

0

8

]10010010000[3

]01010000100[2

]00101011110[1

]10000000000[

]01000000000[11

]5.05.05.0005.005.0005.0[10

]00100000000[9

]00010000000[8

]00001000000[7

]00000100000[6

]00000010000[5

]00000001000[4

]00000000100[3

]00000000010[2

]00000000001[1

]00000000000[

]00010010000[

]00100001000[

]00010000100[

]00001000010[

]00000100001[071653176531

G

G

G

A

A

A

A

A

A

A

A

A

A

A

A

IILLLLWWWWW




Experience ResultExperience ResultUnit target Optimized

Technology －－ 0.8-μm CMOSW1 um >0.8 0.8W2 um >0.8 0.8W3 um >0.8 43W4 um >0.8 43W5 um >0.8 0.8W6 um >0.8 86W7 um >0.8 0.8L1 um >2 2L2 um >2 2L3 um >2 2L4 um >2 2L5 um >2 344L6 um >2 1.6L7 um >2 344

Supply Voltage V 3 3Chip Size um2 minimum 836

Power Dissipation mW <50 50Open loop gain dB >80 80




Optimal Design ResultOptimal Design Result




Ignore some factor… body effect channel length modulation junction capacitance….

Caparison with real modelCaparison with real model

35




Fit the nonlinear modelFit the nonlinear model Rewrite gm

36




LimitationLimitation Accuracy model ?

GP0 Hspice level-1 GP1 Hspice level-39 ( 0.8um CMOS Bsim 3v1) ?? 90nm CMOS Bsim 3v3……..

37







Future Challenge

38




HCA radix-2 ArchitectureHCA radix-2 Architecture

4 3 02 114 7 663

30

31

15... ... ...

L2

L4

L6

L1

L3

L5

562

Odd

Sum ... ... ...

• Generate even carries using radix-2 (P,G)

• Generate odd carries from even carries

• CMOS adder for sum

• 1-b cell width 4m

• 10-stage critical path

(p,g)

XOR2NAND2

NOR2OAI

CM6CM1

NAND2AOI

NOR2OAI

CM2 CM3

NAND2AOI

NOR2OAI

CM4 CM5

AOI

OAI

CMo

XOR2NAND2

XOR2

XOR2

SumCiN

Evenbits

Oddbits

39




KS radix-4 ArchitectureKS radix-4 Architecture

63 62 5961 60 4 3 02 18 57 648 1632 12... ...... ... ...

G4P4

G16P16

CoSum

40




Novel ArchitectureNovel Architecture

Gather all critical path

KS

Radix - 2

41




Critical Path ProblemCritical Path Problem How to synchronize all path? Use GP !! (Transistor sizing)

42

16

24

32




Minimize critical path’s delay time by increase device width

Solved by Geometric ProgramSolved by Geometric Program

Minimize all device’s widths by synchronizing critical path delay time to get low power consumption

43




1: Delay Time Model1: Delay Time Model

44

Process-depend parameter

Target variable

Assign variable




2: Minimize Delay Time2: Minimize Delay Time

45





46

Optimized Ws

Minimized Delay time

3pF 3pF 3pF





47

Optimized Ws

Minimized Delay time

0.1 3pF 6pF




3: Minimize Ws3: Minimize Ws

48

Minimize all Ws by synchronizing critical path’s delay Time





49

Minimize Ws

Synthesize critical path’s delay time




Transistor SizingTransistor Sizing

50

Design new topology adder Synchronizing all path’s delay Time Minimize Widths to save power dissipation

16 paths

24 paths

32 paths






Applications Operating Amplifier LNA Adder

Future Challenge

51




Future ChallengeFuture Challenge Thanks for RDC providing UMC 90nm tech. Some papers about adders

Mathew, S.; Anders, M.; Krishnamurthy, R.K.; Borkar, S.; “A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core,” IEEE, JSSC JSSCVolume 38, Issue 5, pp. 689 – 695, May 2003.

Y. Shimazaki, R. Zlatanovici, B. Nikolic, “A Shared-Well Dual-Supply Voltage 64-bit ALU,” ISSCC Dig. Tech. Papers, pp.104-105, Feb., 2003.

S. Mathew, et al, “A 4GHz 300mW 64b Integer Execution Unit ALU with Dual Supply Voltages in 90nm CMOS,” ISSCC Dig. Tech. Papers, pp.162-163, Feb., 2004.

Klaus von Arnim, Peter Seegebrecht, Rpland Thewes, Christian Pacha, “A Low-Leakage 2.5GHz Skewed CMOS 32b Adder for Nanometer CMOS Technologies,” ISSCC Dig.Tech.Papers, pp. 380-605, Feb., 2005.

Sean Kao, Radu Zlatanovici, Borivoje Nikolic, “A 240ps 64b Carry-Lookahead Adder in 90nm CMOS,” ISSCC Dig.Tech.Papers, pp. 1735-1744, Feb., 2006.

Wijeratne, S. B., Siddaiah, N., Mathew, S. K., Anders, M. A., Krishnamurthy, R. K., Anderson, J., Ernest, M., Nardin, M.,” A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit,” IEEE, JSSC Volume 42, Issue 1, pp.26 – 37, Jan. 2007.

Accuracy nonlinear Model ? Chung-Ping Chen, Chris C. N. Chu, and D. F. Wong, "Fast and Exact Simultaneous Gate

and Wire Sizing by Lagrangian Relaxation," IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 18, No. 7, pp. 1014-1025, July 1999.

52




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