GPMC Bus Interface to CAMIF Connectivity Solution TI ... · © 2013 QuickLogic Corporation † †...

For Use with the Texas Instruments-Based AM335x Processor

General Purpose Memory Controller (GPMC) Bus Interface to Camera Interface (CAMIF) Connectivity Solution Texas Instruments Reference Design Data Sheet

• • • • • •

CSSP FeaturesQuickLogic® has developed a Customer Specific Standard Product (CSSP) to provide a camera interface bridge for the Texas Instruments Sitara AM335x processor line. It is designed to connect a 10-bit parallel interface to the AM335x GPMC 16-bit multiplexed address/data bus. The reference design based on the QuickLogic PolarPro platform, using an Aptina 3.1 MP sensor and is available from CircuitCo or BeagleBoard.org as part their Camera Cape for the BeagleBone system.

This CSSP meets the specifications and requirements defined by Texas Instruments to provide a complete high performance, low power CAMIF for the AM335x family of processors. This CSSP includes the following features:

GPMC Interface LogicThe GPMC interface to the AM335x supports:

• 16-bit multiplexed address/data bus with address valid signal

NOTE: Only bit [7:0] of the GPMC bit [15:0] address/data bus is connected to valid data. The system must configure GPMC as 16-bit to take advantage of the DMA burst capability.

• NOR Flash synchronous burst access, 16-word burst cycle

• Direct Memory Access (DMA) request for high-performance data transfer

NOTE: For the solution to operate correctly, the CSSP DMA request (GPMC_DMAR) must be connected to one of the Texas Instruments AM335x GPIO pins configured as XDMA_EVENT_INTR (e.g., set AM335x pin GPIO0_7 to mode 6 for configuration as XDMA_EVENT_INTR2).

• GPMC clock speed of 50 MHz

• 3.3 V support

CAMIF LogicThe CAMIF logic connects to a camera sensor with a 10-bit parallel bus, such as the Aptina MT9T111. The CAMIF to the sensor supports:”

• Up to 30 frames per second (fps) at VGA (640 x 480) resolution

• Up to 96 MHz clock speed

• RAW 8-bit Bayer pattern or RGB565 or YUV formats

• Camera pixel clock input

• Camera frame valid input

• Camera line valid input

• 2.8 V support

OverviewQuickLogic’s CSSP technology, combining customizable silicon platforms, PSBs, and software drivers, can help OEMs and ODMs address the connectivity gap with a single chip solution optimized for the TI-based AM335x processor, enabling smaller PCB space requirements, much lower power consumption and lower BOM costs.

This connectivity solution offers designers the integration and flexibility to accelerate time-to-market and differentiation in the mobile market. The CSSP provides a unique combination of hard logic and ultra-low power programmable fabric based on QuickLogic’s patented ViaLink® technology for adapting as market conditions change, resulting in longer time-in-market. Custom drivers are provided for Linux and Android platforms.

The QuickLogic CSSP enhances processors to support emerging new standards and customer feature requirements, resulting in an improved user experience.

© 2013 QuickLogic Corporation www.quicklogic.com••• •••

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http://www.quicklogic.com

General Purpose Memory Controller (GPMC) Bus Interface to Camera Interface (CAMIF) Connectivity Solution Texas Instruments Reference Design Data Sheet Rev. 1.1

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System ArchitectureFigure 1 shows the system architecture of the connectivity solution for the Texas Instruments AM335x processor to a camera sensor.

Figure 1: QuickLogic CSSP Connectivity System Architecture

Performance DetailsThe following pixel formats are supported:

• RAW Bayer

• RGB565

• YUV

Table 1 shows the supported resolution and performance for CSSP-FPUN86-6544.

The following factors affect system performance:

• The performance of the GPMC bus.

• Dynamic Random-Access Memory (DRAM) is a shared resource, so the activity in the system can reduce the amount of bandwidth available to the Enhanced Direct Memory Access (EDMA) and GPMC bus.

• Additional CPU bandwidth is required when the sensor output format is different than the application display format.

• Additional CPU bandwidth is required when the sensor output resolution to the application window resolution.

Table 1: Supported Resolution and Performance

Resolution PerformancePower Consumed

(Maximum)

VGA (640 x 480) 30 fps 56 mW

CSSP

LCD 7”

SPI

I2C

GPMC (8-Bit)

HS/VS/DE/PCLK

CAMIF

CLK

Texas Instruments

AM335x

CameraSensor

with 10-bitParallel

InterfaceDMAR

www.quicklogic.com © 2013 QuickLogic Corporation•• ••••




General Purpose Memory Controller (GPMC) Bus Interface to Camera Interface (CAMIF) Connectivity Solution TexasInstruments Reference Design Data Sheet Rev. 1.1

Functional and Module Description

Figure 2 shows a detailed block diagram of the GPMC-CAMIF architecture.

Figure 2: GPMC-CAMIF Block Diagram

The camera data can either be in RAW 8-bit Bayer or RGB format. In either format, the AM335x is responsible for converting the data into the proper format for display on an LCD panel.

• In RAW Bayer format, the CSSP stores the data as a 16-bit value with the lower 8 bits containing the 8 bits of image data and the upper 8 bits with zeros.

• In YUV format, the CSSP stores each byte of sensor data as a 16-bit value and outputs to the GPMC bus based on the sensor output configuration. In this configuration, only bit [7:0] contains valid data, bit [15:8] are not used. For example, in the case of the Aptina sensor, it can be programmed to output in four different ways, so the data on the GPMC bus would appear as follows:

Default (no swap)

MT9T111 Cbi => GPMC_AD[7:0]a GPMC[15:8] = don’t care

MT9T111 Yi => GPMC_AD[7:0]a GPMC[15:8] = don’t care

MT9T111 Cri => GPMC_AD[7:0]a+1 GPMC[15:8] = don’t care

MT9T111 Yi+1 => GPMC_AD[7:0]a+1 GPMC[15:8] = don’t care

Swapped CrCb

MT9T111 Cri => GPMC_AD[7:0]a GPMC[15:8] = don’t care


MT9T111 Cbi => GPMC_AD[7:0]a+1 GPMC[15:8] = don’t care


DataFIFO

GPMCInterface

fifo_data_indata_fifo_data

id_control

CAM_D[9.0]

CAM_FRAME_VALID

CAM_LINE_VALID

CAM_PCLK

fifo_pop

GPMC_CLK

CameraInterface

GPMC_AD[7:0]

output_sel

fifo_push

CAM_PCLK

GPMC_CSXN

GPMC_DMAR

GPMC_CLKGPMC_ADVNGPMC_WENGPMC_OEN

ID/ControlRegister

16

© 2013 QuickLogic Corporation www.quicklogic.com• • • •••

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4

Swapped YC


MT9T111 Cbi => GPMC_AD[7:0]a GPMC[15:8] = don’t care


MT9T111 Cri => GPMC_AD[7:0]a+1 GPMC[15:8] = don’t care

Swapped CrCb, YC


MT9T111 Cri => GPMC_AD[7:0]a GPMC[15:8] = don’t care


MT9T111 Cbi => GPMC_AD[7:0]a+1 GPMC[15:8] = don’t care

Data from the CAMIF is stored in a 1024-word FIFO. When the CSSP detects assertion of the CAM_FRAME_VALID and CAM_LINE_VALID signals from the camera sensor, the CSSP begins to store the camera sensor data into the data FIFO. After the FIFO initially fills with the programmed number of words, the CSSP logic asserts the DMA request signal, GPMC_DMAR, to inform the AM335x DMAC that data is ready for transfer. The AM335x DMAC has less than 1004 camera pixel clocks cycles to begin reading the data FIFO before the CSSP stops storing the camera sensor data.

During synchronous burst read cycles over the GPMC bus, the CSSP output data appears in the following 16-bit format on every clock cycle until the read cycle is completed.

• For RAW Bayer:

GPMC_AD[7:0] = RAW 8-bit bayer pattern

GPMC_AD[15:8] = 00000000

• For RGB:

GPMC_AD[7:0] = RGB byte

GPMC_AD[15:8] = 00000000






Memory Maps

GPMC Host Memory Map

CSSP Register Address Map

CSSP Registers and Descriptions

CSSP Register Set

ID Register (Address: 0x00)

This register provides the IP version number of the CSSP.

GPMC Host Address Memory Description

0000-00FF CSSP Register

CSSP Register Offset Register Description

0000 IP Version GPMC_AD[7:0] with valid data

0002 Control Register [7:0]

0080 CSSP Data FIFO

0100 – 1FFF Reserved

Name Address Size Typea

a. RW = Read/WriteRO = Read OnlyRO-RC = Read Only and Read Cleared

Description

ID 0x00 1 byteRW/RO/RO-RC

IP version number

Control 0x02 1 byteRW/RO/RO-RC

Control register

Data FIFO data 0x80 2 bytes RO Camera sensor data

Reserved 0x100 – 0xFFF N/A N/A N/A

Name Bit Typea

a. RO = Read Only

Description

IP Version 7:0 RO IP version number


5



6

Control Register (Address: 0x02)

This register provides the control/status of the CSSP.

Data FIFO Port (Address: 0x80)

This is the data FIFO containing the camera data. The FIFO is 1024-words deep. If the FIFO overflows, no new sensor data will be stored.

Name Bit Typea

a. RW = Read/WriteRO = Read OnlyRO-RC = Read Only and Read Cleared

Description

FIFO Empty Flag 0 ROData FIFO empty status0: Data FIFO is not empty1: Data FIFO is empty

FIFO Overflow Flag 1RO-RC

Data FIFO overflow status0: No overflow1: Overflow

Reserved 2 RO Don’t care

DMA Control 3 RWDMA request transfer size0: Set 16 words per DMA request1: Set 4x16 words per DMA request

CSSP Enable 4 RWEnable CSSP to start and capture camera data at the start of the next frame0: Disabled1: Enabled

Reserved 5 RW Reserved

Pixel Clock Edge 6 RWSelect active pixel clock edge0: Rising-edge1: Falling-edge

Data Format 7 RWData format select from the camera sensor0: RAW10 Bayer1: RGB/YUV

Name Bit Typea

a. RO = Read Only

Description

RAW Bayer Format

Image Data 7:0 RO 8-bit RAW Bayer pattern image data

Reserved 15:8 RO Reserved, zero-filled

RGB Format

Even Data Byte 7:0 RO RGB data byte of image data

Odd Data Byte 15:8 RO Reserved, zero-filled






Electrical SpecificationsDC CharacteristicsThe DC Specifications are provided in Table 2 through Table 5.

Table 2: Absolute Maximum Ratings

Parameter Value Parameter Value

VCC Voltage -0.5 V to 2.2 V ESD Pad Protection 2 kV

VCCIO Voltage -0.5 V to 4.0 VLeaded Package

Storage Temperature-65° C to + 150° C

Input Voltage -0.5 V to 4.0 V Laminate Package (BGA)Storage Temperature

-55° C to + 125° CLatch-up Immunity ±100 mV

Table 3: Recommended Operating Range

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 1.71 1.89 V

VCCIO I/O Input Tolerance Voltage 1.71 3.60 V

TJ Junction Temperature 0 85 °C

Table 4: DC Characteristics

Symbol Parameter Conditions Min. Typ. Max. Units

Il I or I/O Input Leakage Current VI = VCCIO or GND - - 1 µA

IOZ 3-State Output Leakage Current VI = VCCIO or GND - - 1 µA

CI I/O Input Capacitance VCCIO = 3.6 V - - 10 pF

CCLOCK Clock Input Capacitance VCCIO = 3.6 V - - 10 pF

IVCC Quiescent Current - - 40 100 µA

IVCCIO Quiescent Current on VCCIO

VCCIO = 3.6 V - 2 10 µA

VCCIO = 2.75 V - 2 10 µA

VCCIO = 1.89 V - 2 10 µA

Table 5: I/O Input and Output Levels

SymbolVIL VIH VOL VOH IOL IOH

VMIN VMAX VMIN VMAX VMAX VMIN mA mA

LVTTL -0.3 0.8 2.2 VCCIO + 0.3 0.4 2.4 2.0 -2.0

LVCMOS2 -0.3 0.7 1.7 VCCIO + 0.3 0.7 1.7 2.0 -2.0

LVCMOS18 -0.3 0.63 1.2 VCCIO + 0.3 0.7 1.7 2.0 -2.0


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8

AC Characteristics

CAMIF CSSP Timing

Figure 3 shows the GPMC bus interface timing.

Figure 3: GPMC Bus Interface Timing

Table 6 shows the GPMC bus timing parameters. The GPMC Register Configurations column shows the AM335x register settings.

Table 6: GPMC Bus Timing Parametersa

a. GPMC_CLK is 50 MHz.

Parameter (on GPMC Side)

Number of Clock Cycles

GPMC Register Configurations

GPMC FCLK Divider 1 GPMCFCLKDIVIDER = 1

ClkActivationTime 2 CLKACTIVATIONTIME = 2

RdAccessTime 14 ACCESSTIME = Eh

RdCycleTime 16 RDCYCLETIME = 10h

WrCycleTime 31 WRCYCLETIME = 1Fh

CsOnTime 1 CSONTIME = 1

CsReadOffTime 16 CSRDOFFTIME = 10h

CsWriteOffTime 31 CSWROFFTIME = 1Fh

AdvOnTime 0 ADVONTIME = 0

AdvRdOffTime 4 ADVRDOFFTIME = 4h

AdvWriteOffTime 4 ADVWROFFTIME = 4h

OeOnTime 6 OEONTIME = 6h

OeOffTime 16 OEOFFTIME = 10h

WeOnTime 6 WEONTIME = 6h

WeOffTime 31 WEOFFTIME = 1Fh

AD[7:0]nCSnADVnOEnWECLK






Read and Write Timing

Figure 4 shows the GPMC Write timing diagram.

Figure 4: GPMC Write Timing Diagram7

Table 7 describes the GPMC Write timing.

Table 7: GPMC Write Timing7

Symbol ParameterCSSP-FPUN86-6494 CSSP-FPUN86-6517

Min. Max. Min. Max.

tADSUG nADV setup time to CLK 4.67 ns - 4.65 ns -

tADHLG nADV hold time to CLK 0 ns - 0 ns -

tCSSUG nCS setup time to CLK - - 4.90 ns -

tCSHLG nCS hold time to CLK - - 0 ns -

tWESUG nWE setup time to CLK 2.60 ns - 2.89 ns -

tISUG GPMC Writing AD setup time to CLK 3.01 ns - 2.74 ns -

tIHLG GPMC Writing AD hold time to CLK 0 ns - 0 ns -


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10

Figure 5 illustrates the GPMC Write timing.

Figure 5: GPMC Write Timing






Figure 6 shows the GPMC Read timing diagram.

Figure 6: GPMC Read Timing Diagram

Table 8 describes the GPMC Read timing.

Table 8: GPMC Read Timing


Min. Max. Min. Max.

tOESUG nOE setup time to CLK 2.85 ns - 4.29 ns -

tCOClock-to-out from GPMC CLK edge to GPMC AD

6.83 ns 9.44 ns 6.83 ns 9.44 ns


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12

Figure 7 illustrates the GPMC Read timing.

Figure 7: GPMC Read Timing






Bandwidth Considerations When Configuring the Camera Sensor

The CSSP receives data from the sensor and supplies it to the DMA system in the Texas Instruments AM335x processor. The CSSP has a FIFO to accommodate fluctuations in data rates. However, if the sensor data rate consistently exceeds the rate that the DMA can accept the data, the FIFO will eventually overflow and the frame will be discarded. Thus, it is critical to ensure that the sensor is configured to have a lower data bandwidth than the DMA bandwidth.

The measured maximum sustainable DMA throughput on a lightly loaded system is 28 M transfers/s (see Figure 8). In YUV or RGB mode, each 16 bit word corresponds to a half-pixel, so the DMA system is capable of handling up to 14 M YUV or RGB pixels/s. This CSSP supports VGA (640 x 480) at 30 frames per second for YUV or RGB format.

DMA Bandwidth

Figure 8 illustrates the DMA bandwidth for CSSP-FPUN86-6544.

Figure 8: DMA Bandwidth for CSSP-FPUN86-6544

The time between two adjacent CSSP-issued DMA requests is measured by scope using the following equation for CSSP-FPUN86-6544:

64 bytes= 28.14 MBytes/sec

2.2737 µs


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14

Camera Interface Input Timing

The Camera Interface supports 96 MHz camera_clk input. The calculated result shows that the maximum frequency input clock can be up to 100 MHz.

Figure 9 shows the Camera Interface.

Figure 9: Camera Interface

Table 9 describes the Camera Interface timing.

Figure 10 illustrates the Camera Interface timing.

Figure 10: Camera Interface Timing

Table 9: Camera Interface Timing


Min. Max. Min. Max.

tIVSUC Frame_valid/Line_valid setup time to camera CLK 0 ns - 2.02 ns -

tIVHLC Frame_valid/Line_valid hold time to camera CLK 4.95 ns - 0 ns -

tISUC Camera image data setup time to camera CLKa

a. The active edge of camera CLK is configurable. See Memory Maps on page 5 and CSSP Registers and Descriptions on page 5.

0 ns - 1.83 ns -

tIHLC Camera image data hold time to camera CLKa 4.96 ns - 0 ns -

CAM_D[9:0]

Frame_validLine_valid

CLK






Supported Operating SystemsTable 10 shows the operating systems currently supported.

Power-Up SequencingDuring power-up, current consumption of the CSSP is minimized by keeping VCCIO within 500 mV of VCC.

Initialization SequencingFor proper CSSP operation, the following sequence of events must occur upon power-up or reset:

1. Assert the reset signal for 1 µs and then deassert reset.

2. Enable the CAMIF pixel clock.

3. Perform a dummy read of the CSSP over the GPMC bus.

4. Initialize the CSSP.

5. Enable the camera sensor to capture an image to begin sending the data to the CSSP.

Table 10: Supported Operating Systems

Operating System Android Linux 3.2.x WinMobile 6.x WinMobile 7

Supported Yes Yes No No


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Signal DescriptionsTable 11: Signal Descriptions

Signal Direction Description Voltage

GPMC Bus Interface

GPMC_AD[15:0] I/OGPMC address/data bus, muxed. GPMC_AD[15:8] is not used, but must be configured as a 16-bit access.

v3p3

GPMC_CLK I GPMC bus clock. v3p3

GPMC_CSXN I GPMC chip select. v3p3

GPMC_OEN I GPMC output enable. v3p3

GPMC_WEN I GPMC write enable. v3p3

GPMC_ADVN I GPMC address valid. v3p3

GPMC_DMAR O GPMC DMA request, active-high. v3p3

Camera Interface

CAM_PCLK I Camera pixel clock v2p8

CAM_FRAME_VALID I Camera frame valid v2p8

CAM_LINE_VALID I Camera line valid v2p8

CAM_D[9:0] I Camera data bus v2p8

Miscellaneous

RESETN I System reset v3p3

Supplies

VCC I Power supply pin. v1p8

GND I Common ground. GND

VCCIO(A-D) I

These pins provide the flexibility to interface the device with either a 3.3 V or 2.8 V device. The letter inside the parenthesis means that the VCCIO is located in the bank with that letter. Every I/O pin in the same bank will be tolerant of the same VCCIO input signals and will drive VCCIO level output signals.

A-D

DNC N/A Do Not Connect. Leave floating. N/A






CSSP 86-Ball (6 mm x 6 mm) TFBGA Pinout TableTable 12 shows the ball connections for the CSSP 86-ball (6 mm x 6 mm) TFBGA package.

Table 12: CSSP 86-Ball (6 mm x 6 mm) TFBGA Pinout Table

Pin Pin Name Voltage Type Bank

A1 v1p8 v1p8 VCC -

A2 GND v3p3 I/O D

A3 GND v3p3 I/O D

A4

A5 DNC v3p3 I/O D

A6 RESETN v3p3 CLK D

A7

A8 DNC v3p3 I/O D

A9 GND v3p3 I/O D

A10

A11 v1p8 v1p8 VCC -

B1 GND GND GND -

B2 GPMC_AD7 v3p3 I/O C

B3 GND v3p3 I/O D

B4 GND v3p3 I/O D

B5 GND v3p3 I/O D

B6 GND v3p3 I/O D

B7 GND v3p3 I/O D

B8 DNC v3p3 I/O D

B9 DNC v3p3 I/O D

B10 GND GND GND -

B11 GND GND GND -

C1

C2 GPMC_AD6 v3p3 I/O C

C3 GPMC_AD5 v3p3 I/O C

C4

C5

C6

C7

C8

C9 GND GND GND -

C10 CAM_FRAME_VALID v2p8 I/O A

C11

D1 GPMC_AD4 v3p3 I/O C

D2


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18

D3

D4 v3p3 v3p3 VCCIO D

D5 v1p8 v1p8 VCC -

D6 GPMC_DMAR v3p3 I/O D

D7 DNC v3p3 I/O D

D8

D9 CAM_LINE_VALID v2p8 I/O A

D10

D11 CAM_D0 v2p8 I/O A

E1 GPMC_AD3 v3p3 I/O C

E2

E3

E4 GPMC_AD2 v3p3 I/O C

E5 v3p3 v3p3 VCCIO D

E6 GND GND GND -

E7 GND GND GND -

E8 v2p8 v2p8 VCCIO A

E9 v2p8 v2p8 VCCIO A

E10

E11 CAM_D1 v2p8 I/O A

F1 GPMC_AD1 v3p3 I/O C

F2 GPMC_AD0 v3p3 I/O C

F3

F4 GND GND GND -

F5 GND GND GND -

F6

F7 GND GND GND -

F8 v1p8 v1p8 VCC -

F9 CAM_D2 v2p8 I/O A

F10

F11

G1 GPMC_CLK v3p3 I/O D

G2 v2p8 v2p8 VCCIO B

G3 GPMC_ADVN v3p3 I/O C

G4 v1p8 v1p8 VCC -

G5 v3p3 v3p3 VCCIO C

G6 GND GND GND -

G7 GND GND GND -

Table 12: CSSP 86-Ball (6 mm x 6 mm) TFBGA Pinout Table (Continued)







G8 v1p8 v1p8 VCC -

G9

G10 CAM_D3 v2p8 I/O A

G11 CAM_PCLK v2p8 CLK A

H1 GPMC_WEN v3p3 I/O C

H2 GPMC_OEN v3p3 I/O C

H3

H4

H5 v3p3 v3p3 VCCIO C

H6 GND GND GND -

H7 v2p8 v2p8 VCCIO B



H10 CAM_D4 v2p8 I/O A

H11 CAM_D5 v2p8 I/O A

J1

J2 GPMC_CSXN v3p3 I/O C

J3

J4 DNC v2p8 I/O B

J5

J6

J7

J8

J9

J10 CAM_D6 v2p8 I/O A

J11

K1 GND GND GND -

K2 DNC v2p8 I/O B

K3 DNC v2p8 I/O B

K4 DNC v2p8 I/O B

K5

K6 DNC v2p8 I/O B

K7 DNC v2p8 I/O B

K8 CAM_D9 v2p8 I/O B

K9

K10 CAM_D7 v2p8 I/O A

K11 CAM_D8 v2p8 I/O A

L1 v1p8 v1p8 VCC -




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20

L2 DNC v2p8 I/O B

L3

L4 DNC v2p8 I/O B

L5 GND GND CLK B

L6 GND GND CLK B

L7 DNC v2p8 I/O B

L8 DNC v2p8 I/O B

L9 v3p3 v3p3 - -

L10 GND GND GND -

L11 v1p8 v1p8 VCC -








Packaging Pinout Diagram

86-Pin TFBGA Packaging

Top

Bottom

QL1P100-7PUN86C


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22

Mechanical Drawings86-Pin TFBGA Packaging Drawing






Reference Schematic

Figure 11: Reference Schematic5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

nAD

V

GPM

CC

LK

CAM

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CAM

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CAM

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CAM

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CAM

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CAM

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CAM

_D6

CAM

_D7

CAM

_D8

CAM

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CAM

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CAM

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DG

ND

DG

ND

VDD

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VDD

_2V8

DG

ND

VDD

_1V8

VDD

_2V8

VDD

_3V3

VDD

_1V8

DG

ND

DG

ND

VDD

_3V3

GPM

C_n

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ALE

2

GPM

C_C

LK2

GPM

C_A

D0

2

GPM

C_A

D1

2

GPM

C_A

D2

2

GPM

C_A

D3

2

GPM

C_A

D4

2

GPM

C_A

D5

2

GPM

C_A

D6

2

GPM

C_A

D7

2

GPM

C_A

D8

2

GPM

C_A

D9

2

GPM

C_A

D10

2

GPM

C_A

D11

2

GPM

C_A

D12

2

GPM

C_A

D13

2

GPM

C_A

D14

2

GPM

C_A

D15

2

GPM

C_n

WE

2,3 G

PMC

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E_nR

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3GPM

C_n

CS1

2,3

CAM

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4

CAM

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4

CAM

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23



24

PCB Breakout






QuickLogic CSSP Connection to the Aptina SensorFigure 12 shows the QuickLogic CSSP connection to the Aptina Sensor for 10-bit sensor output.

Figure 12: 10-Bit Sensor Output

Figure 13 shows the QuickLogic CSSP connection to the Aptina Sensor for RGB/YUV sensor output.

Figure 13: RGB/YUV Sensor Output

Aptina SensorQuickLogic CSSP

CAM_D[9:2]

CAM_LINE_VALIDCAM_FRAME_VALID

CAM_PCLKCAM_D[1:0]

D[7:0]

LINE_VALIDFRAME_VALIDPIXCLKGPIO[1:0]

Aptina SensorQuickLogic CSSP

CAM_D[9:2]

CAM_LINE_VALIDCAM_FRAME_VALID

CAM_PCLKCAM_D[1:0]

D[7:0]

LINE_VALIDFRAME_VALIDPIXCLK


25



26

Reflow ProfileFigure 14 shows the Pb-free component preconditioning reflow profile.

Figure 14: Pb-Free Component Preconditioning Reflow Profile

Table 13 shows the Pb-free component preconditioning reflow profile.

NOTE: All temperatures are measured on the package body surface.

Table 13: Pb-Free Component Preconditioning Reflow Profile

Profile Feature Profile Conditions

Ramp-up rate 3°C/sec. max. (2°C/sec. typical)

Preheat time (from 150°C to 200°C) 60 to 180 sec. (80 to 100 sec. typical)

Time maintained above 217°C 60 to 150 sec. (80 to 100 sec. typical)

Peak temperature 260°C

Time within 5°C of actual peak 20 to 40 sec. (23 to 29 sec. typical)

Ramp-down rate 6°C/sec. max. (3°C/sec. typical)

Time from 25°C to peak temperature 8 min. max. (6 min. typical)






Moisture Sensitivity Level

All TFBGA devices are Moisture Sensitivity Level 3. Table 14 shows the solder composition.

Ordering InformationThe ordering information is presented in Table 15.

Contact Information

Phone: (408) 990-4000 (US)

+(44) 1932-21-3160 (Europe)

+(886) 26-603-8948 (Taiwan)

+(86) 21-2116-0532 (China)

+(81) 3-5875-0547 (Japan)

+(82) 31-601-4225 (Korea)

E-mail: [email protected]

Sales: [email protected]

[email protected]

[email protected]

[email protected]

[email protected]

Support: www.quicklogic.com/support

Internet: www.quicklogic.com

Table 14: Solder Composition

Package Type Pin Count Lead Type Pb-Free

TFBGA (6 mm x 6 mm)

86 BGA Solder Sn-3Ag-Cu (Sn4, Ag, Cua)

a. Sn-3Ag-Cu (Sn, 4Ag, Cu) means that Ag can range from 3% to 4%. Cu is always 0.5%.

Table 15: Packaging Options

Packagea

a. TFBGA = Thin Fine Ball Grid Array

Part Number

86-ball TFBGA CSSP-FPUN86-6544


27


mailto:[email protected]






http://www.quicklogic.com/support

http://www.quicklogic.com/


28

Revision History

Notice of Disclaimer

QuickLogic is providing this design, product or intellectual property "as is." By providing the design, product or intellectual property as one possible implementation of your desired system-level feature, application, or standard, QuickLogic makes no representation that this implementation is free from any claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. You are responsible for obtaining any rights you may require for your system implementation. QuickLogic shall not be liable for any damages arising out of or in connection with the use of the design, product or intellectual property including liability for lost profit, business interruption, or any other damages whatsoever. QuickLogic products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use QuickLogic products in these types of equipment or applications.

QuickLogic does not assume any liability for errors which may appear in this document. However, QuickLogic attempts to notify customers of such errors. QuickLogic retains the right to make changes to either the documentation, specification, or product without notice. Verify with QuickLogic that you have the latest specifications before finalizing a product design.

Copyright and Trademark Information

Copyright © 2013 QuickLogic Corporation. All Rights Reserved.

The information contained in this document is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited.

QuickLogic, ArcticLink, pASIC, PolarPro, the PolarPro design, QuickPCI, QuickRAM, and ViaLink are registered trademarks, and Eclipse, EclipsePlus, Eclipse II, QuickWorks and the QuickLogic logo are trademarks of QuickLogic. Other trademarks are the property of their respective companies.

Revision Date Originator and Comments1.0 August 2013 Initial release.

1.1 September 2013

Anthony Le and Kathleen BylsmaUpdated GPMC to 8-bit in Figure 1.Updated to GPMC_AD[7:0] in Figure 2.Changed GPMC Host Address to 0000-00FF.Updated to AD[7:0] in Figure 3.





GPMC Bus Interface to CAMIF Connectivity Solution TI ... · © 2013 QuickLogic Corporation † †...

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