GLS85LP0512P / 1002P / 1004P / 1008P Industrial … GLS85LP0512P / 1002P / 1004P / 1008P Industrial...

Data Sheet 01.000 June 2011

These specifications are subject to change without notice. 06/15/2011 © 2011 Greenliant Systems 1 S71431

GLS85LP0512P / 1002P / 1004P / 1008P

Industrial Grade PATA NANDrive™

Features• Industry Standard ATA / IDE Bus Interface

- Host Interface: 16-bit access

- Supports up to PIO Mode-6 1)

- Supports up to Multi-Word DMA Mode-4 2)

- Supports up to Ultra DMA Mode-4

• Performance

- Sustained sequential data read - Up to 50 MByte/sec

- Sustained sequential data write - Up to 39 MByte/sec

• Power Management

- 3.3V power supply - Immediate disabling of unused circuitry without

Host intervention - Zero wake-up latency

• Power Specification

- Active mode 110mA typical (GLS85LP1008P) 80mA typical (GLS85LP1004P) 60mA typical (GLS85LP1002P) 60mA typical (GLS85LP0512P)

- Sleep mode 500µA typical (GLS85LP1008P) 500µA typical (GLS85LP1004P) 450µA typical (GLS85LP1002P) 450µA typical (GLS85LP0512P)

• Expanded Data Protection

- WP#/PD# pin configurable by firmware for prevention of data overwrites

- Data security through user-selectable protection zones

- Security Erase feature

• 20-Byte Unique ID for Enhanced Security

- Factory pre-programmed 10-Byte unique ID - User-programmable 10-Byte ID

• Integrated Voltage Detector

- Prevents inadvertent Write operations due to unexpected power-down or brownout

• Pre-programmed Embedded Firmware

- Executes industry standard ATA/IDE commands - Implements advanced wear-leveling algorithms to

substantially increase the longevity of flash media - Embedded Flash File System

• Robust Built-in ECC

• Industrial Temperature Range

- -40°C to 85°C

• 91-ball BGA and LBGA Packages

- 14mm x 24mm x 1.90mm (GLSLP1002P / 1004P / 1008P)

- 12mm x 24mm x 1.40mm (GLSLP0512P)

• All Devices are RoHS Compliant

Product Description

The GLS85LP0512P / 1002P / 1004P / 1008P Industrial Grade PATA NANDrive™ devices (referred to as “PATA NANDrive” in this datasheet) are high-performance, fully-integrated, embedded flash solid-state drives. They combine an integrated ATA Controller and 512 MByte, 2 GByte, 4 GByte or 8 GByte of NAND flash memory in a multi-chip package. These products are ideal for solid-state mass storage in embedded and portable applications that require smaller form-factor and more reliable data storage.

ATA-based solid-state mass storage technology is widely used in GPS and telematics, in-vehicle infotainment, portable and industrial computers, handheld data collection scanners, point-of-sale terminals, networking and telecommunications equipment, robotics, audio and video recorders, monitoring devices and set-top boxes.

The PATA NANDrive supports standard ATA/IDE protocol with up to PIO Mode-6

1), Multi-Word DMA Mode-4

2) and Ultra

DMA Mode-6 interface. The PATA NANDrive device provides complete IDE hard disk drive functionality and compatibility in a 14mm x 24mm BGA package or a 12mm x 24mm LBGA package for easy, space-saving mounting to a system motherboard. These products surpass traditional storage in their small size, security, reliability, ruggedness and low power consumption.

The integrated NAND flash controller with built-in advanced NAND management firmware communicates with the Host through the standard ATA protocol. It does not require any additional or proprietary software such as the Flash File System (FFS) and Memory Technology Driver (MTD).

The PATA NANDrive provides a WP#/PD# pin to protect critical information stored in the flash media from unauthorized overwrites. The PATA NANDrive is pre-programmed with a 10-Byte unique serial ID and has the option of programming an additional 10-Byte serial ID for even greater system security.

The PATA NANDrive’s advanced NAND management technology enhances data security, improves endurance and accurately predicts the remaining lifespan of the NAND flash devices. This innovative technology combines robust error correction capabilities with advanced wear-leveling algorithms and bad block management to significantly extend the life of the product.

1) PATA NANDrive is capable of supporting PIO Mode-6, but Identify-Drive information report will show PIO Mode-4

2) PATA NANDrive is capable of supporting Multi-Word DMA Mode-4, but Identify-Drive information report will show MWDMA Mode-2



GLS85LP0512P / 1002P / 1004P / 1008P


Contents

1.0 GENERAL DESCRIPTION..................................................................................................................................... 3

1.1 Optimized PATA NANDrive .................................................................................................................................... 3 1.1.1 Microcontroller Unit (MCU) ..................................................................................................................................... 3 1.1.2 Internal Direct Memory Access (DMA) ................................................................................................................... 3 1.1.3 Power Management Unit (PMU)............................................................................................................................. 3 1.1.4 SRAM Buffer .......................................................................................................................................................... 3 1.1.5 Embedded Flash File System................................................................................................................................. 3 1.1.6 Error Correction Code (ECC) ................................................................................................................................. 3 1.1.7 Serial Communication Interface (SCI) .................................................................................................................... 3 1.1.8 Multi-tasking Interface ............................................................................................................................................ 3 1.2 NAND Flash ........................................................................................................................................................... 3 1.3 Advanced NAND Management .............................................................................................................................. 3 2.0 FUNCTIONAL BLOCKS......................................................................................................................................... 4 3.0 PIN ASSIGNMENT................................................................................................................................................. 4 4.0 KEY PARAMETERS .............................................................................................................................................. 7 5.0 CONFIGURABLE WRITE PROTECT / POWER-DOWN MODES ......................................................................... 8 5.1 Write Protect Mode................................................................................................................................................. 8 5.2 Power-down Mode ................................................................................................................................................. 8 5.3 Security Erase ........................................................................................................................................................ 8 6.0 POWER-ON INITIALIZATION ................................................................................................................................ 8 7.0 ATA/IDE HOST INTERFACE ................................................................................................................................. 8 7.1 Serial Communication Interface (SCI) .................................................................................................................... 8 8.0 LIFETIME EXPECTANCY...................................................................................................................................... 8 9.0 POWER-ON AND BROWN-OUT RESET CHARACTERISTICS............................................................................ 9 10.0 SOFTWARE INTERFACE...................................................................................................................................... 9 10.1 I/O Transfer Function ............................................................................................................................................. 9 10.2 Command Description.......................................................................................................................................... 10 10.2.1 Identify-Drive – ECh ............................................................................................................................................. 11 10.2.2 Set-Features – EFh .............................................................................................................................................. 20 10.2.3 Idle – 97h or E3h .................................................................................................................................................. 21 10.2.4 Set-Sleep-Mode – 99h or E6h .............................................................................................................................. 21 10.2.5 Set-WP#/PD#-Mode - 8Bh ................................................................................................................................... 21 10.2.6 Error Posting ........................................................................................................................................................ 22 11.0 ELECTRICAL SPECIFICATIONS ........................................................................................................................ 23 11.1 Absolute Maximum Ratings.................................................................................................................................. 23 11.1.1 Absolute Maximum Power Pin Stress Ratings ..................................................................................................... 23 11.2 Operating Ratings ................................................................................................................................................ 23 11.3 AC Characteristics................................................................................................................................................ 23 11.3.1 AC Conditions of Test .......................................................................................................................................... 23 11.4 Recommended System Power-on Timing ............................................................................................................ 24 11.5 Reliability Characteristics

30)................................................................................................................................. 24

11.6 Capacitance 30)

..................................................................................................................................................... 24 11.7 Purge Erase Time ................................................................................................................................................ 24 11.8 DC Characteristics ............................................................................................................................................... 25 12.0 APPENDIX ........................................................................................................................................................... 26 12.1 Differences between the PATA NANDrive and the ATA Specifications................................................................ 26 12.1.1 Idle Timer ............................................................................................................................................................. 26 12.1.2 Recovery from Sleep Mode.................................................................................................................................. 26 12.2 Reflow Profile ....................................................................................................................................................... 26 12.3 Product Ordering Information ............................................................................................................................... 27 12.4 Packaging Diagram .............................................................................................................................................. 28 12.4.1 FTE Package........................................................................................................................................................ 28 12.4.2 LBTE Package ..................................................................................................................................................... 29

12.5 Reference Documents.......................................................................................................................................... 30

12.6 Revision History................................................................................................................................................... 30



GLS85LP0512P / 1002P / 1004P / 1008P


1.0 GENERAL DESCRIPTION

Each PATA NANDrive contains an integrated PATA NAND flash memory controller and NAND flash die in a BGA or LBGA package. Refer to Figure 2-1 for the Industrial Grade PATA NANDrive block diagram.

1.1 Optimized PATA NANDrive

The heart of the PATA NANDrive is the PATA NAND flash memory controller, which translates standard PATA signals into flash media data and control signals. The following components contribute to the PATA NANDrive’s operation.

1.1.1 Microcontroller Unit (MCU)

The MCU transfers the ATA/IDE commands into data and control signals required for flash media operation.

1.1.2 Internal Direct Memory Access (DMA)

The PATA NANDrive uses internal DMA allowing instant data transfer from/to buffer to/from flash media. This implementation eliminates microcontroller overhead associated with the traditional, firmware-based approach, thereby increasing the data transfer rate.

1.1.3 Power Management Unit (PMU)

The PMU controls the power consumption of the PATA NANDrive. The PMU dramatically reduces the power consumption of the PATA NANDrive by putting the part of the circuitry that is not in operation into sleep mode.

The Flash File System handles inadvertent power interrupts and has auto-recovery capability to ensure the PATA NANDrive’s data integrity. For regular power management, the Host must send an IDLE_IMMEDIATE command and wait for command ready before powering down the PATA NANDrive.

1.1.4 SRAM Buffer

A key contributor to the PATA NANDrive performance is an SRAM buffer. The buffer optimizes the Host’s data transfer to and from the flash media.

1.1.5 Embedded Flash File System

The embedded flash file system is an integral part of the PATA NANDrive. It contains MCU firmware that performs the following tasks:

1. Translates host side signals into flash media writes and reads

2. Provides flash media wear leveling to spread the flash writes across all memory address space to increase the longevity of flash media

3. Keeps track of data file structures

4. Manages system security for the selected protection zones

5. Stores the data in flash media upon completion of a Write command (The PATA NANDrive does not perform Post-Write operations, except for when the write cache is enabled)

1.1.6 Error Correction Code (ECC)

High performance is achieved through optimized hardware error detection and correction.

1.1.7 Serial Communication Interface (SCI)

The Serial Communication Interface (SCI) is designed for manufacturing error reporting. During the design process, always provide access to the SCI port in the PCB design to aid in design validation.

1.1.8 Multi-tasking Interface

The multi-tasking interface enables fast, sustained write performance by allowing concurrent Read, Program and Erase operations to multiple flash media devices.

1.2 NAND Flash

The PATA NANDrive family utilizes standard NAND flash for data storage. Because the reflow process can alter the PATA NANDrive content, do not program the PATA NANDrive before the reflow process.

1.3 Advanced NAND Management

Advanced NAND management technology balances the wear on erased blocks with an advanced wear-leveling scheme. Advanced NAND management technology tracks the number of program/erase cycles within a group. When the Host updates data, higher priority is given to the less frequently written erase blocks; thereby, evenly distributing host writes within a wear-leveling group.

The product also supports a global wear-leveling feature, which can be enabled or disabled by the host command. When the global wear-leveling is enabled, the wear-leveling is performed both across and within the groups. Please contact Greenliant for more information about this feature. By default, global wear-leveling is enabled.

Advanced NAND management technology enhances the PATA NANDrive security with password protection and four independent protection zones, which can be set to Read-only or Hidden.



GLS85LP0512P / 1002P / 1004P / 1008P


2.0 FUNCTIONAL BLOCKS

Figure 2-1: PATA NANDrive Block Diagram

3.0 PIN ASSIGNMENT

The signal/pin assignments are listed in Table 3-1. Low active signals have a “#” suffix. Pin types are Input, Output or Input/Output. Signals that the Host sources are designated as inputs, while signals that the PATA NANDrive sources are outputs.

Figure 3-1: Pin Assignments for 91-Ball BGA / LBGA



GLS85LP0512P / 1002P / 1004P / 1008P


Table 3-1: Pin Assignments (1 of 2) Pin No.

Symbol 91-Ball

Pin

Type I/O Type Name and Functions

Host Side Interface

A2 K8

A1 K3

A0 L2

I I1Z A[2:0] are used to select one of eight registers in the Task File.

D15 H8

D14 G9

D13 G8

D12 H7

D11 F9

D10 F8

D9 E8

D8 F7

D7 F4

D6 H4

D5 E3

D4 H3

D3 F3

D2 G3

D1 F2

D0 G2

I/O

I1Z/O2

D[15:0] Data bus

DMACK# K2 I I2U DMA Acknowledge - input from Host

DMARQ J3 O O2 DMA Request to Host

CS1FX# L3 CS1FX# is the chip select for the task file registers

CS3FX# L8

I

I2Z CS3FX# is used to select the alternate status register and the Device Control register.

CSEL L9 I I1U

This internally pulled-up signal is used to configure this device as a Master or a Slave. When this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as a Slave. The pin setting should remain the same from Power-on to Power-down.

IORD#: This is an I/O Read Strobe generated by the Host. When Ultra DMA mode is not active, this signal gates I/O data from the device. (This pin supports three functions)

HDMARDY#: In Ultra DMA mode when DMA Read is active, this signal is asserted by the Host to indicate that the Host is ready to receive Ultra DMA data-in bursts. The Host may negate HDMARDY# to pause an Ultra DMA transfer.

IORD# H2 I I2Z

HSTROBE: When DMA Write is active, this signal is the data-out strobe generated by the Host. Both the rising and falling edges of HSTROBE cause data to be latched by the device. The Host may stop generating HSTROBE edges to pause an Ultra DMA data-out burst.

IOWR#: This is an I/O Write Strobe generated by the Host. When Ultra DMA mode is not active, this signal is used to clock I/O data into the device. (This pin supports two functions) IOWR# H9 I I2Z

STOP: When Ultra DMA mode protocol is active, the assertion of this signal causes the termination of the Ultra DMA burst



GLS85LP0512P / 1002P / 1004P / 1008P


Table 3-1: Pin Assignments (2 of 2) Pin No.

Symbol 91-Ball

Pin

Type I/O Type Name and Functions

IORDY: When in PIO mode, the device is not ready to respond to a data transfer request. This signal is negated to extend the Host transfer cycle from the assertion of IORD# or IOWR#. However, it is never negated by this controller. (This pin supports three functions)

DDMARDY#: When Ultra DMA mode DMA Write is active, this signal is asserted by the device to indicate that the device is ready to receive Ultra DMA data-out bursts. The device may negate DDMARDY# to pause an Ultra DMA transfer.

IORDY J4 O O2

DSTROBE: When Ultra DMA mode DMA Read is active, this signal is the data-in strobe generated by the device. Both the rising and falling edges of DSTROBE cause data to be latched by the Host. The device may stop generating DSTROBE edges to pause an Ultra DMA data-in burst.

IOCS16# J8 O O3 This output signal is asserted low when the device is indicating a Word data transfer cycle.

INTRQ J2 O O2 This signal is the active high Interrupt Request to the Host.

PDIAG# K9 I/O I1U/O2 The Pass Diagnostic signal in the Master/Slave handshake protocol.

DASP# D9 I/O I1U/O4 The Drive Active/Slave Present signal in the Master/Slave handshake protocol.

RESET# E4 I I2U This input pin is the active low hardware reset from the Host.

Serial Communication Interface (SCI)

SCIDOUT D8 O O2 SCI data output. No external pull-up or pull-down resistor should connect to this signal.

SCIDIN D7 I I1U SCI data input

SCICLK E7 I I1D SCI clock

Miscellaneous

WP#/PD# F6 I I2U

The WP#/PD# pin can be used for either the Write Protect mode or Power-down mode, but only one mode is active at any time. The Write Protect or Power-down modes can be selected through the host command. The Write Protect mode is the factory default setting.

VSS G4, G6, G7, K4,

K6, K7, J9 PWR Ground

VDD E2, E9, K5, L5,

M2, M9 PWR VDD (3.3V)

DNU

A1, A2, A9,

A10, B1, B9,

B10, D2, D3,

D4, D5, D6,

E5, E6, F5,

G5, J7, L4, L6,

L7, M3, M4,

M5, M6, M7,

M8, N2, N3,

N4, N5, N6,

N7, N8, N9,

R1, R2, R9,

R10, T1, T2,

T9, T10

Do not use. All these pins should not be connected.



GLS85LP0512P / 1002P / 1004P / 1008P


4.0 KEY PARAMETERS

Table 4-1 shows the PATA NANDrive default capacity. At production time, the manufacturer can change the default settings in the drive ID table. Please contact Greenliant for details.

Table 4-1: Default PATA NANDrive Settings

Capacity Total Bytes Cylinders Heads Sectors Max LBA (Logical Block Addressing)

512 MByte 456,744,960 885 16 63 892,080

2 GByte 2,000,388,096 3,876 16 63 3,907,008

4 GByte 4,068,384,768 7,883 16 63 7,946,064

8 GByte 8,136,769,536 15,766 16 63 15,892,128

Table 4-2: Sustained Performance

Product Write Performance Read Performance

GLS85LP0512P-S-I-LBTE Up to 6 MByte/sec Up to 25 MByte/sec

GLS85LP1002P-S-I-FTE Up to 11 MByte/sec Up to 28 MByte/sec



Table 4-3: Supported ATA Modes

Products PIO MWDMA Ultra DMA

GLS85LP0512P-S-I-LBTE Up to Mode-6 1)

Up to Mode-4 2)

Up to Mode-6

GLS85LP1002P-S-I-FTE Up to Mode-6 1)

Up to Mode-4 2)

Up to Mode-6


Up to Mode-4 2)

Up to Mode-6


Up to Mode-4 2)

Up to Mode-6



GLS85LP0512P / 1002P / 1004P / 1008P


5.0 CONFIGURABLE WRITE PROTECT / POWER-DOWN MODES

The WP#/PD# pin can be used for either Write Protect mode or Power-down mode, but only one mode is active at any time. Either mode can be selected through the host command, Set-WP#/PD#-Mode.

Once the mode is set with this command, the device will stay in the configured mode until the next time this command is issued. Power-off or reset will not change the configured mode.

5.1 Write Protect Mode

When the device is configured in the Write Protect mode, the WP#/PD# pin offers extended data protection. This feature can be either selected through a jumper or host logic to protect the stored data from inadvertent system writes or erases, and viruses. The Write Protect feature protects the full address space of the data stored on the flash media.

In the Write Protect mode, assert the WP#/PD# pin prior to issuing all destructive commands: Write-DMA, Write-Multiple, Write-Sector(s) or Write-Verify. This will force the PATA NANDrive to reject any destructive commands from the ATA interface. All destructive commands will return 51H in the Status register and 04H in the Error register signifying an invalid command. All non-destructive commands will be executed normally.

5.2 Power-down Mode

When the device is configured in the Power-down mode, if the WP#/PD# pin is asserted during a command, the PATA NANDrive stops the ongoing command and immediately enters Power-down mode. Afterwards, the device will not accept any other commands. Both software reset and hardware reset will bring the device to normal operation with the WP#/PD# pin de-asserted.

5.3 Security Erase

The PATA NANDrive supports purge and security

erase features 3)

3) For implementation on the security erase feature, please refer to the “NANDrive™ & 55LD040M Controller Security Erase Feature / Purge Command” application note. A signed NDA is required to receive this application note.

6.0 POWER-ON INITIALIZATION

The PATA NANDrive is self-initialized during the first power-up. As soon as the power is applied to the PATA NANDrive it reports busy for typically up to seven seconds while performing search for bad blocks search and low-level format. This initialization is a one-time event.

During the first self-initialization, the PATA NANDrive firmware scans all connected flash media devices and reads their device ID. If the device ID matches the listed flash media devices, the PATA NANDrive performs drive recognition based on the algorithm provided by the flash media suppliers, including setting up the bad block table, executing all the necessary handshaking routines for flash media support and performing the low-level format.

If the drive initialization fails and a visual inspection is unable to determine the problem, Greenliant provides a comprehensive interface for manufacturing flow debug. This interface not only allows debug of the failure and manual reset of the initialization process, but also allows customization of user definable options.

7.0 ATA/IDE HOST INTERFACE

The ATA/IDE host interface can be used for PATA NANDrive manufacturing support. Greenliant provides an example of a DOS- and Windows™-based solution (an executable routine) for manufacturing debug and rework.

7.1 Serial Communication Interface (SCI)

For additional manufacturing flexibility, the SCI bus can be used for manufacturing error reporting and for accessing the status of the controller’s internal activities. The SCI consists of three active signals: SCIDOUT, SCIDIN and SCICLK. Always provide access to the SCI port in the PCB design to aid in design validation.

8.0 LIFETIME EXPECTANCY

The PATA NANDrive with advanced NAND management technology significantly extends the life of a product with its extensive ECC and advanced wear-leveling algorithms.

For applications where data security is essential, the PATA NANDrive with advanced NAND management technology offers two additional protection features - protection zones and password protections.

Protection Zones - Up to four independent protection zones can be enabled as either Read-only or Hidden (Read/Write protected). If the zones are not enabled, the data is unprotected (default configuration).

Password Protection - Requires a customer-unique password to access information within the protected zones.



GLS85LP0512P / 1002P / 1004P / 1008P


9.0 POWER-ON AND BROWN-OUT RESET CHARACTERISTICS

Figure 9-1 and Table 9-1 detail the Power-on and Brown-out reset characteristics of the PATA NANDrive.

Figure 9-1: Power-on and Brown-out Reset Timing

Table 9-1: Power-on and Brown-out Reset Timing

Item Symbol Min Max Units

VDD Rise Time TR 250 ms

VDD Fall Time TF 250 ms

10.0 SOFTWARE INTERFACE

10.1 I/O Transfer Function

The default operation for the PATA NANDrive is 16-bit. However, if the Host issues a SET-FEATURE command to enable 8-bit mode, the PATA NANDrive permits 8-bit data access.

Table 10-1: I/O Function Function Code CS3FX# CS1FX# A0-A2 IORD# IOWR# D15-D8 D7-D0

Invalid Mode VIL VIL X X X Undefined Undefined

Standby Mode VIH VIH X X X High Z High Z

Task File Write VIH VIL 1-7H VIH VIL X Data In

Task File Read VIH VIL 1-7H VIL VIH High Z Data Out

Data Register Write VIH VIL 0 VIH VIL In1 In

Data Register Read VIH VIL 0 VIL VIH Out1 Out

Control Register Write VIL VIH 6H VIH VIL X Control In

Alt Status Read VIL VIH 6H VIL VIH High Z Status Out

4) If 8-bit data transfer mode is enabled. In 8-bit data transfer mode, High Byte is undefined for Data Out. For Data In, X can be VIH or VIL, but no other value.



GLS85LP0512P / 1002P / 1004P / 1008P


10.2 Command Description

This section defines the software requirements and the format of the commands the Host sends to the PATA NANDrive. Commands are issued to the PATA NANDrive by loading the required registers in the command block with the supplied parameters, and then writing the command code to the Command register. With the exception of commands listed in Sections “Idle – 97h or E3h”, “Set-Sleep-Mode – 99h or E6h”, “Set-WP#/PD#-Mode - 8Bh”, a SMART command

13) and the security erase relating commands

3), the PATA NANDrive complies with ATA-7

Specifications.

Table 10-2: NANDrive Command Set Command Code FR

5),6) SC

6), 7) SN

6), 8) CY

6), 9) DH

10), 11) LBA

6), 12)

Check-Power-Mode E5h or 98h - - - - D -

Execute-Drive-Diagnostic 90h - - - - D -

Flush-Cache E7h - - - - D -

Flush-Cache-EXT EAh - - - - D -

Identify-Drive ECh - - - - D -

Idle E3h or 97h - Y - - D -

Idle-Immediate E1h or 95h - - - - D -

Initialize-Drive-Parameters 91h - Y - - Y -

NOP 00h - - - - D -

Read-Buffer E4h - - - - D -

Read-DMA C8h or C9h - Y Y Y Y Y

Read-DMA-EXT 25h - Y Y Y Y Y

Read-Multiple C4h - Y Y Y Y Y

Read-Multiple-EXT 29h - Y Y Y Y Y

Read-Sector(s) 20h or 21h - Y Y Y Y Y

Read-Sector(s)-EXT 24h - Y Y Y Y Y

Read-Verify-Sector(s) 40h or 41h - Y Y Y Y Y

Read-Verify-Sector(s)-EXT 42h - Y Y Y Y Y

Recalibrate 1Xh - - - - D -

Security-Disable-Password F6h - - - - D -

Security-Erase-Prepare F3h - - - - D -

Security-Erase-Unit F4h - - - - D -

Security-Freeze-Lock F5h - - - - D -

Security-Set-Password F1h - - - - D -

Security-Unlock F2h - - - - D -

Seek 7Xh - - Y Y Y Y

Set-Features EFh Y - - - D -

SMART B0h Y Y Y Y D -

Set-Multiple-Mode C6h - Y - - D -

Set-Sleep-Mode E6h or 99h - - - - D -

Set-WP#/PD#-Mode 8Bh Y - - - D -

Standby E2h or 96h - - - - D -

Standby-Immediate E0h or 94h - - - - D -

Write-Buffer E8h - - - - D -

Write-DMA CAh or CBh - Y Y Y Y Y

Write-DMA-EXT 35h - Y Y Y Y Y

Write-Multiple C5h - Y Y Y Y Y

Write-Multiple-EXT 39h - Y Y Y Y Y

Write-Sector(s) 30h or 31h - Y Y Y Y Y

Write-Sector(s)-EXT 34h - Y Y Y Y Y

Write-Verify 3Ch - Y Y Y Y Y 5) FR - Features register 6) Y - The register contains a valid parameter for this command 7) SC - Sector Count register 8) SN - Sector Number register 9) CY - Cylinder registers 10) For the Drive/Head register: Y means both the Drive and Head parameters are used; D means only the Drive parameter is valid and

not the Head parameter 11) DH - Drive/Head register 12) LBA - Logical Block Address mode supported (see command descriptions for use) 13) Please ask your Greenliant contact about SMART command support



GLS85LP0512P / 1002P / 1004P / 1008P


10.2.1 Identify-Drive – ECh

Bit -> 7 6 5 4 3 2 1 0

Command (7) ECh

C/D/H (6) X Drive X

Cyl High (5) X

Cyl Low (4) X

Sec Num (3) X

Sec Cnt (2) X

Feature (1) X

The Identify-Drive command enables the Host to receive parameter information from the PATA NANDrive. This command has the same protocol as the Read-Sector(s) command. The parameter Words in the buffer have the arrangement and meanings defined in Table 10-3. All reserved bits or Words are zero. The following table gives the definition for each field in the Identify-Drive information.

Table 10-3: Identify-Drive Information (1 of 2) Word

Address Total Bytes

Default Value

Data Field Type Information

0 2 044Ah General configuration bit

1 2 bbbbh 15)

Default number of cylinders

2 2 0000h Reserved

3 2 bbbbh 15)

Default number of heads

4 2 0000h Reserved

5 2 0000h Reserved

6 2 bbbbh 15)

Default number of sectors per track

7-8 4 xxxxh 14)

Reserved

9 2 xxxxh 14)

Vendor Unique

10-14 10 eeeeH 17)

User-programmable serial number in ASCII

15-19 10 ddddH 18)

Greenliant preset, unique ID in ASCII

20 2 0000H Retired

21 2 xxxxh 14)

Vendor Unique

22 2 xxxxh 14)

Vendor Unique

23-26 8 aaaah 19)

Firmware revision in ASCII. Big Endian Byte Order in Word

27-46 40 cccch 20)

User Definable Model number

47 2 8001h Maximum number of sectors on Read/Write-Multiple command

48 2 0000h Reserved

49 2 0B00h Capabilities

50 2 0000h Reserved

51 2 0200h PIO Data Transfer Cycle Timing Mode

52 2 0000h Reserved

53 2 0007h Translation parameters are valid

54 2 nnnnh 16)

Current numbers of cylinders

55 2 nnnnh 16)

Current numbers of heads

56 2 nnnnh 16)

Current sectors per track

57-58 4 nnnnh 16)

Current capacity in sectors (LBAs) (Word 57 = LSW, Word 58 = MSW)

59 2 010xh Multiple sector setting

60-61 4 nnnnh 16)

Total number of sectors addressable in LBA mode

62 2 0000h Reserved

63 2 xx07h DMA data transfer is supported in NAND Controller

64 2 0003h Advanced PIO Transfer mode supported

65 2 0078h 120 ns cycle time support for Multi-Word DMA Mode-2

66 2 0078h 120 ns cycle time support for Multi-Word DMA Mode-2

67 2 0078h PIO Mode-4 supported

68 2 0078h PIO Mode-4 supported



GLS85LP0512P / 1002P / 1004P / 1008P


Table 10-3: Identify-Drive Information (2 of 2) Word

Address Total Bytes

Default Value

Data Field Type Information

69-79 22 0000h Reserved

80 2 00FEh ATA major version number

81 2 0021h ATA minor version number

82 2 706Bh Features/command sets supported

83 2 7408h Features/command sets supported

84 2 4000h Features/command sets supported

85-87 6 xxxxh 14)

Features/command sets enabled

88 2 xx7Fh UDMA modes

89 2 xxxxh 14)

Time required for security erase unit completion

90 2 xxxxh 14)

Time required for enhanced security erase unit completion

91 2 0000h Advanced Power Management Level. This always returns 0000h.

92 2 0000h Reserved

93 2 xxxxh 14)

Hardware reset result

94-99 12 0000h Reserved

100-103 8 nnnnh 16)

Maximum user LBA for 48-bit Address feature set

104-127 48 0000h Reserved

128 2 xxxxh 14)

Security Status

129-159 62 0000h Vendor unique bytes

160-216 114 0000h Reserved

217 2 0001h Nominal media rotation rate of the device

218-404 74 0000h Reserved

255 2 BBA5h Integrity Word [15-8 Checksum, 7-0 Signature (A5h)] 14) xxxx - This field is subject to change by the Host or the device. 15) bbbb - default value set by the controller. The selections could be user programmable. 16) n - calculated data based on product configuration 17) eeee - the default value is ‘0000000000’ 18) dddd - unique number of each device 19) aaaa - any unique Greenliant firmware revision 20) cccc – the default value is “xxxMB NANDrive” or “xxxGB NANDrive” where xxx is the flash drive capacity.

The user has an option to change the model number during manufacturing.

Word 0: General Configuration This field informs the Host that this is a non-magnetic, hard sectored, removable storage device with a transfer rate greater than 10 MByte/sec and is not MFM encoded.

Word 1: Default Number of Cylinders This field contains the number of translated cylinders in the default translation mode. This value will be the same as the number of cylinders.

Word 3: Default Number of Heads This field contains the number of translated heads in the default translation mode.

Word 6: Default Number of Sectors per Track This field contains the number of sectors per track in the default translation mode.

Word 10-19: Serial Number The contents of this field are right justified and padded with spaces (20h). The right-most ten bytes are Greenliant preset, unique ID. The left-most ten bytes are a user-programmable value with a default value of 0000000000.

Word 23-26: Firmware Revision This field contains the revision of the firmware for this product.

Word 27-46: Model Number This field is reserved for the model number for this product.

Word 47: Read-/Write-Multiple Sector Count This field contains the maximum number of sectors that can be read or written per interrupt using the Read-Multiple or Write-Multiple commands. Only a value of ‘1’ is supported.



GLS85LP0512P / 1002P / 1004P / 1008P


Word 49: Capabilities Bit Function 13 Standby Timer 0: Forces sleep mode when Host is inactive 11 IORDY Support 1: PATA NANDrive supports PIO Mode-4 9 LBA support 1: PATA NANDrive supports LBA mode addressing 8 DMA Support 1: DMA mode is supported

Word 51: PIO Data Transfer Cycle Timing Mode This field contains the mode for PIO data transfer. The PATA NANDrive supports PIO Mode-4.

Word 53: Translation Parameters Valid Bit Function 0 1: Words 54-58 are valid and reflect the current number of cylinders, heads and sectors. 1 1: Words 64-70 are valid to support PIO Mode-3 and -4. 2 1: Word 88 is valid to support Ultra DMA data transfer.

Word 54-56: Current Number of Cylinders, Heads, Sectors/Track These fields contain the current number of user addressable Cylinders, Heads and Sectors/Track in the current translation mode.

Word 57-58: Current Capacity This field contains the product of the current cylinders times heads times sectors.

Word 59: Multiple Sector Setting This field contains a validity flag in the Odd Byte and the current number of sectors that can be transferred per interrupt for Read/Write Multiple in the Even Byte. The Odd Byte is always 01h which indicates that the Even Byte is always valid.

The Even Byte value depends on the value set by the Set Multiple command. The Even Byte of this Word by default contains a 00h which indicates that Read/Write Multiple commands are not valid.

Word 60-61: Total Sectors Addressable in LBA Mode This field contains the number of sectors addressable for the PATA NANDrive in LBA mode only.

Word 63: Multi-Word DMA Transfer Mode This field identifies the Multi-Word DMA transfer modes supported by the PATA NANDrive and indicates the mode that is currently selected. Only one DMA mode can be selected at any given time.

Bit Function 15-11 Reserved 10 Multi-Word DMA mode 2 selected 1: Multi-Word DMA mode 2 is selected and bits 8 and 9 are cleared to 0 0: Multi-Word DMA mode 2 is not selected 9 Multi-Word DMA mode 1 selected 1: Multi-Word DMA mode 1 is selected and 8 and 10 should be cleared to 0 0: Multi-Word DMA mode 1 is not selected 8 Multi-Word DMA mode 0 selected 1: Multi-Word DMA mode 0 is selected and bits 9 and 10 are cleared to 0 0: Multi-Word DMA mode 0 is not selected 7-3 Reserved 2 Multi-Word DMA mode 2 supported 1: Multi-Word DMA mode 2 and below are supported and Bits 0 and 1 are set to 1 1 Multi-Word DMA mode 1 supported 1: Multi-Word DMA mode 1 and below are supported 0 Multi-Word DMA mode 0 supported 1: Multi-Word DMA mode 0 is supported



GLS85LP0512P / 1002P / 1004P / 1008P


Word 64: Advanced PIO Data Transfer Mode 4)

Bits [7:0] are defined as the PIO data and register transfer supported field. If this field is supported, bit 1 of Word 53 shall be set to one. This field is bit significant. Any number of bits may be set to one in this field by the device to indicate the PIO modes the device is capable of supporting. Of these bits, bits [7:2] are reserved for future PIO modes.

Bit Function 0 1: PATA NANDrive supports PIO Mode-3 1 1: PATA NANDrive supports PIO Mode-4

Word 65: Minimum Multi-Word DMA Transfer Cycle Time Per Word 21)

This field defines the minimum Multi-Word DMA transfer cycle time per Word. This field defines, in nanoseconds, the minimum cycle time that the PATA NANDrive supports when performing Multi-Word DMA transfers on a per Word basis. The PATA NANDrive supports up to Multi-Word DMA Mode-2, so this field is set to 120ns.

21) The PATA NANDrive is capable of supporting Multi-Word DMA Mode-4 cycle time of 80ns (0050H). Contact Greenliant sales/ FAE for more details.

Word 66: Device Recommended Multi-Word DMA Cycle Time 21)

This field defines the PATA NANDrive recommended Multi-Word DMA transfer cycle time. This field defines, in nanoseconds, the minimum cycle time per Word during a single sector host transfer while performing a multiple sector READ DMA or WRITE DMA command for any location on the media under nominal conditions. If a Host runs at a faster cycle rate by operating at a cycle time of less than this value, the PATA NANDrive may negate DMARQ for flow control. The rate at which DMARQ is negated could result in Advance Information reduced throughput despite the faster cycle rate. Transfer at this rate does not ensure that flow control will not be used, but implies that higher performance may result. The PATA NANDrive supports Multi-Word DMA Mode-2, so this field is set to 120ns.

Word 67: Minimum PIO Transfer Cycle Time Without Flow Control 22)

This field defines, in nanoseconds, the minimum cycle time that, if used by the Host, the device guarantees data integrity during the transfer without utilization of IORDY flow control. If this field is supported, Bit 1 of Word 53 shall be set to one. The PATA NANDrive supports PIO Mode-4, so this field is set to 120ns.

22) The PATA NANDrive is capable of supporting PIO Mode-6 cycle time of 80ns (0050H). Contact Greenliant sales/ FAE for more details.

Word 68: Minimum PIO Transfer Cycle Time With IORDY 22)

This field defines, in nanoseconds, the minimum cycle time that the device supports while performing data transfers while utilizing IORDY flow control. If this field is supported, Bit 1 of Word 53 shall be set to one. The PATA NANDrive supports PIO Mode-4, so this field is set to 120ns.

Word 80: Major Version Number If not 0000H or FFFFh, the device claims compliance with the major version(s) as indicated by bits [6:1] being set to one. Since ATA standards maintain downward compatibility, a device may set more than one bit. The PATA NANDrive supports ATA-1 to ATA-7.

Word 81: Minor Version Number If an implementer claims that the revision of the standard they used to guide their implementation does not need to be reported or if the implementation was based upon a standard prior to the ATA-3 standard, Word 81 should be 0000h or FFFFh.

A value of 0021h reported in Word 81 indicates ATA-7 T13/1532D volume 1, revision 4b guided the implementation.

Words 82-84: Features/command sets supported Words 82, 83 and 84 indicate the features and command sets supported. A value of 706Bh is reported.



GLS85LP0512P / 1002P / 1004P / 1008P


Word 82 Bit Function 15 0: Obsolete 14 1: NOP command is supported 13 1: Read Buffer command is supported 12 1: Write Buffer command is supported 11 0: Obsolete 10 0: Host Protected Area feature set is not supported 9 0: Device Reset command is not supported 8 0: Service interrupt is not supported 7 0: Release interrupt is not supported 6 1: Look-ahead is supported 5 1: Write cache is supported 4 0: Packet Command feature set is not supported 3 1: Power Management feature set is supported 2 0: Removable Media feature set is not supported 1 1: Security Mode feature set is supported 0 1: SMART feature set is supported

Word 83 The values in this Word should not be depended on by host implementers.

Bit Function 15 0: Provides an indication whether the features/command sets supported Words are valid or not 14 1: Provides an indication whether the features/command sets supported Words are valid or not 13 1: Flush Cache Ext command supported 12 1: Mandatory Flush Cache command supported 11 0: Device Configuration Overlay feature set not supported 10 1: 48-bit Address feature set supported 9 0: Reserved 8 0: Set-Max security extension is not supported 7-5 0: Reserved 4 0: Removable Media Status feature set is not supported 3 1: Advanced Power Management feature set is supported However, it is No Operation (NOP) and Word 91 will always return 0000h 2 0: CFA feature set is not supported 1 0: Read DMA Queued and Write DMA Queued commands are not supported 0 0: Download Microcode command is not supported


Bit Function 15 0: Provides an indication whether the features/command sets supported Words are valid or not 14 1: Provides an indication whether the features/command sets supported Words are valid or not 13-0 0: Reserved

Words 85-87: Features/command sets enabled Words 85, 86, and 87 indicate features/command sets enabled. The Host can enable/disable the features or command set only if they are supported in Words 82-84.



GLS85LP0512P / 1002P / 1004P / 1008P


Word 85 Bit Function 15 0: Obsolete 14 0: NOP command is not enabled 1: NOP command is enabled 13 0: Read Buffer command is not enabled 1: Read Buffer command is enabled 12 0: Write Buffer command is not enabled 1: Write Buffer command is enabled 11 0: Obsolete 10 1: Host Protected Area feature set is enabled 9 0: Device Reset command is not enabled 8 0: Service interrupt is not enabled 7 0: Release interrupt is not enabled 6 0: Look-ahead is not enabled 1: Look-ahead is enabled 5 0: Write cache is not enabled 1: Write cache is enabled 4 0: Packet Command feature set is not enabled 3 0: Power Management feature set is not enabled 1: Power Management feature set is enabled 2 0: Removable Media feature set is not enabled 1 0: Security Mode feature set has not been enabled via the Security Set Password command 1: Security Mode feature set has been enabled via the Security Set Password command 0 0: SMART feature set is not enabled

Word 86 Bit Function 15-14 0: Reserved 13 1: Flush Cache Ext command supported 12 1: Mandatory Flush Cache command supported 11 0: Device Configuration Overlay feature set not supported 10 1: 48-bit Address feature set supported 9 0: Reserved 8 1: Set-Max security extension supported 7-5 0: Reserved 4 0: Removable Media Status feature set is not enabled 3 0: Advanced Power Management feature set is not enabled 2 0: CFA feature set is disabled 1 0: Read DMA Queued and Write DMA Queued commands are not enabled 0 0: Download Microcode command is not enabled


Bit Function 15 0: Provides an indication whether the features/command sets supported Words are valid or not 14 1: Provides an indication whether the features/command sets supported Words are valid or not 13-0 0: Reserved



GLS85LP0512P / 1002P / 1004P / 1008P


Word 88 Bit Function 15 Reserved 14 1: Ultra DMA mode 6 is selected 0: Ultra DMA mode 6 is not selected 13 1: Ultra DMA mode 5 is selected 0: Ultra DMA mode 5 is not selected 12 1: Ultra DMA mode 4 is selected 0: Ultra DMA mode 4 is not selected 11 1: Ultra DMA mode 3 is selected 0: Ultra DMA mode 3 is not selected 10 1: Ultra DMA mode 2 is selected 0: Ultra DMA mode 2 is not selected 9 1: Ultra DMA mode 1 is selected 0: Ultra DMA mode 1 is not selected 8 1: Ultra DMA mode 0 is selected 0: Ultra DMA mode 0 is not selected 7 Reserved 6 1: Ultra DMA mode 6 and below supported 5 1: Ultra DMA mode 5 and below supported 4 1: Ultra DMA mode 4 and below are supported 3 1: Ultra DMA mode 3 and below are supported 2 1: Ultra DMA mode 2 and below are supported 1 1: Ultra DMA mode 1 and below are supported 0 1: Ultra DMA mode 0 is supported

Word 89: Time required for Security erase unit completion Word 89 specifies the time required for the Security Erase Unit command to complete.

Value Time

0 Value not specified

1-254 (Value * 2) minutes

255 >508 minutes

Word 90: Time required for Enhanced security erase unit completion Word 90 specifies the time required for the Enhanced Security Erase Unit command to complete.

Value Time

0 Value not specified

1-254 (Value * 2) minutes

255 >508 minutes



GLS85LP0512P / 1002P / 1004P / 1008P


Word 93: Hardware reset result The contents of bits [12:0] of this Word will change only during the execution of the hardware reset.

Bit Function 15 Shall be cleared to zero 14 Shall be set to one 13 1: Device detected CBLID - above VIH 0: Device detected CBLIP - below VIL 12-8 Device 1 hardware reset result; Device 0 shall clear these bits to zero Device 1 shall set these bits as follows: 12 Reserved 11 0: Device 1 did not assert PDIAG- 1: Device 1 asserted PDIAG- 10-9 These bits indicate how Device 1 determined the device number 00: Reserved 01: A jumper was used 10: The CSEL signal was used 11: Some other method was used or the method is unknown 8 Shall be set to one 7-0 Device 0 hardware reset result Device 1 shall clear these bits to zero. Device 0 shall set these bits as follows: 7 Reserved 6 0: Device 0 does not respond when Device 1 is selected 1: Device 0 responds when Device 1 is selected 5 0: Device 0 did not detect the assertion of DASP- 1: Device 0 detected the assertion of DASP- 4 0: Device 0 did not detect the assertion of PDIAG- 1: Device 0 detected the assertion of PDIAG- 3 0: Device 0 failed diagnostics 1: Device 0 passed diagnostics 2-1 These bits indicate how Device 0 determined the device number: 00: Reserved 01: A jumper was used 10: The CSEL signal was used 11: Some other method was used or the method is unknown 0 Shall be set to one

Word 128: Security Status Bit Function 8 Security Level 1: Security mode is enabled and the security level is maximum 0: and security mode is enabled, indicates that the security level is high 5 Enhanced security erase unit feature supported 1: Enhanced security erase unit feature set is supported 4 Expire 1: Security count has expired and Security Unlock and Security Erase Unit are command aborted

until a Power-on reset or hard reset 3 Freeze 1: Security is frozen 2 Lock 1: Security is locked 1 Enable/Disable 1: Security is enabled 0: Security is disabled 0 Capability 1: PATA NANDrive supports security mode feature set 0: PATA NANDrive does not support security mode feature set



GLS85LP0512P / 1002P / 1004P / 1008P


Word 217: Nominal Media Rotation Rate Word 217 indicates the nominal media rotation rate of the device. For the PATA NANDrive, the value is always 0001h for this field to indicate non-rotating media.

Word 255: Integrity Word Word 255 is optional. When bits [7:0] of this Word contain the signature A5h, bits [15:8] contain the data-structure checksum. The data-structure checksum value is the two’s complement of the sum of all bytes in Words [254:0] and the byte consisting of bits [7:0] in Word 255. Add each byte with unsigned arithmetic, and ignore overflow. When the checksum is correct, the sum of all 512 bytes is zero.



GLS85LP0512P / 1002P / 1004P / 1008P


10.2.2 Set-Features – EFh

Bit -> 7 6 5 4 3 2 1 0

Command (7) EFh

C/D/H (6) X Drive X

Cyl High (5) X

Cyl Low (4) X

Sec Num (3) X

Sec Cnt (2) Config

Feature (1) Feature

This command is used by the Host to establish or select certain features. Table 10-4 defines all features that are supported.

Table 10-4: Features Supported Feature Operation

01h Enable 8-bit data transfers.

02h Enable Write cache

03h Set transfer mode based on value in Sector Count register. Table 10-5 defines the values.

05h Enable Advanced Power Management

09h Enable Extended Power Operations

55h Disable Read Look Ahead.

66h Disable Power-on Reset (POR) establishment of defaults at software reset.

69h NOP - Accepted for backward compatibility.

81h Disable 8-bit data transfer.

82h Disable Write Cache

85h Disable Advanced Power Management

89h Disable Extended Power operations

96h NOP - Accepted for backward compatibility.

97h Accepted for backward compatibility. Use of this Feature is not recommended.

AAh Enable Read-Look-Ahead

CCh Enable Power-on Reset (POR) establishment of defaults at software reset.

Features 01h and 81h are used to enable and clear 8-bit data transfer mode. If the 01h feature command is issued all data transfers will occur on the low order D[7:0] data bus and the IOCS16# signal will not be asserted for data register accesses.

Features 02h and 82h allow the Host to enable or disable write cache in the PATA NANDrive that implements write cache. When the subcommand Disable-Write-Cache is issued, the PATA NANDrive should initiate the sequence to flush cache to non-volatile memory before command completion.

Feature 03h allows the Host to select the transfer mode by specifying a value in the Sector Count register. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value. One PIO mode is selected at all times. The Host may change the selected modes by the Set-Features command.

Feature 55h is the default feature for the PATA NANDrive. Therefore, the Host does not have to issue Set-Features command with this feature unless it is necessary for compatibility reasons.

Features 66h and CCh can be used to enable and disable whether the Power-on Reset (POR) Defaults will be set when a software reset occurs.

Table 10-5: Transfer Mode Values

Mode 23)

Bits [7:3] Bits [2:0]

PIO default mode 00000b 000b

PIO default mode, disable IORDY 00000b 001b

PIO flow control transfer mode 00001b mode1

Multi-Word DMA mode 00100b mode1

Ultra-DMA mode 01000b mode1

Reserved Other N/A

23) Mode = transfer mode number, all other values are not valid



GLS85LP0512P / 1002P / 1004P / 1008P


10.2.3 Idle – 97h or E3h

Bit -> 7 6 5 4 3 2 1 0

Command (7) 97h or E3h

C/D/H (6) X Drive X

Cyl High (5) X

Cyl Low (4) X

Sec Num (3) X

Sec Cnt (2) Timer Count (5 msec increments)

Feature (1) X

This command causes the PATA NANDrive to set BSY, enter the Idle mode, clear BSY and generate an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5 milliseconds and the automatic Power-down mode is enabled. If the sector count is zero, the automatic Power-down mode is also enabled, the timer count is set to 3, with each count being 5 ms

24).

24) The time base equals to 5 ms is different from the ATA specification.

10.2.4 Set-Sleep-Mode – 99h or E6h

Bit -> 7 6 5 4 3 2 1 0

Command (7) 99h or E6h

C/D/H (6) X Drive X

Cyl High (5) X

Cyl Low (4) X

Sec Num (3) X

Sec Cnt (2) X

Feature (1) X

This command causes the PATA NANDrive to set BSY, enter the Sleep mode, clear BSY and generate an interrupt. Recovery from sleep mode is accomplished by simply issuing another command (a reset is permitted, but not required). Sleep mode is also entered when internal timers expire so the Host does not need to issue this command except when it wishes to enter Sleep mode immediately. The default value for the timer is 15 milliseconds.

10.2.5 Set-WP#/PD#-Mode - 8Bh

Bit -> 7 6 5 4 3 2 1 0

Command (7) 8Bh

C/D/H (6) X Drive X

Cyl High (5) 6Eh Cyl Low (4) 44h

Sec Num (3) 72h Sec Cnt (2) 50h Feature (1) 55h or AAh

This command configures the WP#/PD# pin for either the Write Protect mode or the Power-down mode. When the Host sends this command to the device with the value AAH in the feature register, the WP#/PD# pin is configured for the Write Protect mode. The Write Protect mode is the factory default setting. When the Host sends this command to the device with the value 55h in the feature register, WP#/PD# is configured for the Power-down mode.

All values in the C/D/H register, the Cylinder Low register, the Cylinder High register, the Sector Number register, the Sector Count register, and the Feature register need to match the values shown above, otherwise, the command will be treated as an invalid command.

Once the mode is set with this command, the device will stay in the configured mode until the next time this command is issued. Power-off or reset will not change the configured mode.



GLS85LP0512P / 1002P / 1004P / 1008P


10.2.6 Error Posting

The following table summarizes the valid status and error values for the PATA NANDrive command set.

Table 10-6: Error and Status Register 25) 26)

Error Register Status Register Command ICRC

/BBK UNC IDNF ABRT AMNF RDY DWF DSC CORR ERR

Check-Power-Mode V V V V V

Execute-Drive-Diagnostic V V V

Flush-Cache V V V V V

Flush-Cache-EXT V V V V V

Identify-Drive V V V V V

Idle V V V V V

Idle-Immediate V V V V V

Initialize-Drive-Parameters V V V

NOP V V V V

Read-Buffer V V V V V

Read-DMA V V V V V V V V V V

Read-DMA-EXT V V V V V V V V V V

Read-Multiple V V V V V V V V V V

Read-Multiple-EXT V V V V V V V V V V

Read-Sector(s) V V V V V V V V V V

Read-Sector(s)-EXT V V V V V V V V V V

Read-Verify-Sector(s) V V V V V V V V V V

Read-Verify-Sector(s)-EXT V V V V V V V V V V

Recalibrate V V V V V

Security-Disable-Password V V V V V

Security-Erase-Prepare V V V V V

Security-Erase-Unit V V V V V

Security-Freeze-Lock V V V V V

Security-Set-Password V V V V V

Security-Unlock V V V V V

Seek V V V V V V

Set-Features V V V V V

Set-Multiple-Mode V V V V V

Set-Sleep-Mode V V V V V

Set-WP#/PD#-Mode V V V V

SMART V V V V

Standby V V V V V

Standby-Immediate V V V V V

Write-Buffer V V V V V

Write-DMA V V V V V V V V

Write-DMA-EXT V V V V V V V V

Write-Multiple V V V V V V V V

Write-Multiple-EXT V V V V V V V V

Write-Sector(s) V V V V V V V V

Write-Sector(s)-EXT V V V V V V V V

Write-Verify V V V V V V V V

Invalid-Command-Code V V V V V 25) The Host is required to reissue any media access command (such as Read-Sector and Write Sector) that ends with an error

condition. 26) V = valid on this command.



GLS85LP0512P / 1002P / 1004P / 1008P


11.0 ELECTRICAL SPECIFICATIONS

11.1 Absolute Maximum Ratings

Absolute Maximum Stress Ratings - Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.

Storage Temperature............................................................................................................................-55°C to +125°C D.C. Voltage on Pin types

27) I1, I2, O2, O3, and O4 to Ground Potential ..................................... -0.5V to VDD +0.5V

Transient Voltage (<20 ns) on Pin types 27)

I1, I2, O2, O3, and O4 to Ground Potential ............... -2.0V to VDD +2.0V Package Power Dissipation Capability (TA = 25°C)...............................................................................................1.0W Surface Mount Solder Reflow Temperature

28)............................................................................ 260°C for 10 seconds

Output Short Circuit Current 29)

..............................................................................................................................60mA

27) Refer to Table 3-1 “Pin Assignment” 28) Refer to Figure 12-1 29) Outputs shorted for no more than one second. No more than one output shorted at a time.

11.1.1 Absolute Maximum Power Pin Stress Ratings

Table 11-1: Absolute Maximum Power Pin Stress Ratings

Parameter Symbol Conditions

Input Power VDD -0.3V min to 4.0V max

Voltage on all other pins with respect to VSS -0.5V min to VDD + 0.5V max

11.2 Operating Ratings

Table 11-2: Operating Range VDD (3.3V) Range Ambient Temperature

Min Max

Industrial -40°C to +85°C 3.135V 3.465V

11.3 AC Characteristics

11.3.1 AC Conditions of Test

Table 11-3: AC Conditions of Test

Input Rise/Fall Time Output Load

5 ns CL = 100 pF

Figure 11-1: AC Input/Output Reference Waveforms



GLS85LP0512P / 1002P / 1004P / 1008P


11.4 Recommended System Power-on Timing

Table 11-4: Recommended System Power-on Timing 30)

Symbol Parameter Typical Maximum Units

TPU-INITIAL Drive Initialization to Ready 7 50 sec

TPU-READY11 Host Power-on/Reset to Ready Operation 500 2,000 ms

TPU-WRITE11 Host Power-on/Reset to Write Operation 500 2,000 ms 30) This parameter is measured only for initial qualification and after a design or process change that could affect.

11.5 Reliability Characteristics 30)

Table 11-5: Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

ILTH Latch Up 100 + IDD mA JEDEC Standard 78

11.6 Capacitance 30)

Table 11-6: Capacitance (Ta = 25°C, f=1 MHz, other pins open)

Parameter Description Test Condition Maximum

CI/O I/O Pin Capacitance VI/O = 0V 15 pF

CIN Input Capacitance VIN = 0V 9 pF

11.7 Purge Erase Time

Table 11-7: Purge Erase Time

Product Min. [sec] Typ. [sec] Max. [sec]

GLS85LP0512P-S-I-LBTE 110 120 150

GLS85LP1002P-S-I-FTE 210 220 250

GLS85LP1004P-S-I-FTE 210 220 250

GLS85LP1008P-S-I-FTE 260 270 300



GLS85LP0512P / 1002P / 1004P / 1008P


11.8 DC Characteristics

Table 11-8: DC Characteristics for Host Interface Symbol Type Parameter Min Max Units Conditions

VIH1 2 V VDD=VDD Max

VIL1 I1 Input Voltage

0.8 V VDD=VDD Min

IIL1 I1Z Input Leakage Current -10 10 µA VI =VDD Max or 0V

ID1 I1D Input Pull-Down Current 20 120 µA VDD=VDD Max, VIN = VDD Max

IU1 I1U Input Pull-Up Current -120 -20 µA VDD=VDD Max, VIN = GND

VT+ 1.75 V VDD=VDD Max

VT- I2 Input Voltage Schmitt Trigger

1.09 V VDD=VDD Min

IIL2 I2Z Input Leakage Current -10 10 µA VI = VDD Max or 0V

IU2 I2U Input Pull-Up Current -120 -20 µA VDD=VDD Max, VIN = GND

VOH2 2.4 V IOH2=IOH2 Min

VOL2 Output Voltage

0.4 V IOL2=IOL2 Max

IOH2 -4 mA VDD=VDD Min

IOL2

O2

Output Current 4 mA VDD=VDD Min

VOH3 2.4 V IOH3=IOH3Min

VOL3 Output Voltage

0.4 V IOL3=IOL3 Max


IOL3

O3


VOH4 2.4 V IOH4=IOH4 Min

VOL4 Output Voltage

0.4 V IOL4=IOL4 Max


IOL4

O4


Table 11-9: Power Consumption Symbol Type Device Parameter Min Max Units Conditions

IDD 31), 32)

PWR Power supply current (TA = -40°C to +85°C)

300.0 mA VDD=VDD Max

ISP PWR

GLS85LP1008P Sleep/Standby/Idle current (TA = -40°C to +85°C)

5.20 mA VDD=VDD Max

IDD 31), 32)



ISP PWR


5.10 mA VDD=VDD Max

IDD 31), 32)



ISP PWR


5.05 mA VDD=VDD Max

IDD 31), 32)



ISP PWR


5.05 mA VDD=VDD Max

31) Sequential data transfer from host interface and write data to media. 32) This parameter is measured only for initial qualification and after a design or process change that could affect.



GLS85LP0512P / 1002P / 1004P / 1008P


12.0 APPENDIX

12.1 Differences between the PATA NANDrive and the ATA Specifications

12.1.1 Idle Timer

The Idle timer uses an incremental value of 5 ms, rather than the 5 sec minimum increment value specified in the ATA specifications.

12.1.2 Recovery from Sleep Mode

For the PATA NANDrive devices, recovery from sleep mode is accomplished by simply issuing another command to the device. Hardware or Software reset is not required.

12.2 Reflow Profile

Figure 12-1: Soldering Reflow Profile



GLS85LP0512P / 1002P / 1004P / 1008P


12.3 Product Ordering Information

GLS 85 LP 1 000P - S - I - FTE XX XX X XXXX - X - X - XXXX

Environmental Attribute E

33) = non-Pb

Package Modifier T = 88 ball positions (nearest letter code

to total ball count of 91)

Package Type

Operation Temperature I = Industrial: -40°C to +85°C

NAND Type S = SLC

Version P = Initial Version

Capacity MByte or GByte Designator 1 = GByte / 0 = MByte

Interface P= Parallel ATA/IDE Interface

Voltage L = 3.3V

Product Series 85 = NANDrive

33) Environmental suffix “E” denotes non-Pb solder. Greenliant non-Pb solder devices are “RoHS Compliant.”

Valid Combinations 34)

PATA NANDrive Product GLS85LP1008P-S-I-FTE/ GLS85LP1004P-S-I-FTE GLS85LP1002P-S-I-FTE/ GLS85LP0512P-S-I-LBTE

PATA NANDrive Evaluation Board (xxCN: xx-pin ATA Interface EVB, K: Kit) GLS85LP1008P-S-I-40CN-K, GLS85LP1008P-S-I-44CN-K GLS85LP1004P-S-I-40CN-K, GLS85LP1004P-S-I-44CN-K GLS85LP1002P-S-I-40CN-K, GLS85LP1002P-S-I-44CN-K GLS85LP0512P-S-I-40CN-K, GLS85LP0512P-S-I-44CN-K

34) Valid product combinations are those that are in the mass production or will be in the mass production. Consult your Greenliant sales representative to confirm availability of the valid combinations and to determine availability of new product combinations.



GLS85LP0512P / 1002P / 1004P / 1008P


12.4 Packaging Diagram

12.4.1 FTE Package

Figure 12-2: PATA NANDrive 91-Ball, Ball Grid Array (BGA) Greenliant Package Code: FTE



GLS85LP0512P / 1002P / 1004P / 1008P


12.4.2 LBTE Package

Figure 12-3: PATA NANDrive 91-Ball, Ball Grid Array (BGA) Greenliant Package Code: LBTE



GLS85LP0512P / 1002P / 1004P / 1008P


12.5 Reference Documents

Table 12-1: Reference Document

Title Revision Date

Industrial Grade 512MB 2_4_8GB NANDrive Migration Guide v01 02 01.02 Jan 24, 2011

NANDrive SMART Specification 02.000 Feb 10, 2011

NANDrive Protection Zone Specification 01.000 Feb 10, 2011

NANDrive Security Erase Feature/ Purge Command 01.100 Feb 10, 2011

WindowsPT2 User Guide 02.000 March 1, 2011

12.6 Revision History

Table 12-2: Revision History Number Description Date

01.000 Initial release of datasheet June 15, 2011

© 2011 Greenliant Systems. All rights reserved.

Greenliant, the Greenliant Logo and NANDrive are trademarks of Greenliant Systems. All other trademarks and registered trademarks are the property of their respective owners.

Specifications are subject to change without notice. Memory sizes denote raw storage capacity; actual usable capacity may be less.

Greenliant makes no warranty for the use of its products other than those expressly contained in the Greenliant Terms and Conditions of Sale.

www.greenliant.com

GLS85LP0512P / 1002P / 1004P / 1008P Industrial … GLS85LP0512P / 1002P / 1004P / 1008P Industrial...

Documents

Transcript of GLS85LP0512P / 1002P / 1004P / 1008P Industrial … GLS85LP0512P / 1002P / 1004P / 1008P Industrial...