Getting to 0ppm - Automotive Session
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Transcript of Getting to 0ppm - Automotive Session
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Confidential © ams AG 2016
Test Development : Getting to 0ppm
Automotive Innovative Special Session
Peter Sarson CEng MIET CMgr MCMIFull Service Foundry
16th July 2015
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Introduction
• During the test development process a few simple things can be done to increase the defect coverage of the test program without having to do much to attain it.
• I will demonstrate a few technique over the next 15 mins
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Quality Level at ams AG
Cause Group Ppm (Parts) % of total ppm
FAB 0.035 35%
Test UPS 0.000 0%
Test PHI 0.006 6%
Test Dev. 0.023 22%
Assembly 0.010 10%
Ppm statistics Parts 0.10
Large proportion of RMA’s due to Test Program coverage
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• Simple IDD tests- Powerup, Reset, Standby
• Digital IDDq with Delta calculation- With scan vectors
• Analog IDDq with Delta calculation- Test modes where each block can be
individually powered• Stress
- Stress the device with High Voltage and run scan
- Measure IDD type test post stress and calculate delta
SolutionDefect Based Tests
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Example of Good IDD testsDlog
0.000 mA 5.000 mA 1.285 mA IAVDDH_PWR_UP5.000 mA 15.000 mA 9.733 mA IAVDDL_PWR_UP0.200 uA 190.000 uA 0.253 uA IDVDD_PWR_UP0.000 mA 2.000 mA 0.498 mA IAVDDH_MIN0.000 mA 2.000 mA 0.642 mA IAVDDL_MIN0.200 uA 190.000 uA 0.365 uA IDVDD_MIN2.000 mA 10.000 mA 5.484 mA IAVDDH_NOM_RMS2.000 mA 10.000 mA 9.783 mA IAVDDL_NOM_RMS2.000 mA 10.000 mA 5.356 mA IDVDD_NOM_RMS5.000 mA 12.000 mA 7.688 mA IAVDDH_MAX_RMS2.000 mA 12.000 mA 9.970 mA IAVDDL_MAX_RMS2.000 mA 10.000 mA 5.343 mA IDVDD_MAX_RMS
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Example of Good IDD testsDlog
0.000 mA 5.000 mA 1.285 mA IAVDDH_PWR_UP5.000 mA 15.000 mA 9.733 mA IAVDDL_PWR_UP0.200 uA 190.000 uA 0.253 uA IDVDD_PWR_UP0.000 mA 2.000 mA 0.498 mA IAVDDH_MIN0.000 mA 2.000 mA 0.642 mA IAVDDL_MIN0.200 uA 190.000 uA 0.365 uA IDVDD_MIN2.000 mA 10.000 mA 5.484 mA IAVDDH_NOM_RMS2.000 mA 10.000 mA 9.783 mA IAVDDL_NOM_RMS2.000 mA 10.000 mA 5.356 mA IDVDD_NOM_RMS5.000 mA 12.000 mA 7.688 mA IAVDDH_MAX_RMS2.000 mA 12.000 mA 9.970 mA IAVDDL_MAX_RMS2.000 mA 10.000 mA 5.343 mA IDVDD_MAX_RMS
Initial Powerup setting of the device
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Example of Good IDD testsDlog
0.000 mA 5.000 mA 1.285 mA IAVDDH_PWR_UP5.000 mA 15.000 mA 9.733 mA IAVDDL_PWR_UP0.200 uA 190.000 uA 0.253 uA IDVDD_PWR_UP0.000 mA 2.000 mA 0.498 mA IAVDDH_MIN0.000 mA 2.000 mA 0.642 mA IAVDDL_MIN0.200 uA 190.000 uA 0.365 uA IDVDD_MIN2.000 mA 10.000 mA 5.484 mA IAVDDH_NOM_RMS2.000 mA 10.000 mA 9.783 mA IAVDDL_NOM_RMS2.000 mA 10.000 mA 5.356 mA IDVDD_NOM_RMS5.000 mA 12.000 mA 7.688 mA IAVDDH_MAX_RMS2.000 mA 12.000 mA 9.970 mA IAVDDL_MAX_RMS2.000 mA 10.000 mA 5.343 mA IDVDD_MAX_RMS
Min setting of the device
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Example of Good IDD testsDlog
0.000 mA 5.000 mA 1.285 mA IAVDDH_PWR_UP5.000 mA 15.000 mA 9.733 mA IAVDDL_PWR_UP0.200 uA 190.000 uA 0.253 uA IDVDD_PWR_UP0.000 mA 2.000 mA 0.498 mA IAVDDH_MIN0.000 mA 2.000 mA 0.642 mA IAVDDL_MIN0.200 uA 190.000 uA 0.365 uA IDVDD_MIN2.000 mA 10.000 mA 5.484 mA IAVDDH_NOM_RMS2.000 mA 10.000 mA 9.783 mA IAVDDL_NOM_RMS2.000 mA 10.000 mA 5.356 mA IDVDD_NOM_RMS5.000 mA 12.000 mA 7.688 mA IAVDDH_MAX_RMS2.000 mA 12.000 mA 9.970 mA IAVDDL_MAX_RMS2.000 mA 10.000 mA 5.343 mA IDVDD_MAX_RMS
Nominal setting of the device
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Example of Good IDD testsDlog
0.000 mA 5.000 mA 1.285 mA IAVDDH_PWR_UP5.000 mA 15.000 mA 9.733 mA IAVDDL_PWR_UP0.200 uA 190.000 uA 0.253 uA IDVDD_PWR_UP0.000 mA 2.000 mA 0.498 mA IAVDDH_MIN0.000 mA 2.000 mA 0.642 mA IAVDDL_MIN0.200 uA 190.000 uA 0.365 uA IDVDD_MIN2.000 mA 10.000 mA 5.484 mA IAVDDH_NOM_RMS2.000 mA 10.000 mA 9.783 mA IAVDDL_NOM_RMS2.000 mA 10.000 mA 5.356 mA IDVDD_NOM_RMS5.000 mA 12.000 mA 7.688 mA IAVDDH_MAX_RMS2.000 mA 12.000 mA 9.970 mA IAVDDL_MAX_RMS2.000 mA 10.000 mA 5.343 mA IDVDD_MAX_RMS
Max setting of the device
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IDD test coverage
IDVDD_PWR_UP 40% of failuresIAVDDH_PWR_UP 6% of failuresIAVDDH_MIN 6% of failuresIAVDDL_PWR_UP 5% of failuresIAVDDL_MIN 5% of failuresIAVDDH_NOM 2% of failures
Basic IDD tests account for 64%
But we can improve this further
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Use the device in a way it wasn’t intended
By manipulating the register map of a device you can select combinations of registersthat ordinarily in normal operating mode wouldn’t be used in a certain way.
However by manipulating these registers we can get a marginal device to show itself which wouldn’t be possible otherwise.
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IDDq Analog or ICCq(NXP)
660.000 uA 1820.000 uA 847.740 uA IDDq_0x01660.000 uA 1820.000 uA 862.189 uA IDDq_0x0B-100.000 uA 100.000 uA 14.450 uA IDDq_0x01_del950.000 uA 2270.000 uA 1051.640 uA IDDq_0x0F0.000 uA 500.000 uA 189.450 uA IDDq_0x0B_del1450.000 uA 2870.000 uA 1632.834 uA IDDq_0x11350.000 uA 620.000 uA 581.195 uA IDDq_0x0F_del2000.000 uA 3300.000 uA 2125.725 uA IDDq_0x31 420.000 uA 800.000 uA 492.891 uA IDDq_0x11_del2680.000 uA 4270.000 uA 2923.664 uA IDDq_0x71560.000 uA 1090.000 uA 797.938 uA IDDq_0x31_del2680.000 uA 4270.000 uA 2922.058 uA IDDq_0xF1 -100.000 uA 100.000 uA -1.606 uA IDDq_0x71_del
Register setting of power register linearly
increased
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IDDq Analog or ICCq(NXP)
660.000 uA 1820.000 uA 847.740 uA IDDq_0x01660.000 uA 1820.000 uA 862.189 uA IDDq_0x0B-100.000 uA 100.000 uA 14.450 uA IDDq_0x01_del950.000 uA 2270.000 uA 1051.640 uA IDDq_0x0F0.000 uA 500.000 uA 189.450 uA IDDq_0x0B_del1450.000 uA 2870.000 uA 1632.834 uA IDDq_0x11350.000 uA 620.000 uA 581.195 uA IDDq_0x0F_del2000.000 uA 3300.000 uA 2125.725 uA IDDq_0x31 420.000 uA 800.000 uA 492.891 uA IDDq_0x11_del2680.000 uA 4270.000 uA 2923.664 uA IDDq_0x71560.000 uA 1090.000 uA 797.938 uA IDDq_0x31_del2680.000 uA 4270.000 uA 2922.058 uA IDDq_0xF1 -100.000 uA 100.000 uA -1.606 uA IDDq_0x71_del
Delta from one register setting to the next calculated and
binned based on simulated or characterization data
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Result
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Result
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Result
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Result
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Delta coverage
IDDq_0x0F_del 4.26% of the failures IDDq_0x11_del 4.26% of the failuresIDDq_0x0B_del 3.95% of the failuresIDDq_0x31 3.95% of the failuresIDDq_0xF1 3.34% of the failuresIDDq_0x71 3.34% of the failures
Some of these failures would have been covered by functional testing however some could be missed
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Result
The effect of doing this technique is to introduce a kind of trimming.Instead of having a Gaussian distribution of parts that pass the production test.We remove the tails of the distribution and produce a sort of squared up distributionObviously this is at the cost of a small percentage of yield
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High Voltage Scan StressBurn in simulation
3.500 uA 25.000 uA 12.726 uA VDD_I -0.100 - 0.100 - 0.000 - LVSCAN656 -0.100 - 0.100 - 0.000 - HVSCAN3 3.500 uA 25.000 uA 12.567 uA VDD_I_STRESS -0.650 uA 0.650 uA 0.159 uA VDD_I_delta_STRESS 39.900 ms 50.100 ms 43.692 ms Stress_Time 4.490 V 4.510 V 4.500 V Stress_Voltage 2.800 uA 11.800 uA 4.564 uA ADC_VDD_I 0.900 uA 11.700 uA 8.163 uA VDD_I_delta 0.900 uA 11.700 uA 8.003 uA ADC_delta_post0.485 - 0.525 - 0.505 - delta_STRESS
Measure Typical current consumption
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High Voltage Scan StressBurn in simulation
3.500 uA 25.000 uA 12.726 uA VDD_I -0.100 - 0.100 - 0.000 - LVSCAN656 -0.100 - 0.100 - 0.000 - HVSCAN3 3.500 uA 25.000 uA 12.567 uA VDD_I_STRESS -0.650 uA 0.650 uA 0.159 uA VDD_I_delta_STRESS 39.900 ms 50.100 ms 43.692 ms Stress_Time 4.490 V 4.510 V 4.500 V Stress_Voltage 2.800 uA 11.800 uA 4.564 uA ADC_VDD_I 0.900 uA 11.700 uA 8.163 uA VDD_I_delta 0.900 uA 11.700 uA 8.003 uA ADC_delta_post0.485 - 0.525 - 0.505 - delta_STRESS
Stress the device at a higher VDD than normal while running scan
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High Voltage Scan StressBurn in simulation
3.500 uA 25.000 uA 12.726 uA VDD_I -0.100 - 0.100 - 0.000 - LVSCAN656 -0.100 - 0.100 - 0.000 - HVSCAN3 3.500 uA 25.000 uA 12.567 uA VDD_I_STRESS -0.650 uA 0.650 uA 0.159 uA VDD_I_delta_STRESS 39.900 ms 50.100 ms 43.692 ms Stress_Time 4.490 V 4.510 V 4.500 V Stress_Voltage 2.800 uA 11.800 uA 4.564 uA ADC_VDD_I 0.900 uA 11.700 uA 8.163 uA VDD_I_delta 0.900 uA 11.700 uA 8.003 uA ADC_delta_post0.485 - 0.525 - 0.505 - delta_STRESS
Re measure the typical current consumption
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Confidential © ams AG 2016Page 23
High Voltage Scan StressBurn in simulation
3.500 uA 25.000 uA 12.726 uA VDD_I -0.100 - 0.100 - 0.000 - LVSCAN656 -0.100 - 0.100 - 0.000 - HVSCAN3 3.500 uA 25.000 uA 12.567 uA VDD_I_STRESS -0.650 uA 0.650 uA 0.159 uA VDD_I_delta_STRESS 39.900 ms 50.100 ms 43.692 ms Stress_Time 4.490 V 4.510 V 4.500 V Stress_Voltage 2.800 uA 11.800 uA 4.564 uA ADC_VDD_I 0.900 uA 11.700 uA 8.163 uA VDD_I_delta 0.900 uA 11.700 uA 8.003 uA ADC_delta_post0.485 - 0.525 - 0.505 - delta_STRESS
Re measure the typical current consumption and ensure it hasn’t moved
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Histogram of Stress Test
Repeatability of one device
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Histogram of Stress Test
How one wafer looks
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Failures
Test Device 1 Device 2 Device 3 Device 4 Device 5 Device 6 Device 7 Typ
VDD_I 14.252 14.455 14.156 12.822 15.181 14.327 13.778 12.4
VDD_I_STRESS 13.312 15.667 13.439 11.642 13.842 12.972 12.949 12.4
VDD_I_delta_STRESS 0.94 -1.213 0.717 1.179 1.339 1.355 0.829 0
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All techniques togetherPost Stress
4.4 V 4.6 V 4,5 V Stress_Voltage19 ms 21 ms 20 ms Stress_Time3.055 mA 5.845 mA 4.137 mA IpowAnaMax_post2.400 mA 9.600 mA 7.099 mA IpowDigMax_post29.600 mW 58.400 mW 47.278 mW MaxPower_post0.000 uA 52.250 uA 32.942 uA IpowAnaStandby_post2.000 mA 9.600 mA 5.798 mA IpowDigStandby_post5.000 mW 85.750 mW 21.044 mW StandbyPower_post0.000 uA 285.000 uA 163.118 uA IpowAnaSleep_post0.000 mA 11.400 mA 6.122 mA IpowDigSleep_post2.000 mW 38.100 mW 22.896 mW SleepPower_post718.000 uA 1762.000 uA 854.172 uA IDDq_0x01_post718.000 uA 1762.000 uA 857.386 uA IDDq_0x0B_post-90.000 uA 90.000 uA 3.214 uA IDDq_0x01_del_post968.500 uA 2201.500 uA 1067.917 uA IDDq_0x0F_post25.000 uA 475.000 uA 210.530 uA IDDq_0x0B_del_post1454.500 uA 2795.500 uA 1667.366 uA IDDq_0x11_post489.500 uA 660.500 uA 599.449 uA IDDq_0x0F_del_post1875.000 uA 3225.000 uA 2163.961 uA IDDq_0x31_post325.000 uA 775.000 uA 496.595 uA IDDq_0x11_del_post2683.500 uA 4186.500 uA 2956.263 uA IDDq_0x71_post586.500 uA 1063.500 uA 792.302 uA IDDq_0x31_del_post2683.500 uA 4186.500 uA 2957.870 uA IDDq_0xF1_post 90.000 uA 90.000 uA 1.607 uA IDDq_0x71_del_post
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All techniques togetherDelta of deltas
-200.000 uA 200.000 uA 9.642 uA IpowAnaMax_post_del-400.000 uA 400.000 uA -46.588 uA IpowDigMax_post_del-1.000 mW 1.000 mW -0.117 mW MaxPower_post_del-16.000 uA 16.000 uA 0.000 uA IpowAnaStandby_post-300.000 uA 300.000 uA -54.620 uA IpowDigStandby_post-1.000 mW 1.000 mW -0.197 mW StandbyPower_post_del-16.000 uA 16.000 uA 0.000 uA IpowAnaSleep_post_del-300.000 uA 300.000 uA -62.652 uA IpowDigSleep_post_del-1.000 mW 1.000 mW -0.226 mW SleepPower_post_del-5.000 uA 5.000 uA 0.000 uA IDDq_0x01_post_del-5.000 uA 5.000 uA 0.000 uA IDDq_0x0B_post_del-5.000 uA 5.000 uA 0.000 uA IDDq_0x01_del_post_del-5.000 uA 5.000 uA 0.000 uA IDDq_0x0F_post_del-5.000 uA 5.000 uA 0.000 uA IDDq_0x0B_del_post_del-5.000 uA 5.000 uA 1.607 uA IDDq_0x11_post_del-5.000 uA 5.000 uA 1.607 uA IDDq_0x0F_del_post_del-5.000 uA 5.000 uA 1.607 uA IDDq_0x31_post_del-5.000 uA 5.000 uA 0.000 uA IDDq_0x11_del_post_del-5.000 uA 5.000 uA 0.000 uA IDDq_0x71_post_del-5.000 uA 5.000 uA -1.607 uA IDDq_0x31_del_post_del-5.000 uA 5.000 uA 1.607 uA IDDq_0xF1_post_del-5.000 uA 5.000 uA 1.607 uA IDDq_0x71_del_post_del
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Low Voltage Digital TestsMinus failure passing at room
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Low Voltage Digital TestsMinus temperature failure
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Low Voltage Digital Test Minus failure found at room temp with low voltage
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Coverage
DigFuncOTP 0.3% of failures found per waferBut the real question is how many escapes could there be at cold?
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ppm coverage from 30 lots of 25 wafersStacked map – 15 fails, 3ppm at cold
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Confidential © ams AG 2016
Thank you
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