George Mason University ECE 645 – Computer Arithmetic Introduction to FPGA Tools.
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Transcript of George Mason University ECE 645 – Computer Arithmetic Introduction to FPGA Tools.
ECE 645 – Computer Arithmetic 2
Design process (1)
Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..
Library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; );end AES_core;
Specification (Lab Experiments)
VHDL description (Your Source Files)
Functional simulation
Post-synthesis simulationSynthesis
ECE 645 – Computer Arithmetic 3
Design process (2)
Implementation
Configuration
Timing simulation
On chip testing
ECE 645 – Computer Arithmetic 9
architecture MLU_DATAFLOW of MLU is
signal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;
beginA1<=A when (NEG_A='0') else
not A;B1<=B when (NEG_B='0') else
not B;Y<=Y1 when (NEG_Y='0') else
not Y1;
MUX_0<=A1 and B1;MUX_1<=A1 or B1;MUX_2<=A1 xor B1;MUX_3<=A1 xnor B1;
with (L1 & L0) selectY1<=MUX_0 when "00",
MUX_1 when "01",MUX_2 when "10",MUX_3 when others;
end MLU_DATAFLOW;
VHDL description Circuit netlist
Logic Synthesis
ECE 645 – Computer Arithmetic 10
Features of synthesis tools
• Interpret RTL code
• Produce synthesized circuit netlist in a standard EDIF format
• Give preliminary performance estimates
• Some can display circuit schematics corresponding to EDIF netlist
ECE 645 – Computer Arithmetic 11
Implementation
• After synthesis the entire implementation process is performed by FPGA vendor tools
ECE 645 – Computer Arithmetic 13
Translation
Translation
UCF
NGD
EDIF NCF
Native Generic Database file
Constraint Editor
User Constraint File
Native Constraint
File
Electronic Design Interchange Format
Circuit netlist Timing Constraints
Synthesis
ECE 645 – Computer Arithmetic 14
Sample UCF File
• #• # Constraints generated by Synplify Pro 7.3.3, Build 039R• #• # Period Constraints• #Begin clock constraints• #End clock constraints• # Output Constraints• # Input Constraints• # Location Constraints• # End of generated constraints• NET "clock" LOC = "P88";• NET "control(0)" LOC = "P50";• NET "control(1)" LOC = "P48";• NET "control(2)" LOC = "P42";• NET "reset" LOC = "P93";• NET "segments(0)" LOC = "P67";• NET "segments(1)" LOC = "P39";• NET "segments(2)" LOC = "P62";• NET "segments(3)" LOC = "P60";• NET "segments(4)" LOC = "P46";• NET "segments(5)" LOC = "P57";• NET "segments(6)" LOC = "P49";
ECE 645 – Computer Arithmetic 15
Pin Assignment
LAB2
CLOCKCONTROL(0)
CONTROL(2)CONTROL(1)
RESET
SEGMENTS(0)SEGMENTS(1)SEGMENTS(2)SEGMENTS(3)SEGMENTS(4)SEGMENTS(5)SEGMENTS(6)
P39
P42P46
P48P49P50
P57
P60
P62
P67
P88
P93FPGA
ECE 645 – Computer Arithmetic 22
Static Timing Analyzer
• Performs static analysis of the circuit performance
• Reports critical paths with all sources of delays
• Determines maximum clock frequency
ECE 645 – Computer Arithmetic 23
Static Timing Analysis
• Critical Path – The Longest Path From Outputs of Registers to Inputs of Registers
D Qin
clk
D Qout
tP logic
tCritical = tP FF + tP logic + tS FF
ECE 645 – Computer Arithmetic 24
Static Timing Analysis
• Min. Clock Period = Length of The Critical Path
• Max. Clock Frequency = 1 / Min. Clock Period
ECE 645 – Computer Arithmetic 25
Configuration
• Once a design is implemented, you must create a file that the FPGA can understand• This file is called a bit stream: a BIT file (.bit extension)
• The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information
ECE 645 – Computer Arithmetic 26
Resources & Required ReadingSpartan FPGA devices
Xilinx Spartan-3 FPGA Family: Complete Data Sheets
• Module 1: Introduction & Ordering Information• Module 2: Functional Description
Xilinx Virtex-II 1.5V FPGA Family: Complete Data Sheets
• Module 1: Introduction & Ordering Information• Module 2: Functional Description
ECE 645 – Computer Arithmetic 27
Integrated Interfaces: Active-HDL with Synplify®
http://www.aldec.com/Previews/active_synplify.htm
Integrated Synthesis and Implementationhttp://www.aldec.com/Previews/synthesis_implementation.htm
Resources & Required Reading
FPGA Tools
ECE 645 – Computer Arithmetic 28
Hands-on Session
Enough Talking Let’s Get To It!!Brace Yourselves!!
ECE 645 – Computer Arithmetic 29
0
1Y [3:0]
neg_Y
0
1
ar_log
0
1
2
3
arith [1:0]
A + B
A - B
A <<< 1
A >>> 1
0
1
2
3
logic [1:0]
A and B
A or B
A xor B
A xnor B
A[3:0]
B[3:0]
ALU Schematic