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Journal of ELECTRONIC MATERIALS, Vol.33, No.8, 2004 Regular Issue Paper

886

Germanium-on-Insulator Substrates by Wafer Bonding

CLARENCE J.TRACY,1,4 PETER FEJES,1 N. DAVID THEODORE,1PAPU MANIAR,2 ERIC JOHNSON,2ALBERT J. LAMM,3

ANTHONY M. PALER,3 IGOR J. MALIK,3 and PHILIP ONG3

1.Advanced Products Research and Development Laboratory, Motorola SemiconductorProducts Sector, Tempe, AZ 85284. 2.Microelectronics and Physical Sciences Laboratory,Motorola Labs, Tempe, AZ 85284. 3.Silicon Genesis Corporation, San Jose, CA 95134.4.E-mail: c.tracy@motorola.com

Single-crystal Ge-on-insulator (GOI) substrates, made by bonding a hydrogen-implanted Ge substrate to a thermally oxidized, silicon handle wafer, arestudied for properties relevant to device fabrication. The stages of the layertransfer process are examined through transmission electron microscopy(TEM) from the initial hydrogen implant through the final Ge film polish. The

completed GOI substrate is characterized for film uniformity, surface quality,contamination, stress, defectivity, and thermal robustness using a variety oftechniques and found to be acceptable for initial device processing.

Key words: GOI, wafer bonding, Ge substrate

(Received December 9, 2003; accepted April 20, 2004)

INTRODUCTION

The degradation in performance of silicon metal-

oxide semiconductor (MOS) devices with scalingcaused by fundamental material limitations is forcingthe semiconductor industry to consider extraordinarymeasures. Changes in structure (various forms of dou-ble-gated devices), alteration of material properties inthe channel region (SiGe alloys or strained silicon),and replacement of silicon altogether (digital GaAsbased on a new GaAs gate dielectric) are all being con-sidered. In view of the challenges of introducing any ofthe preceding technologies into full manufacturing,other options that reuse much of the silicon infra-structure and processing knowledge are attractive.

Pure Ge is one such possibility. The availabilityof good quality, bulk Ge wafers as large as 200 mm,

driven by the solar cell industry for space applica-tions, combined with significantly larger mobilitiesfor both electrons and holes when compared tosilicon are two immediate positives. Junctions areeasily formed by implanting and annealing the usualelements (B, P, As, etc.) with solid solubilities thatare reasonable. Germanides made with familiar ma-terials readily form to enable contact metallization.

However, Ge suffers from a potentially fatal flawincreased leakage because of the lower bandgap

which now appears possible to overcome in partthrough the use of Ge-on-insulator (GOI) substratesthat up to now have not been commonly available.

Relaxed silicon-GOI substrates with Ge percentagesas high as 25% have been demonstrated and areintended to be used for heteroepitaxial growth ofdevice material layers.1 Germanium layers havebeen transferred directly onto silicon using the hy-drogen-induced splitting process for photovoltaicapplications.2 The Ge p-channel, MOS field-effecttransistors (FETs) have been built on GOI sub-strates made through a bond and etch-back process,but little characterization is described of the sub-strate itself and etch-back processes typically arelimited to thicker films.3

The first industrially manufactured, 150-mm-diameter GOI wafers are now available in limited

quantities. It is critical both to understand thedetails of the process by which they are made andthe quality of the end result before attempting tobuild evaluation devices. The former enables thecontinuous improvement of these substrates whilethe latter is a requirement before inserting thismaterial into a wafer processing line. In this paper,we report on both aspects.

GOI WAFER PROCESSING

The basic process steps46 from Silicon Genesispatented technology (San Jose, CA) for fabricating

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150-mm-diameter GOI substrates are illustratedschematically in Fig. 1. These steps are (1) forma-tion of a strained-layer cleave plane by hydrogenimplantation; (2) thermal oxidation of a handlesilicon wafer to form the buried oxide (BOX) layer;

(3) plasma-activated bonding of the Ge donor and Sihandle wafers;7,8 (4) room-temperature separationof the wafers within the cleave plane, leaving theGe device layer attached to the BOX/handle wafer;and (5) optional postcleave processing to thin theGe layer, reduce surface roughness, and remove ion-implant recoil damage.

The transmission electron microscopy (TEM) mi-crographs in Fig. 2 show the Ge substrate at vari-ous stages of this fabrication process. The Ge donorwafer is implanted with hydrogen ions of a pre-scribed energy to reach a specific depth to establishthe cleaving plane and thickness of the transferredfilm (Fig. 2a).

After an appropriate clean,9,10

the Ge is thenplasma-activated and bonded to the oxidized siliconhandle as an initial step in the low-temperaturebonding process. The bonded pair then receives alow-temperature bond treatment to optimize thebond strength.

Finally, the Ge wafer is mechanically separated atroom temperature from the oxidized silicon handleas the thin Ge layer is transferred. This controlledcleaving is a low stress-layer transfer process that

proceeds from a separation initiation at the edgegroove of the bonded wafer pair. This initiationcauses a transverse cleave propagation that movesquickly through the engineered cleave plane in acontrolled manner.4 The resulting surface of the as-cleaved, transferred Ge film exhibits a significantroughness on the order of200 root mean square(RMS). Some residual damage from the implant isstill visible (Fig. 2c). The process can include an ad-ditional step, such as chemical-mechanical polishing(CMP), to reduce surface roughness, remove theimplant damage, and thin the Ge layer to the de-sired thickness (Fig. 2c and d). Polishing of theseGOI samples after cleaving was done through a Gewafer supplier.11

The cross-sectional transmission electron mi-croscopy (XTEM) results show microstructuralchanges in the Ge as it is implanted, bonded,cleaved, and CMP smooth-polished. In the as-implanted Ge, a band of implant damage is visible.

As-implanted ions penetrate the Ge and implant

cascades form, resulting in the presence of intersti-tials and vacancies in the material. During theimplantation process, these point defects can dif-fuse and then coalesce to form point-defect clusters.Strain around the clusters results in localizedcontrast in the TEM micrographs. A band of suchclusters results in the implant damage band seenin Fig. 2a.

Upon exposure to thermal treatment, the point-defect clusters can grow as seen by the generalcoarsening of features in the damage region anda roughening near the top of the implant region(Fig. 2b). The defects tend to cluster together in atight band at the approximate depth and location

of the band of point-defect clusters that were seenin the as-implanted sample (Fig. 2a). Occasionally,a dislocation threads upward toward the surface ofthe wafer. However, the density of such defects is re-duced toward the surface of the wafer. Following thisstep, the wafer is cleaved using the compressive-stress implant layer as a guiding plane controllingthe fracture propagation.

In Fig. 2c, we see the microstructure of the Ge-on-SiO2 after the donor wafer has been cleaved off.

materials.

Fig. 2. The XTEM bright-field images of substrates at various sequential stages in the process of making GOI wafers. The diffraction conditionsfor these images were close to the 220 Bragg condition. The XTEM of implanted Ge (a) with no thermal treatment, (b) with thermal treatmentequivalent to bonding cycle, (c) after bonding to silicon dioxide on silicon and the cleave process, and (d) the XTEM of Ge film after transfer,cleave, and CMP smoothing.

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Significant surface roughness is evident.This rough-ness arises from the fact that the cleavage locations(in the implanted Ge) depend on the Ge materialproperties and H-induced stress distributions. Occa-sionally, a threading dislocation is seen in the Gelayer (e.g., Fig. 2c). This is consistent with the occa-sional presence of such threading dislocations in theGe above the implant damage seen in the thermallytreated Ge (Fig. 2b).

After the Ge film has undergone CMP, the surfaceroughness has decreased substantially (Fig. 2d). Thespeckled contrast in the TEM micrograph (Fig. 2d)suggests the presence of point-defect clusters in theimplant- and cleave-processed Ge. It is not entirelyclear, at this time, whether these defects are intrin-sic to the processed Ge or if these arise during TEMspecimen preparation. However, Ge etch-rate stud-ies do suggest a likely presence of such defects inthe H-implanted and cleaved Ge layers. The follow-ing characterization results have largely been doneon unannealed samples, whereas it is becoming

evident that GOI wafers may benefit from a finalhigh-temperature heat treatment.

GOI WAFER CHARACTERIZATION

The characteristics of the incoming GOI substratescan be divided into three categories: (1) macroscopicproperties, including thickness uniformity, roughness,stress, visual defects, and surface contamination; (2)material defects; and (3) processing robustness.

Optical microscope inspection of a recent lot ofsix wafers was used to look for and measure thedensity of large defects. Most commonly observedis a small circular feature usually less than 20 min diameter, as shown in Fig. 3. Closer microscope

inspections indicate these are voids where the Gefilm is missing, and based on the color, the full thick-ness BOX layer is exposed. This is confirmed byscanning electron microscopy (SEM) evaluationsand Auger analysis of the surface within the void,which finds only silicon and oxygen signals. Approx-

imately 25 cm2 of each wafer is scanned, and thedefects manually counted, which yields a defect den-sity of ranging from 2.2 defects/cm2 to 4 defects/cm2,depending on the wafer. While this is still unac-ceptable for very large-scale integration manufac-turing, it is a dramatic improvement from the 200

void defects/cm2 observed on the first GOI materiallots of a few months ago and does not prevent

proceeding with device feasibility development.The Ge film thickness and thickness uniformitydata in Table I were measured using spectroscopicreflectometry on a commercially available tool map-ping 46 points/wafer. The targeted thicknesses wereintentionally varied over the lot, resulting in mean

values for the thickest sample at 159 nm and thethinnest at 76 nm. The thickness range for anygiven wafer is on the order of 20 nm and so becomesan increasingly significant percentage variation forthe thinnest samples. This thickness control and

variation is sufficient for some devices and applica-tions but will need improvement for others (e.g.,fully depleted MOSFETs) where the Ge film will

need to be a few tens of nanometers.Atomic force microscopy (AFM) was used toevaluate the roughness of the GOI surface in com-parison to the bulk Ge epi-ready substrates that arecommercially available. Figure 4 compares AFM-generated images and lists both the Rq (RMS) andZr (range) values for bulk Ge and GOI substrates oftwo different Ge-film thicknesses. The surfaceroughness of all three samples is similar with Rqand Zr values of0.25 nm and 7 nm, respectively.For comparison, a silicon wafer measured under thesame conditions has Rq and Zr values of 0.07 nmand 0.67 nm, respectively, and is significantlysmoother than any of the Ge material. A second

point to note is that the thicker GOI sample showsa significant density of pit-like defects and a corre-spondingly slightly larger Zr. The density of thistype of defect, as determined by examining AFM im-ages for six wafers with Ge thicknesses greater than150 nm, is estimated to be 2 107/cm2, whereasnone of this type of defect were seen on images offive wafers with Ge thicknesses of approximately100 nm or less. Examination of XTEM images ofunpolished GOI specimens, focusing on defects thatcould come to within 100 nm of the surface ofthe implanted sample, yields an estimated defect

Fig. 3. Optical micrograph showing typical void defect in GOIsubstrate.

Table I. Optical Reflectometry Ge Film-ThicknessMeasurements

Mean Max Min Std.Sample (nm) (nm) (nm) Dev. (%)

1 75.6 86.9 57.5 10.32 90.5 97.3 77.9 5.5

3 93.8 101.8 87.8 3.44 102.6 108.9 91.6 3.35 136.2 142.4 126.5 2.56 159.1 172.2 150.4 3.3

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density in the 1 1071 108/cm2 range. The de-fects do not appear to be threading dislocations;

rather, they appear to be platelets on inclined {111}planes. This means that the defect density wouldvary quite sharply as we thin the sample downto 100 nm, 90 nm, or 80 nm (substantially lowerdefects) as opposed to 110 nm, 150 nm, etc. (higherdefects). Thus, it is believed that the AFM detectedpits are related to these platelets, emphasizing theneed to remove enough Ge during the smoothingprocess to remove the defects created by the specifichydrogen-implant conditions used on these samples.

Raman spectroscopy was performed on two GOIsamples and compared to a bulk Ge wafer with thesame doping (Sb, approximately 2 1017 cm3 ) as areference to measure film stress and give an indica-

tion of crystallinity. The frequency and full-width athalf-maximum (FWHM) are listed in Table II for theRaman peak around 300 cm1 corresponding to thelongitudinal optical phonon in Ge. The bulk refer-ence sample has a peak frequency corresponding tounstrained Ge and a peak width reflecting goodcrystallinity. The two GOI films show no significant

frequency shift and, therefore, are almost stress free(20 MPa either tensile or compressive), but theslight consistent increase in the Raman peak widthsuggests that the crystallinity is poorer than thebulk sample.

To confirm the low stress levels present in theGe film, x-ray triple-axis diffraction (004) 2-scans were used to determine the lattice constantin absolute units. At room temperature, the verti-cal lattice constant c of Ge in GOI is measured as0.5657 nm, which is in good agreement with theliterature value of 0.5658 nm for bulk Ge.

Total reflection x-ray fluorescence (TXRF) analy-sis to measure metal contamination on the sur-face of a single, 150-mm-diameter polished GOIwafer was performed in the typical manner,12 exam-

ining 10-mm-diameter areas at three locationsalong a radius line, and the results are reportedin Table III. High levels of Ca and Zn are observedin spectra from all locations of the wafer, whereasCr, Fe, Ni, and Cu are observed at lower levelsin some locations. In addition to the data in TableIII, a Si signal is observed, but initially, it wasnot clear whether this signal is due to contami-nation from some Si-containing component of thepolishing compound or if it is due to the exposedsilicon oxide at the bonding interface in a few small

void defects. A TXRF analysis done on a bulk Gewafer processed through the same polishing processagain revealed high levels of Si, indicating that at

least some of this contamination is likely due to theCMP module. The 2003 International Technology

Roadmap for Semiconductors13 sets surface metalliccontamination limits for future starting substrates

Table II. Raman Peak Frequency and FWHM forGe Bulk and GOI Samples

Phonon PeakFrequency FWHM

Samples (cm1) (cm1)

Ge (bulk reference wafer) 299.73 2.95 0.05GOI sample 1 299.60 3.02 0.05GOI sample 2 299.74 3.06 0.05

Table III. The TXRF Results at Three Sites on a GOI Wafer*

Site S Cl K Ca Ti Cr Mn Fe Ni Cu Zn Ar

1 700 50 185 17 10 670 40 4 8.3 1.3 1.9 2.5 1.2 3.5 1.5 8.5 2 230 14 55 92 1,020 70 140 15 11 1,300 80 4 7.7 1.3 2 1.8 4 2 4 1.8 270 16 53 93 370 30 70 12 11 1,440 90 4 5 1.2 2 4.7 1.5 1.7 7.7 2 230 14 34 8

*Units of 1010 atoms/cm2.

Fig. 4. The AFM images (5 m 5 m scan area) of (a) a bulk Ge wafer, (b) a GOI wafer with 158-nm Ge thickness, and (c) a GOI wafer with76-nm Ge thickness.

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Tracy, Fejes,Theodore, Maniar, Johnson, Lamm, Paler, Malik,890 and Ong

at 1 1010 atoms cm2, somewhat below the mea-sured levels. However, at this stage of development,the actual impact of specific contaminants on theyield of Ge MOS devices is not known. A secondconsideration is meeting the cross-contaminationprotocol limits of a silicon pilot line where shareddevelopment of Ge technology is to be done. None ofthe observed contamination levels are sufficientlyalarming to prevent processing of these substratesin a pilot line, but they do point out the need forreducing metal contamination at the CMP vendorand development of appropriate clean sequences forGe surfaces.

Material defects in the GOI film are studied usingtwo methods. First, etch rates of the film are used asan uncalibrated indication of the damage level withthe assumption that such will enhance the etch rate.Second, plan-view TEM images in addition to thecross section described earlier provide increasedsensitivity to lower defect densities because of thegreater sample area. As discussed later, both meth-

ods indicate degraded crystalline quality as was alsosuggested by the increased Raman peak width.Etch-rate studies in room temperature (2025C)

1:10 H2O2:H2O comparing bulk single-crystal Gewafers, sputtered polycrystalline Ge films, and GOIsubstrates showed surprising differences. Whereasboth bulk and polycrystalline Ge etched at rates be-tween 20 nm/min and 30 nm/min, GOI materialetched at rates between 100 nm/min and 129nm/min. The AFM measurements of the Rq (RMS)roughness of the bulk single-crystal wafer after 10min of etching showed no change, but with just 30sec of etching, the Rq for the GOI sample more thandoubled. These results indicate that the Ge film of

the GOI substrate is significantly damaged duringthe manufacturing process.Plan-view TEM samples were prepared of the

Ge film on a GOI sample after CMP. After mechani-cally polishing the piece of wafer from the backsideto remove the bulk of the substrate, the remainingmaterial was thinned to electron transparency byfocused ion-beam thinning. We estimate that weare viewing approximately the top 100 nm of theGe film.

Figure 5 shows three types of defects that are ob-served. First, there are small dislocation loops withdiameters200 nm. Most of these loops are circular,with a few having irregular shapes.There is no vari-

ation of contrast with depth that is normally seenwith inclined dislocations; so these loops are as-sumed to be roughly parallel with the (001) plane ofthe wafer surface. These defects are observed at adensity of approximately 4 107 cm2. Because ofthe regularity of these residual defects, it is thoughtthat what is being observed may be strain aroundthe defect edges in the Ge film.

The second type of defect observed is seen assections of dislocation loops inclined to the (001)plane of the wafer surface. These dislocation loopsare generally much larger than 200 nm and are

probably the same dislocations that have been iden-tified in XTEM as threading dislocation loops. Theirdensity is measured as 3 107 cm2.

The third type of defect observed in the plan-viewTEM sample consists of patches that may appeareither dark or light in the bright-field images. Theyhave diameters 300 nm and exhibit no strain fieldassociated with them. They are most likely surface

features, possibly pits in the Ge surface, as havebeen detected by AFM and that will appear eitherdark or bright, depending on the exact diffractingconditions.

Finally, the thermal robustness of the GOI mater-ial, an essential question before attempting deviceprocessing, was examined. Activation studies forphosphorus implanted into Ge show that annealtemperatures in excess of 600C may be required.14

The low melting temperature of Ge (937C) andthe significant difference between the linear coeffi-cients of thermal expansion at 300 K for Ge (5.8 106 C1) and silicon (2.6 106 C1), therefore,raise concerns.15 The previously discussed Raman

data confirms that, at room temperature, the Ge isnot strained, but upon heating, it will go into com-pressive stress, and at high enough temperatures, itis expected to relax by creating material defects.Then, upon cooling, it will go into tensile strain andpotentially additional defects may be created. To ini-tially examine this issue, small specimens cut froma GOI wafer were annealed on a hot stage in high

vacuum at set point temperatures of 725C, 815C,and 960C for about 1 h followed by optical, AFM,and SEM inspections as appropriate. Actual sampletemperatures are believed to be 1525C lower than

Fig. 5. Plan-view bright-field TEM image with the 220 Bragg conditionsatisfied of the Ge film showing the three types of defects found in thisfilm. A: small round loops in the (001) plane of the wafer surface.These are assumed to be hydrogen platelets. B: Dislocation loops atan angle to the (001) plane of the wafer surface. C: Surface features,probably pits in the Ge surface.

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the set point and further calibrations are in pro-

gress. Figure 6 presents a plan-view TEM micro-graph obtained from a GOI wafer annealed at 725Cfor 1 h. No extended defects were observed. Figure 7shows AFM images for the 815C annealed sampleand the unannealed control and clearly indicatesthe appearance of defects. The well-defined surfacesteps are believed to be due to slip within the Gecrystal because with temperature both the materialductility and the mechanical stress induced by theconstraining silicon substrate increase. The resultsappear similar to those described in the literaturefor bulk Ge substrates.16 No change was observedfor the 725C annealed sample, whereas drasticchanges in the film were apparent in the opticalmicroscope inspection of the 960C sample. The re-

sults confirm that the thermal processing concernsare real but only if temperatures approach 800C orhigher.

CONCLUSIONS

The 150-mm GOI substrates consisting of about a100-nm Ge film on a thermally oxidized, silicon han-dle wafer are now commercially available in small

quantities and with sufficient quality to allow devicedevelopment studies to begin. Analysis of variousproperties as-received and following high-tempera-ture processing cycles indicate that these substratesdo not pose a risk to a modern pilot line beyond thatassociated with the processing of the Ge material it-self. Surface smoothness and metal contaminationare acceptable for building devices to enable under-standing the technical and business value of usingGe for some future applications.

However, there are several issues that must beaddressed if these wafers are to be ultimately usedin manufacturing. Macroscopic defect densities arehigh, and Raman, TEM, and etch-rate data indicate

that crystalline quality of the Ge film is degraded.Surface contamination with some metals is higherthan considered acceptable for silicon substrates, andthe unusual presence of silicon contamination on theGe surface may be important for certain processes.

Additionally, the variation in Ge film thicknessacross the substrate after the polishing process is toogreat to allow the ultrathin layers essential for someof the more interesting future devices. Finally, theseproblems have to be solved not only for 150-mmwafers but also for 200-mm and 300-mm wafers. Ona positive note, none of these issues appear to bea showstopper and reuse of the knowledge learnedin building standard silicon-on-insulator substratesshould accelerate progress.

Fig. 6. Plan-view TEM of the GOI wafer annealed at 725C for 1 h. Abright-field image with the 220 Bragg condition satisfied. No defectswere seen. The dark bands visible in the micrograph are bendcontours and thickness fringes.

Fig. 7. The AFM images (5 m 5 m scan area) of the GOI surface: (a) not annealed and (b) annealed at 815C.

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5. I.J. Malik, S.W. Bedell, H. Kirk, M. Korolik, S. Kang,M.I. Current, and F.J. Henley, 2000 InternationalConference on Solid State Devices and Materials X(Tokyo:Business Center for Academic Societies Japan, 2000),pp. 490491.

6. W.G. En, I.J. Malik, M.A. Bryan, S. Farrens, F.J. Henley,N.W. Cheung, and C. Chan, Int. IEEE SOI Conf. Proc.(Piscataway, NJ: IEEE, 1998), pp. 163164.

7. S. Farrens, J.R. Dekker, J.K. Smith, and B.E. Roberds,J. Electrochem. Soc. 142, 3949 (1995).

8. I.J. Malik, S. Kang, J. Sullivan, M. Fuerfanger, P.J. Ong, andF.J. Henley,Spring 2003 ECS Meeting, Extended Abstract(Pennington, NJ: Electrochemical Society, 2003).

9. S. Gan, L. Li, and R.F. Hicks,J. Electrochem. Soc. 73, 1068(1998).

10. J.M. Zahler, C.G. Ahn, S. Zaghi, H. Atwater, C. Chu, andP. Iles,Mater. Res. Soc. Symp.Proc. 681E, I4.5.1 (2001).

11. Umicore Electro-Optic Materials, Olen, Belgium.12. Charles Evans & Associates, Sunnyvale, CA.13. International Technology Roadmap for Semiconductors,

2003 edition, http://public.itrs.net14. C. Jasper, L. Rubin, C. Lindfors, K.S. Jones, and J. Oh,

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15. S.M. Sze, Physics of Semiconductor Devices (New York:John Wiley & Sons, Inc., 1981), pp. 850851.

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Tracy, Fejes, Theodore, Maniar, Johnson, Lamm, Paler, Malik,892 and Ong

ACKNOWLEDGEMENTS

The authors acknowledge the support of theMotorola Microelectronics and Physical SciencesProcess and Characterization Laboratories and theMotorola APRDL Physical Analysis Laboratory(Tempe, AZ). Special thanks go to Diana Convey forthe AFM analysis and Dr. Ran Liu for the Raman

spectroscopy studies.

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