AMINI PROJECT REPORTONGENERALIZED SUBSTITUTION BOXSubmitted in partial fulfillment of the requirements for the award of degree ofBACHELOR OF TECHNOLOGY InELECTRONICS AND COMMUNICATION ENGINEERINGByK.SAKETH REDDY A.HARI KRISHNA S.SUPRIYA B.HAREESHCH.MOUNIKA [11QK1A0433] [11QK1A0413] [11QK1A0454] [11QK1A0412][11QK1A0417]Under the esteemed guidance of Mr. P.V.N SWAMY Assoc. Professor & HOD E.C.E Dept DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING JYOTHISHMATHI INSTITUTE OF TECHNOLOGICAL SCIENCES (Recognized by AICTE & Affiliated to JNTUH, Hyderabad) RAMAKRISHNA COLONY, KARIMNAGAR-505481JYOTHISHMATHI INSTITUTE OF TECHNOLOGICAL SCIENCES RAMAKRISHNA COLONY, KARIMNAGAR-505481DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERINGCERTIFICATEThis is to certify that this project work entitled GENERALIZEDSUBSTITUTION-BOX is a bonafide work carried out by K.SAKETH REDDY(11QK1A0408), A.HARI KRISHNA (11QK1A0413), S.SUPRIYA (11QK1A0454),B.HAREESH (11QK1A0412), CH.MOUNIKA (11QK1A0417) in partial fulfillment ofthe requirements for the award of Bachelor of Technology in Electronics andCommunication Engineering during the period of 2013-2014 under the guidance andsupervision.Internal GuideMr. P.V.N SWAMY Assoc. Professor Dept. of ECEJMTK, Karimnagar. Head of the Dept Mr. P.V.N.SWAMYAssoc. Professor Dept. of E.C.EJMTK ,Karimnagar.DECLARATIONWe, K.SAKETH REDDY (11QK1A0408), A.HARI KRISHNA (11QK1A0413),S.SUPRIYA(11QK1A0454),B.HAREESH(11QK1A0412),CH.MOUNIKA(11QK1A0417)herebydeclarethattheprojectentitledGENERALIZEDSUBSTITUTION-BOX, submitted in the partial fulfillment of the requirements forthe award of B.Tech., in Electronics and Communication Engineering toJyothishmathi Institute of Technological Sciences, Ramakrishna Colony, Affiliatedto JNTU, Hyderabad is a authentic work and has not been submitted to any otheruniversity or institute for award of the Under Graduation.K.SAKETH REDDY A.HARI KRISHNA S.SUPRIYA B.HAREESHCH.MOUNIKA [11QK1A0433] [11QK1A0413] [11QK1A0454] [11QK1A0412][11QK1A0417]iiiACKNOWLEDGEMENTBehind every success of work there is a good guidance, suggestions and motivations. We think it is our duty to convey our heart full thanks to those whose contribution made this project success.The completion of this project would be incomplete without naming the people who made it possible, whose constant guidance and encouragement made this project work.It is a great pleasure to express our deepest sense of gratitude and indebtedness to Dr. V. POORNA CHANDRA RAO, Principal, Jyothishmathi Institute of Technological Sciences, Karimnagar for providing the college facilities for the completion of the project.We wish to express our sincere thanks to our mini project guide Mr.P.V.N.SWAMY, Assoc.Prof.,& Head of Dept ECE, Jyothishmathi Institute of Technological Sciences, Karimnagar for giving their valuable suggestions and for having been a source of constant inspiration, precious guidance and generous assistance during the project work. We deem it as a privilege to have worked under his able guidance. Without his close monitoring and valuable suggestions this work wouldnt have taken this shape. We feel that this help is un-substitutable and unforgettable.Finally, we thank all the faculty members, management and supporting staff of ECE Dept. and friends for their kind co-operation and valuable help for completing the project.K.SAKETH REDDY A.HARI KRISHNA S.SUPRIYA B.HAREESHCH.MOUNIKA [11QK1A0433] [11QK1A0413] [11QK1A0454] [11QK1A0412][11QK1A0417]ABSTRACTIn Cryptography,an S-Box (Substitution-box) is a basic component symmetric key algorithms which performs substitution. In the block ciphers, they are typically used toobscure the relationship between the key and the cipher text Shannon's property of ConfusionIn general,an S-Box takes some number of input bits, m,and transforms them into some number of output bits, n,where n is not necessarily equal to m.An mxn S-Box canbe implemented as a lookup table with 2m words of n bits each.Given a 6-bit input, the 4-bit output is found by selecting the row using the outer two bits (the first and the last bits), and the column using the inner four bits. For example, an input "011011" has outer bits "01" and inner bits "1101"; the corresponding output would be "1001.The main design features of the proposed system are the configurability and flexibility. The proposed system is design using VHDL and is implemented by using the Modelsim software and also in Active HDL 4.2 SE version.vINDEXTOPICABSTRACT CONTENTSLIST OF FIGURESLIST OF TABLES PAGE NOS(v) (vi) (viii)(ix)CONTENTSTOPICCHAPTER 1INTRODUCTION1.1 Motivation and History 1.2 CryptographyCHAPTER 2 VLSI & FPGA 2.1 VLSI Technology 2.2 What are FPGAS 2.3 Types of FPGAS2.3.1 History of FPGA2.4 Basic FPGA Architecture 2.5 FPGA Design flow2.6 General View of FPGA 2.7 FPGAS Vs CPLDS 2.8 How FPGAS work2.9 Advantages and Disadvantages of FPGA2.10Hardware Description Languages PAGE NOS01-030102-0304-19 04 06 06 07 07 08 13 14 16 1819CHAPTER 321-26INTRODUCTION TO VLSI3.1 Overview21 3.2 What is VLSI?22 3.3 History of Scale Integration23 3.4 VLSI and Systems24 3.5 Applications25CHAPTER 427-47VHDL4.1 History of VHDL 27 4.2 Levels of Abstraction 30 4.3Need for VHDL 32 4.4Advantages of VHDL 33 4.5DesignMethodology using VHDL 34 4.6Elementsof VHDL 35 4.7VHDL Language Features 36 4.8DataTypes 45CHAPTER 547-51 VERILOG HDL5.1 History47 5.2 Major Capabilities48 5.3 Synthesis49CHAPTER 652-56 S-BOX6.1 Cryptography52 6.2Substitution Box 54CHAPTER 7RESULTS AND CONCLUSION57REFERENCES58LIST OF FIGURESfig 2.2 Basic FPGA Architecture07 fig 2.3 FPGA Design flow09 fig 4.1 Levels of Abstraction30 fig 5.1 Mixed Level Modeling49 fig 5.2 Synthesis Process50 fig 5.3 Typical Design Process51 fig 6.1 Information Box diagram53 fig 6.2 Public Key Cryptography54LIST OF TABLESTable 2.1 Comparision between CPLD & FPGA14Table 6.1.An example of 6x4 bit S-Box55INTRODUCTIONCHAPTER-1 INTRODUCTION1.1 Motivation and History:Cryptography has roots that began around 2000 B.C. in Egypt when thehieroglyphics were used to decorate tombs to tell the story of the life of the deceased. Thepractice was not as much to hide the messages themselves, but to make them seem morenoble, ceremonial and majestic. Encryption methods evolved from being mainly for theshow into practical applications used to hide the information from others. A Hebrewcryptographic method required the alphabet to be flipped so that each letter in the originalalphabet is mapped to a different letter in the flipped alphabet. The encryption methodwas called at bash. An example of an encryption key used in the at bash encryption is as shown in following:ABCDEFGHI JK LMNOPQ R STU VW XYZ ZYXWVUTSR QP ONMLKJ I HGF ED CBAAround 400 B.C., the Spartans used a system of encrypting information by writing a message on a sheet of papyrus, which was wrapped around a staff. (This would look like a piece of paper wrapped around a stick or wooden rod.) The message was only readable if it was around the correct staff, which allowed the letters to properly matchup. This is referred to as the scytale cipher.When the papyrus was removed from the staff, the the writing appeared as just a bunch of random characters. The Greek government had carriers run these pieces of papyrus to different groups of soldiers.During World War II, simplistic encryption devices were used for tactical communication, which drastically improved with the mechanical and electromechanical technology that provided the world with telegraphic and radio communication. The rotor cipher machine, which is a device that substitutes letters using different rotors within the machine, was a huge breakthrough in military cryptography that provided complexity that proved difficult to break. This work gave way to the most famous cipher1INTRODUCTIONmachine in history to date: Germanys enigma machine. The Enigma machine had three rotors, a plug board, and a reflecting rotor.As computers came to be, the possibilities for encryption methods and the devices advanced, and cryptography efforts expanded exponentially. This era brought an unprecedented opportunity for cryptographic designers and encryption techniques. The most well-known and successful project was Lucifer, which was developed at IBM. Lucifer introduced complex mathematical equations and functions that were later adopted and modified by the U.S. National Security Agency (NSA) to come up with the U.S.Encryption is used in the hardware devices and software to protect data, Banking transactions, corporate extranets, e-mail, Web transactions, faxes and wireless communications, storing of confidential information, and phone calls. The code breakers and cryptanalysis efforts and the amazing amount of number crunching capabilities of the microprocessors hitting the market each year quickened the evolution of cryptography so the Cryptanalysis is a science of studying and breaking the secrecy of the encryption algorithms and their necessary pieces. Different types of cryptography have been used throughout civilization, but today it is deeply rooted in every part of our communication and computing world. Automated information systems and cryptography play a huge role in the effectiveness of militaries, functionality of governments, and economics of private businesses. As our dependency upon technology increases, so does our dependency upon cryptography, because secrets will always need to be kept.1.2 Cryptography:Cryptography is a method of storing and transmitting data in a form that only who are intended to read and process. Cryptography is an effective way of protecting sensitive information as it is stored on media or transmitted through network communication paths. Although the ultimate goal of cryptography, and the mechanisms that make it up, is to hide information from unauthorized individuals, most algorithms can be broken and the information can be exposed if the attacker has enough time, desire, and resources. So a more realistic goal of cryptography is to make obtaining the information too work-intensive to be worth it to the attacker.2INTRODUCTIONCryptographic algorithms can be divided into three several classes as : Public key algorithms, Symmetric key algorithms and Hash functions. While the firsttwo are used to encrypt and decrypt data, the third is hash functions are the one-way functions that do not allow the processed data to be retrieved. Hash function also called as message digest or one way encryption algorithm that cannot use any keys throughput by unrolling the calculation structure, but at the expense of more hardware resources.Cryptosystems can provide four types of security services. They are as follows: Confidentiality, Authenticity, Integrity, and Non-repudiation. It does not provide availability of data or systems. Confidentiality means that unauthorized parties cannot even access information. Authenticity refers to validating the source of the message to ensure the sender is properly identified. Integrity provides assurance that the messagewasnot modified during the transmission, accidentally or intentionally. Non-repudiationmeans that a sender cannot deny sending the message at a later date, and the receivercannot deny receiving it. So if your boss sends you a message telling you that you will bereceiving a raise that doubles your salary and it is encrypted, encryption methods can alsoensure that it really came from your boss, that someone did not alter it before it arrived itinto your computer, that no one else was able to read this message as it travelled over thenetwork, and that your boss cannot deny sending the message later when he comes to his senses.3INTRODUCTION4VLSI & FPGACHAPTER 2 VLSI AND FPGA2.1 VLSI TECHNOLOGY:Digital systems are highly complex at their most detailed level. They may consist ofmillions of elements i.e., transistors or logic gates. For many decades, logic schematics served asrequisite of logic design, but not any more. Today, hardware complexity has grown to such a degree that a schematic with logic gates is almost useless as it shows only a web of connectivity and not functionality of design. Since the 1970s, computer engineers, electrical engineers and electronics engineers have moved towards Hardware description language (HDLs).Digital circuit has rapidly evolved over the last twenty five years .The earliest digitalcircuits were designed with vacuum tubes and transistors. Integrated circuits were then invented where logic gates were placed on a single chip. The first IC chip was small scale integration (SSI) chips where the gate count is small. When technology became sophisticated, designers were able to place circuits with hundreds of gates on a chip. These chips were called MSI chips with advent of LSI, designers could put thousands of gates on a single chip. At this point, design process is getting complicated and designers felt the need to automate these processes.With the advent of VLSI technology, designers could design single chip with more than hundred thousand gates. Because of the complexity of these circuits computer aided techniques became critical for verification and for designing these digital circuits. One way to lead with increasing complexity of electronic systems and the increasing time to market is to design at high levels of abstraction. Traditional paper and pencil and capture and simulate methods have largely given way to the described un synthesized approach.For these reasons, hardware description languages have played an important role indescribe and synthesis design methodology. They are used for specification, simulation and synthesis of an electronic system. This helps to reduce the complexity in designing and products are made to be available in market quickly.4 Generalized Substitution-boxVLSI & FPGAThe components of a digital system can be classified as being specific to an application or as being standard circuits. Standard components are taken from a set that has been used in other systems. MSI components are standard circuits and their use results in a significant reduction in the total cost as compared to the cost of using SSI Circuits. In contrasts, specific components are particular to the system being implemented and are not commonly found among the standard components.2.2 WHAT ARE FPGAs?FPGA stands for Field Programmable Gate Array.Field Programmable means that the FPGA's function is defined by a user's program rather than by the manufacturer of the device. It can be programmed in a number of different languages.Definition: Programmable Digital Logic Chips that can be programmed to perform any digitalfunction.1. The FPGA is an integrated circuit that contains many (64 to10,000)identical logic cells that can be viewed as a standard components.2. The individual cells are interconnected by a matrix of wires and programmable switches. 3. Speed up to 200 MHz or more.As their name implies, FPGAs offer significant benefit of being readily programmable. Unlike their forbearers in PLD category, FPGAs can be programmed again and again, giving designers multiple opportunities to tweak their circuits.2.3 TYPES OF FPGAS:1. SRAM based:a.Static memory technology.b.Insystemprogrammableand reprogrammable.c.Requires external boot devices.5 Generalized Substitution-boxVLSI & FPGA2. FLASH based:a Flash-erase EPROM technology.b Can be erased, even in plastic packages. c. Can be in-system programmed.d. Does not require power supply to maintain information. 2.3.1 History of FPGAS:1. The historical roots of FPGAs are in complex programmable logic devices(CPLDs) of the early to mid 1980s.2. Field programmable gate arrays (FPGA) arrived in 1984 as an alternative to programmable logic devices (PLDS) and ASICS.3. A Xilinx co-founder invented the field programmable gate array in 1984.4. CPLDs and FPGAs include a relatively large number of programmable logic elements.5. While the first FPGAs didn't have internal memories, all new FPGAs have internal memories. That increases a lot their scope of applications.2.4 BASIC FPGA ARCHITECTURE:FPGAs fill a gap between discrete logic and the smaller PLDs on the low end of the complexity scale and costly custom ASICs on the high end. They consist of an array of logic blocks that are configured using software. Programmable I/O blocks surround these logic blocks. Both are connected by programmable interconnects. The programming technology in an FPGA determines the type of basic logic cell and the interconnect scheme. In turn, the logic cells and interconnection scheme determine the design of the input and output circuits as well as the programming scheme.6 Generalized Substitution-boxVLSI & FPGAFig 2.2: Basic FPGA ArchitectureDigital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase shifting clock signals. Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storage elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of logical functions as well as to store data.Input/output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. The Input/output Block (IOB) provides a programmable, bidirectional interface between an I/O pin and the FPGAs internal logic. Block RAM provides data storage. Multiplier blocks accept two binary numbers as inputs and calculate the product.2.5 FPGA DESIGN FLOW:The process of implementing a design on an FPGA can be broken down in to several stages, loosely definable as design entry or capture, synthesis, and place and route. Along the way, the design is simulated at various levels of abstraction as in ASIC design. The availability of sophisticated and coherent tool suites for FPGA design makes them all the more attractive.7 Generalized Substitution-boxVLSI & FPGAAt one time, design entry was performed in the form of schematic capture. Most designers have moved over to hardware description languages (HDLs) for design entry. Some will prefer a mixture of the two techniques. Schematic-based design-capture tools gave designers a great deal of control over the physical placement and partitioning of logic on the device. But its becoming less likely that designers will take that route. Mean while, language-based design entry is faster, but often at the expense of performance or density.For many designers, the choice of whether to use schematic-or HDL-based designentry comes down to their conception of their design .For those who think in software or algorithmic-like terms, HDLs are the better choice. HDLs are well suited for highly complex designs, especially when the designer has a good handle on how the logic must be structured. They can also be very useful for designing smaller functions when you havent the time or inclination to work through the actual hardware implementation.8 Generalized Substitution-boxVLSI & FPGAFig 2.3: FPGA Design flowOn the other hand, HDLs represent a level of abstraction that can isolate designers from the details of the hardware implementation. Schematic-based entry gives designers much more visibility in to the hardware. Its a better method for those who are hardware- oriented. The downside of schematic-based entry is that it makes the design more difficult to modify or port to another FPGA.A third option for design entry, state-machine entry, works well for designers who can see their logic design as a series of states that the system control, that can be clearly represented in visual formats. Tool support for finite state-machine entry is limited, though.After design entry, the design is simulate0d at the register-transfer level (RTL). This is the first of several simulation stages, because the design must be simulated at successive levels9 Generalized Substitution-boxVLSI & FPGAof abstraction as it moves down the chain toward physical implementation on the FPGA itself. RTL simulation offers the highest performance in terms of speed. As a result, designers can perform many simulation runs in an effort to refine the logic. At this stage, FPGA development isnt unlike software development. Signals and variables are observed, procedures and functions traced, and breakpoints set. The good news is that its a very fast simulation. But because the design hasnt yet been synthesized to gate level, properties such as timing and resources usage are still unknowns.The next step follows RTL simulation is to convert the RTA representation of the design into a bit-stream file that can be loaded onto the FPGA. The interim step is FPGA synthesis, which translates the VHDL or Verilog code into a device net list format that can be understood by a bit-stream converter.The synthesis process can be broken down into three steps. First step, the HDL code is converted into device net list format. Then the resulting file is converted into device netlist format. Then the resulting file is converted into a hexadecimal bit-stream file, or bit file. This step is necessary to change the list of required devices and interconnects into hexadecimal bits to download to the FPGA. This final step completes the FPGA synthesis procedure by programming the design onto the physical FPGA.Its important to fully constrain designs before synthesis. A constrain file is an input tothe synthesis process just as the RTL code itself. Constrains can be applied globally or to specific portions of the design. The synthesis engine uses these constrain to optimize the netlist. However, its equally important to not over-constrain the design, which will generally result in less than-optimal results from the next step in the implementation process-physical device placement-and interconnect routing.Following synthesis, device implementation begins. After netlist synthesis, the design is automatically converted into the format supported internally by the FPGA vendors place-and-route tools. Design-rule checking and optimization is performed on the incoming netlist and the software partitioning is required to achieve high routing completion and high performance. Increasingly, FPGA designers are turning to floor planning after synthesis and design partitioning. FPGA floor planners work from the netlist hierarchy as defined by the RTL coding. Floor planning can help if area is tight. When possible, its a good idea to place critical logic in separate blocks.10 Generalized Substitution-boxVLSI & FPGAAfter partitioning and floor planning, the placement tool tries to place the logic blocks to achieve efficient routing. The tool monitors routing length and track congestion while placing the blocks. It may also track the absolute path delays to meet the users timing constraints. Overall the process mimics PCB place and route.Functional simulation is performed after synthesis and before physical implementation.This step ensures correct logic functionality. After implementation, theres a final verification step with full timing information. After placement and routing, the logic and routing delays are back-annotated to the gate-level net list for this simulation. At this point, simulation is a much longer process, because timing is also a factor. Often, designers substitute static timing simulation. Static timing analysis calculates the timing of combinational paths between registers and compares it again the designers timing constraints.Once the design is successfully verified and found to meet timing, the final step is to actually program the FPGA itself. At the completion of placement and routing, a binary programming file is created. Its used to configure the device. No matter what the devices underlying technology, the FPGA interconnect fabric has cells that configure it to connect to the inputs and outputs of the logic blocks. In turn, the cells configure that logic to each other. Most programmable-logic technologies, including the PROMs for SRAM-based FPGAs, require some sort of a device programmer. Device can also be programmed through their configuration ports using a set of dedicated pins.Modern FPGAs also incorporate a JTAG port that, happily, can be used for more than boundary-scan testing. The JTAG port can be connected to the devices internal SRAM configuration-cell shift registers, which in turn can be instructed to connect to the chips JTAG scan chain. Integrated flows for FPGAs make sure sense in general, considering that FPGA vendors will continue to introduce more complex, powerful, and economical devices over time. An integrated third-party flow makes it easier to re-target a design to different technologies from different vendors as conditions warrant.2.6 GENERALVIEW OF FPGA:FPGAs (Field Programmable Gate Arrays) are semiconductor devices containing programmable logic and programmable interconnects. A FPGA is essentially a hardware processing unit that can be reconfigured at runtime. FPGAs evolved out of the older CPLD11 Generalized Substitution-boxVLSI & FPGA(Complex Programmable Logic Device) chips. Compared to CPLDs, FPGAs typically contain a much higher number of logic cells. Additionally the architecture of FPGAs includes several level embedded function blocks, such as multipliers and block RAMs. This allows FPGAs to implement much more complicated functions than the older CPLDs.The speed of a FPGA is generally slower than that of an equivalent ASIC (ApplicationSpecific Integrated Circuit) chip, however an ASICs functionality and architecture are fixed on manufacture, whereas a FPGA can be reconfigured as necessary. This leads to substantially lower development and manufacturing costs, and also allows the final system a greater degree of flexibility.On a FPGA, algorithms are constructed from blocks of hardware logic, instead of instructions interpreted and executed by a processor. In addition, the architecture of FPGAs allows for the simultaneous, parallel execution of multiple tasks. All these factors mean that certain algorithms can be executed much, much faster on a FPGA than they could on a CPU.1. The General Workflow When Working With FPGAs:1. You use a computer to describe a "logic function" that you want. You might draw aschematic, or create a text file describing the function, doesn't matter.2. You compile the "logic function" on your computer, using softwareprovided by the FPGA vendor. That creates a binary file that can be downloaded into the FPGA.3. You connect a cable from your computer to the FPGA, and download the binary file to the FPGA.That's it! FPGA behaves according to our "logic function".2. It Is Important That:1. You can download FPGAs as many time as you want - no limit - with different functionalities every time if you want. If you make a mistake in your design, just fix your "logic function", re-compile and re-download it. No PCB, solder or component to change. 2. The designs can run much faster than if you were to design a board with discretecomponents, since everything runs within the FPGA, on its silicon die.12 Generalized Substitution-boxVLSI & FPGA3. FPGAsloose their functionality when the power goes away (like RAM in a computer that looses its content). You have to re-download them when power goes back up to restore the functionality.2.7 FPGAS Vs CPLDS:Both are programmable digital logic chips. Both are made by the same companies.But they have different characteristics.1. FPGAs are "fine-grain" devices. That means that they contain a lot (up to 100000) of tiny blocks of logic with flip-flops. CPLDs are "coarse-grain" devices. They contain relatively few (a few 100's max) large blocks of logic with flip-flops.2. FPGAs are RAM based. They need to be "downloaded" (configured) at each power-up. CPLDs are EEPROM based. They are active at power-up (i.e. as long as they've been programmed at least once...).3. FPGAs have special routing resources to implement efficiently binary counters and arithmetic functions (adders, comparators...) and RAM. CPLDs do not.4 FPGAs can contain very large digital designs, while CPLDs can contain small designs only.5. CPLD logic gate densities range from the equivalent of several thousand to tens of thousands of logic gates, while FPGAs typically range from tens of thousands to several million.6. Another notable difference between CPLDs and FPGAs is the presence in most FPGAs of higher-level embedded functions (such as adders and multipliers) and embedded .7 . FPGAs are RAM based.8 . CPLDs are EEPROM based.9. FPGAs can contain very large digital designs, while CPLDs can contain small designs 10.According to the architecture CPLD has less flexibility and FPGA has moreflexibility.13 Generalized Substitution-boxVLSI & FPGACPLDFPGALOGIC ELEMENTSUP TO 500UP TO 2,50,000OPERATING VOLTAGE5V3.3V external, 1.5V internal2.8 HOW FPGAS WORK:1. Internal logic:FPGAs are built from one basic "logic-cell", duplicated hundreds or thousands of time. A logic-cell is composed of a small lookup table, some gates and a D-flipflop. Each logic-cell then can be connected to other logic-cells through interconnect resources (wires/muxes placed around the logic-cells).Each cell can do little, but with so many of them, complex logic functions can be created. The interconnect wires also go to the boundary of the device where I/O cells are implemented and connected to the pins of the FPGAs.2. Dedicated routing/carry chains:In addition to general-purpose interconnect resources; FPGAs have fast dedicated linesin between neighboring logic cells. The most common type of fast dedicated lines are carry chains. Carry chains allow creating arithmetic functions (counters/adders) very efficiently (low logic usage & high operating speed). Older programmable technologies (PAL/CPLD) don't have carry chains and so are quickly limited when arithmetic operations are required.3.Internal Ram:While the first FPGAs didn't have internal memories, all new FPGAs have internalmemories. That increases a lot their scope of applications.14 Generalized Substitution-boxVLSI & FPGAThere are many parameters affecting RAM operation. The main parameter is the number of agents that can access the RAM simultaneously. single-port" RAMs: only one agent can read/write the RAM. "dual-port" or "quad-port" RAMs: 2 or 4 agents can read/write. Great to get data across clock domains (each agent can use a different clock).To figure out how many agents are available, count the number of separate addressbuses going to the RAM. Each agent has a dedicated address bus. Each agent has also a read, a write, or both data buses. Having both data buses doesn't always mean an agent can read and write simultaneously.Writing to the RAM is usually done synchronously. Reading is usually also done synchronously but can also sometimes be done asynchronously. RAM blocks are the usually dedicated memory block ("block rams"). Xilinx has a lot of flexibility in the RAM distribution, because it also allows using the logic-cells as tiny RAMs ("distributed RAM"). Altera usually takes another approach and builds different-size block rams around the device.4. FPGA Power:FPGAs usually require 2 voltages to operate: a "core voltage" and an "IO voltage". Each voltage is provided through separate power pins.1. The internal core voltage (called VCCINT here for simplicity), is used to power the logic gates and flip-flops inside the FPGA. The voltage can range from 5V for older FPGA generations, to 3.3V, 2.5V, 1.8V, 1.5V and even lower for the latest devices! The core voltage is fixed (set by the model of FPGA that you are using).2. The IO voltage (called VCCIO here for simplicity) is used to power the I/O blocks (= pins) of the FPGA. That voltage should match what the other devices connected to the FPGA expect.Actually, FPGA devices themselves don't prevent VCCINT and VCCIO to be the same (i.e. the VCCINT and VCCIO pins could be connected together). But since FPGAs tend to use low-voltage cores, the two voltages are usually different.15 Generalized Substitution-boxVLSI & FPGA5. Applications:Applications of FPGAs include digital signal processing, software-defined radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation and a growing range of other areas.2.9 ADVANTAGES AND DISADVANTAGES OF FPGA:Advantages:1. Most flexible Processor. 2. Easily upgraded.3. Newest technology.4. Low cost and low risk.5. Allow easy design changes. Disadvantages:1. Large and fast devices are expensive.2. These devices are consumes high power.3. Programmable software relatively slow.2.10 HARDWARE DESCRIPTION LANGUAGES:To configure a FPGA, users first provide a description of the desired functional modules in the form of either a schematic, or hardware description language (HDL).This description is then synthesized to produce a binary file used to configure the FPGA device.The advantage of using a hardware description language is that it allows the user to both describe and verify the functioning of a system before it is implemented on hardware. HDLs also allow for the succinct description of concurrent systems, with multiple subcomponents all operating at the same time. This is in contrast to standard programming languages, which are designed to be executed sequentially by a CPU. Using a HDL also allows for a more flexible and16 Generalized Substitution-boxVLSI & FPGApowerful expression of system behavior than simply connecting components together using a schematic.Common HDLs used in FPGA design are VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) and Verilog. VHDL developed from the Ada programming language, and has a relatively verbose syntax. In addition, VHDL is both strongly typed and case insensitive. By contrast, Verilog evolved out of the C programming language, and as such is a much more terse language than VHDL. Verilog is also more weakly typed than VHDL, and is case sensitive. The two languages are highly similar in functionality, and both are widely supported by software synthesis tools.1. Language Features:1. Signal data types (in, out, bidir, signal-strength ..) 2. Hardware structures (memory, register-files ..)3. Logic operators (shift, rotation, masking .)4. Asynchronous structures (set, reset of memories) 5. Parallel or synchronous structures6. Constraints (pin, technology, areas, delays .)7. Inter-process communications (shared medium, message passing )17 Generalized Substitution-boxINTRODUCTION OF VLSICHAPTER 3INTRODUCTION OF VLSIVery-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. The term is no longer as common as it once was, as chips have increased in complexity into the hundreds of millions of transistors.3.1 Overview:The first semiconductor chips held one transistor each. Subsequent advances added more and more transistors, and, as a consequence, more individual functions or systems were integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as "small-scale integration" (SSI), improvements in technique led to devices with hundreds of logic gates, known as large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved far past this mark and today's microprocessors have many millions of gates and hundreds of millions of individual transistors.At one time, there was an effort to name and calibrate various levels of large-scale integration above VLSI. Terms like Ultra-large-scale Integration (ULSI) were used. But the huge number of gates and transistors available on common devices has rendered such fine distinctions moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread use. Even VLSI is now somewhat quaint, given the common assumption that all microprocessors are VLSI or better.As of early 2008, billion-transistor processors are commercially available, an example of which is Intel's Montecito Itanium chip. This is expected to become more21 Generalized Substitution-boxINTRODUCTION OF VLSIcommonplace as experiencing new challenges such as increased variation across process corners). Another notable example is NVIDIAs 280 series GPU.This microprocessor is unique in the fact that its 1.4 Billion transistor count, capable of a teraflop of performance, is almost entirely dedicated to logic (Itanium's transistor count is largely due to the 24MB L3 cache). Current designs, as opposed to the earliest devices, use extensive design automation and automated logic synthesis to lay out the transistors, enabling higher levels of complexity in the resulting logic functionality. Certain high-performance logic blocks like the SRAM cell, however, are still designed by hand to ensure the highest efficiency (sometimes by bending or breaking established design rules to obtain the last bit of performance by trading stability).semiconductor fabrication moves from the current generation of 65 nm processes to the next 45 nm generations (while experiencing new challenges such as increased variation across process corners). Another notable example is NVIDIAs 280 series GPU.This microprocessor is unique in the fact that its 1.4 Billion transistor count, capable of a teraflop of performance, is almost entirely dedicated to logic (Itanium's transistor count is largely due to the 24MB L3 cache). Current designs, as opposed to the earliest devices, use extensive design automation and automated logic synthesis to lay out the transistors, enabling higher levels of complexity in the resulting logic functionality. Certain high-performance logic blocks like the SRAM cell, however, are still designed by hand to ensure the highest efficiency (sometimes by bending or breaking established design rules to obtain the last bit of performance by trading stability).3.2 What is VLSI?VLSI stands for "Very Large Scale Integration". This is the field which involves packing more and more logic devices into smaller and smaller areas.Simply we say Integrated circuit is many transistors on one chip.Design/manufacturing of extremely small, complex circuitry using modifiedsemiconductor materialIntegrated circuit (IC) may contain millions of transistors, each a few mm insize22 Generalized Substitution-boxINTRODUCTION OF VLSIApplications wide ranging: most electronic logic devices3.3 History of Scale Integrationlate 40s Transistor invented at Bell Labslate 50s First IC (JK-FF by Jack Kilby at TI)early 60s Small Scale Integration (SSI)10s of transistors on a chiplate 60s Medium Scale Integration (MSI)100s of transistors on a chipearly 70s Large Scale Integration (LSI)1000s of transistor on a chipearly 80s VLSI 10,000s of transistors on achip (later 100,000s & now 1,000,000s)Ultra LSI is sometimes used for 1,000,000s SSI - Small-Scale Integration (0-102) MSI - Medium-Scale Integration (102-103) LSI - Large-Scale Integration (103-105)VLSI - Very Large-Scale Integration (105-107)ULSI - Ultra Large-Scale Integration (>=107)Advantages of ICs over discrete components:While we will concentrate on integrated circuits , the properties of integrated circuits-what we can and cannot efficiently put in an integrated circuit-largely determine the architecture of the entire system. Integrated circuits improve system characteristics in several critical ways. ICs have three key advantages over digital circuits built from discrete components:Size: Integrated circuits are much smaller-both transistors and wires are shrunk to micrometer sizes, compared to the millimeter or centimeter scales of discrete components. Small size leads to advantages in speed and power consumption, since smaller components have smaller parasitic resistances, capacitances, and inductances.23 Generalized Substitution-boxINTRODUCTION OF VLSISpeed: Signals can be switched between logic 0 and logic 1 much quicker within a chip than they can between chips. Communication within a chip can occur hundreds of times faster than communication between chips on a printed circuit board. The high speed of circuits on-chip is due to their small size-smaller components and wires have smaller parasitic capacitances to slow down the signal.Power consumption: Logic operations within a chip also take much less power.Once again, lower power consumption is largely due to the small size of circuits on the chip-smaller parasitic capacitances and resistances require less power to drive them.3.4 VLSI and systems:These advantages of integrated circuits translate into advantages at the systemlevel:1. Smaller physical size. Smallness is often an advantage in itself-consider portable televisions or handheld cellular telephones.2. Lower power consumption. Replacing a handful of standard parts with a single chip reduces total power consumption. Reducing power consumption has a ripple effect on the rest of the system: a smaller, cheaper power supply can be used; since less power consumption means less heat, a fan may no longer be necessary; a simpler cabinet with less shielding for electromagnetic shielding may be feasible, too.3. Reduced cost: Reducing the number of components, the power supply requirements, cabinet costs, and so on, will inevitably reduce system cost. The ripple effect of integration is such that the cost of a system built from custom ICs can be less, even though the individual ICs cost more than the standard parts they replace. Understanding why integrated circuit technology has such profound influence on the design of digital systems requires understanding both the technology of IC manufacturing and the economics of ICs and digital systems.3.5 Applications:Applications of VLSI24 Generalized Substitution-boxINTRODUCTION OF VLSIElectronic systems now perform a wide variety of tasks in daily life. Electronic systems in some cases have replaced mechanisms that operated mechanically, hydraulically, or by other means; electronics are usually smaller, more flexible, and easier to service. In other cases electronic systems have created totally new applications. Electronic systems perform a variety of tasks, some of them visible, some more hidden:1.Personal entertainment systems such as portable MP3 players and DVD playersperform sophisticated algorithms with remarkably little energy.2.Electronic systems in cars operate stereo systems and displays; they also control fuel injection systems, adjust suspensions to varying terrain, and perform the control functions required for anti-lock braking (ABS) system.3.Digital electronics compress and decompress video, even at high-definition data rates, on-the-fly in consumer electronics.4.Low-cost terminals for Web browsing still require sophisticated electronics,despite their dedicated function.5.Personal computers and workstations provide word-processing, financialanalysis, and games. Computers include both central processing units (CPUs) and special-purpose hardware for disk access, faster screen display, etc.6.Medical electronic systems measure bodily functions and perform complexprocessing algorithms to warn about unusual conditions. The availability of these complex systems, far from overwhelming consumers, only creates demand for even more complex systems.The growing sophistication of applications continually pushes the design and manufacturing of integrated circuits and electronic systems to new levels of complexity. And perhaps the most amazing characteristic of this collection of systems is its variety-as systems become more complex, we build not a few general-purpose computers but an ever wider range of special-purpose systems. Our ability to do so is a testament to our growing mastery of both integrated circuit manufacturing and design, but the increasing demands of customers continue to test the limits of design and manufacturing25 Generalized Substitution-boxVHDLCHAPTER 4VHDL4.1 VHDLVHDL is an acronym for Very High Speed Integrated Circuits Hardwaredescription Language. The language can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. The complexity of the digital system being modeled could vary from that of a simple gate to a complete digital electronic system. The VHDL language can be regarded as an integrated amalgamation of sequential, concurrent, net list and waveform generation languages and timing specifications.History of VHDLVHDL stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language. It was developed in the 1980s as spin-off of a high-speed integrated circuit research project funded by the US department of defense. During the VHSIC program, researchers were confronted with the daunting task of describing circuits of enormous scale (for their time) and of managing very large circuit design problems that involved multiple teams of engineers. With only gate-level tools available, it soon became clear that more structured design methods and tools would be needed.To meet this challenge, teams of engineers from three companies - IBM, Texas Instruments and Inter metrics were contracted by the department of defense to complete the specification and implementation of a new language based design description method. The first publicly available version of VHDL, version 7.2 was released in 1985. In 1986, the IEEE was presented with a proposal to standardize the language, which it did in 1987 and academic representatives. The resulting standard, IEEE 10761987 is the basis for virtually every simulation and synthesis product sold today. An enhanced and updated version of the language, IEEE 1076-1993, was released in 1994, and VHDL tool vendors have been responding by adding these new language features to their products.28 Generalized Substitution-boxVHDLAlthough IEEE standard 1076 defines the complete VHDL language, there are aspects of the language that make it difficult to write completely portable design descriptions (description that can be simulated identically using different vendors tools). The problem stems from the fact that VHDL supports many abstract data types, but it does not address the simple problem of characterizing different signal strengths or commonly used simulation conditions such as unknowns and high impedances. Soon after IEEE 1076-1987 [3] was adopted, simulator companies began enhancing VHDL with new non-standard types to allow their customers to accurately simulate complex electronics circuits. This caused problems because design descriptions entered into one simulator were often incompatible with another with other environments. VHDL was quickly becoming a non-standard.To get around the problem of non-standard data types, an IEEE committee adopted another standard. This standard numbered 1164, defines a standard package (a VHDL feature that allows commonly used declaration to be collected into an external library) containing definition for a standard nine-value data type. This standard data type is called standard logic, and the IELL 1164 package is often referred to as the standard logic package.The IEEN 1076-1987 and IEEE 1164 standards together form the complete VHDL standard in widest use today (IEEE 1076-1993 is slowly working its way into the VHDL mainstream, but it does not add significant number of features for synthesis users).In the search for a standard design and documentation tool for the Very HighSpeed Integrated Circuits (VHSIC) program the United States Department of Defense (DOD) in the summer of 1981 sponsored a workshop on HDLs at Woods Hole, Massachusetts. The conclusion of the workshop was the need for a standard language, and the features that might be required by such a standard in 1983.DoD established requirements for a standard VHSIC hardware description language(VHDL), based on the recommendation of the Woods Hole workshop. A contract for the development of the VHDL language, its environment, and its software was awarded to IBM, Texas instruments and Inter metrics. VHDL 2.0 was released only six months after the project began. The language was significantly improved hereafter and other shortcomings were29 Generalized Substitution-boxVHDLcorrected leading to the release of VHDL 6.0. In 1985 this significant developments led to the release of VHDL 6.0. In 1985 these significant development led to the release of VHDL 7.2 language reference manual. This was later on developed as IEEE 1076/A VHDL language reference manual.Efforts for defining the new version of VHDL stated in 1990 by a ream ofvolunteers working under the IEEE DASC (Design Automation Standards committee). In October of 1992, a new VHDL93 was completed and was released for review. After minor modifications, this new version was approved by the VHDL balloting group members and became the new VHDL language standard. The present VHDL standard is formally referred as VHDL 1076-1993.4.2 Levels of abstraction (Styles)VHDL supports many possible styles of design description. These stylesdiffer primarily in how closely they relate to the underlying hardware. When we speak of the different styles of VHDL, then, we are really talking about the differing levels of abstraction possible using the language. To give an example, it is possible to describe a counter circuit in a number of ways. At the lowest level of abstraction, you could use VHDL's hierarchy features to connect a sequence of predefined logic gates and flip-flips to form a counter circuit.Fig. 4.1 Levels of abstraction30 Generalized Substitution-boxVHDLIn a behavioral description, the concept of time may be expressed precisely,with actual delays between related events, or may simply be an ordering of operations that are expressed sequentially. When you are writing VHDL for input to synthesis tools, you may use behavioral statements in VHDL to imply that there are registers in your circuit. It is unlikely, however, that your synthesis tool will be capable of creating precisely the same behavior in actual circuitry as you have defined in the language.The highest level of abstraction supported in VHDL is called the behaviorallevel of abstraction. When creating a behavioral description of a circuit, you will describe your circuit in terms of its operation over time. The concept of time is the critical distinction between behavioral descriptions of circuits and lower-level descriptions.If you are familiar with event-driven software programming languages then writing behavior level VHDL will not seem like anything new. Just like a programming language, you will be writing one or more small programs that operate sequentially and communicate with one another through their interfaces. The only difference between behavior-level VHDL and a software programming language such as Visual Basic is the underlying execution platform: in the case of Visual Basic, it is the Windows operating system; in the case of VHDL, it is a simulator.An alternate design method, in which a circuit design problem is segmented intoregisters and combinational input logic, is what is often called the dataflow level of abstraction. Dataflow is an intermediate level of abstraction that allows the drudgery of combinational logic to be hidden while the more important parts of the circuit, the registers, are more completely specified.There are some drawbacks to using a purely dataflow method of design inVHDL. First, there are no built-in registers in VHDL; the language was designed to be general-purpose, and VHDLs designers on its behavioral aspects placed the emphasis. If you are going to write VHDL at the dataflow level of abstraction, then you must first create behavioral descriptions of the register elements that you will be using in your31 Generalized Substitution-boxVHDLdesign. These elements must be provided in the form of components or in the form of subprograms.But for hardware designers, for whom it can be difficult to relate the sequentialdescriptions and operation of behavioral VHDL with the hardware that is being described, using the dataflow level of abstraction can make quite a lot of sense. Using dataflow, it can be easier to relate a design description to actual hardware devices. The dataflow and behavior levels of abstraction are used to describe circuits in terms of their logical function. There is a third style of VHDL that is used to combine such descriptions together into a larger, hierarchical circuit description. Structural VHDL allows you to encapsulate one part of a design description as a re-usable component. Structural VHDL can be thought of as being analogous to a textual schematic, or as a textual block diagram for higher-level design.4.3 Need for VHDLThe complex and laborious manual procedures for the design of the hardware paved the way for the development of languages for high level description of the digital system. This high-level description can serve as documentation for the part aswell as an entry point into the design process. The high level description can beprocessed through various boards, or gate array using the synthesis tools of Hardware Description language us such a language. VHDL was designed as a solution to provide an integrated design and documentation to communicate design data between various levels of abstractions.4.4 Advantages of VHDLVHDL allows quick description and synthesis of circuits of 5, 10, 20 thousandgates. It also provides the following capabilities. The following are the major advantages of VHDL over other hardware description languages:Power and flexibility :VHDL has powerful language constructs which allows code description of complex control logic.32 Generalized Substitution-boxVHDLDevice independent design: VHDL creates design that fits into many device architecture and it also permits multiple styles of design description.Portability :VHDLs portability permits the design description to be used on different simulators and synthesis tools. Thus VHDL design descriptions can be used in multiple projects.ASIC migration: The efficiency of VHDL allows design to be synthesized on a CPLDor an FPGA. Sometimes the code can be used with the ASIC.Quick time to market and low cost: VHDL and programmable logic pair togetherfacilitate speedy design process. VHDL permits designs to be described quickly. TheProgrammable logic eliminates expenses and facilitates quick design iterations.1. The language can be used as a communication medium between different Computer Aided Design (CAD) and Computer Aided Engineering (CAE) tools.2. The language supports hierarchy, i.e., a digital system can be modeled as a set ofinterconnected components; each component, in turn, can be modeled as a set of interconnected subcomponents.3. The language supports flexible design methodologies: Top-Down, Bottom- Up, or Mixed.4. The language is technology independent and hence the same behavior model can besynthesized into different vendor libraries.5. Various digital modeling techniques such as finite-state machine descriptions, algorithmic descriptions and Boolean equations can be modeled using the language.6. It supports both synchronous and asynchronous timing models.7. It is an IEEE and ANSI standard, and therefore, models described using these languages are portable.8. There are no limitations that are imposed by the language on the size of the design.33 Generalized Substitution-boxVHDL9. The language has elements that make large-scale design modeling easier, for e.g. Components, functions, procedures and packages.10. Test benches can be written using the same language to test other VHDL models.11. Nominal propagation delays, min-max delays, setup and holding timing, timingconstraints, and spike detection can all be described very naturally in this language.12. Behavioral models that conform to a certain synthesis description style are capableof being synthesized to gate-level description.13. The capability of defining new data types provides the power to describe and simulate a new design technique at a very high level of abstraction without any concern about implementation details.4.5 Design methodology using VHDL: There are three design methodologies namely: bottom-up, top-down and flat1. The bottom-up approach involves the defining and designing the individual components, then bringing the individual components together to form the overall design.2. In a flat design the functional components are defined at the same level as theinterconnection of those functional components.3. A top-down design process involves a divide-and-conquer approach to implementthe design a large system. Top-down design is referred to as recursive partitioning of a system into its sub-components until all sub-components become manageable design parts. Design of a component is manageable if the component is available as part of a library, it can be implemented by modifying an already available part, or it can be described for a synthesis program or an automatic hardware generator.4.6 Elements of VHDL:This functionality depends on input-output signals and other parameters that arespecified in the interface description. Several architectural specifications with different34 Generalized Substitution-boxVHDLidentifiers can exist for one component with a given interface description. VHDL allows architecture to be configured for a specific technology environment.In a hardware design environment it becomes necessary to group componentsor utilities used for description of components. Components and such utilities can be grouped by use of packages. A package declaration contains components and utilities to become visible by Entities and Architectures. VHDL allows the use of Libraries and binding of sub-components of a design to elements of various libraries. Constructs for such applications include a library statement and configurations.4.7 VHDL language features:The various building blocks and constructs in VHDL which have been usedare:4.1.7.1 Entity:Every VHDL design description consists of at least one entity. In VHDL, anentity declaration describes the circuit as it appears from the "outside", from the perspective of its input and output interfaces.An entity declaration in VHDL provides the complete interface for a circuit.Using the information provided in an entity declaration (the port names and the data type and direction of each port), you have all the information you need to connect that portion of a circuit into other, higher-level circuits.The entity declaration includes a name, compare, and a port statement defining all the inputs and outputs of the entity. Each of the ports is given a direction (either in, out or inout).Formal Definition:It is the hardware abstraction of a digital system. Entity declaration describesthe external view of the entity to the outside world.Simplified syntax:35 Generalized Substitution-boxVHDLEntity entity-name isPort (port-list);[generic(generic-list);]end entity-name;Description:All designs are expressed in terms of entities. Entity is the most basic buildingblock in a design. The uppermost level of the design is the top-level entity. If the designis hierarchical, then the top-level description will have lower-level descriptions containedin it. These lower-level descriptions will be lower-level entities contained in the top-levelentity description.4.1.7.2 Architecture:Every entity in a VHDL design description must be bound with a correspondingarchitecture. The architecture describes the actual function of the entity to which it is bound. Using the schematic as a metaphor, you can think of the architecture as being roughly analogous to a lower-level schematic pointed to by the higher-level functional block symbol.The second part of a minimal VHDL source file is the architecture declaration.Every entity declaration you write must be accompanied by at least one corresponding architecture.The architecture declaration begins with a unique name, followed by the name of the entity to which the architecture is bound. Within the architecture declaration is found the actual functional description of our comparator. There are many ways to describe combinational logic functions in VHDL.Formal Definition:A body associated with an entity declaration to describe the internal organization36 Generalized Substitution-boxVHDLor operation of a design entity. An architecture body is used to describe the behavior,dataflow or structure of design entity.Simplified syntax:Architecture architecture-name of entity-name isArchitecture-declarationsBeginConcurrent-statementsEnd [architecture] [architecture-name];Description:Architecture assigned to an entity describes internal relationship between input and output ports of the entity. It contains of two parts: declarations and concurrent statements. First (declarative) part of architecture may contain declarations of types, signals, constants, subprograms (functions and procedures), components and groups. Concurrent statements in the architecture body define the relationship between inputs and outputs. This relationship can be specified using different types of statements: Concurrent signal assignment, process statement, component instantiation, and concurrent procedure call, generate statement, concurrent assertion statement, and block statement. It can be writing in different styles: structural, dataflow, behavioral (functional) or mixed.The description of a structural body is based on component instantiation andgenerates statements. It allows creating hierarchical projects, from simple gates to very complex components, describing entire subsystems.The Connections among components are realized through ports. The Dataflow description is built with concurrent signal assignment statements: Each of the statements can be activated when any of its input signals changes its value.The architecture body describes only the expected functionality (behavior) of the circuit, without any direct indication as to the hard ware implementation. Such37 Generalized Substitution-boxVHDLdescription consists only of one or more processes, each of which contains sequential statements. The Architecture body may contain statements that define both behavior and structure of the circuit at the same time. Such architecture description is called mixed.4.1.7.3 Component declaration:Formal Definition:A component declaration declares a virtual design entity interface that may beused in component instantiation statement.Simplified syntax:Component component-name[generic(generic-list)];port(port-list);end component [component-name];4.1.7.4 Component instantiation:Formal Definition:A component instantiation statement defines a subcomponent of the design entityin which it appears, associate signals or values with the ports of that subcomponent, andassociates values with generics of that subcomponent.Simplified syntax:Label: [component] component-nameGeneric map (generic-association-list);Port map (port-association-list);4.1.7.5 Configuration declaration:38 Generalized Substitution-boxVHDLFormal Definition:A configuration is a construct that defines how component instances in a given block are bound to design entities in order to describe how design entities are put together to form a complete design.Simplified syntax:Configuration configuration-name of entity-name isConfiguration declarations.For architecture-nameFor instance-label: component-nameUse entity library-name. Entity-name (arch-name);End for;end for;end configuration-name;4.1.7.6 Configuration instantiation:Formal Definition:A component instantiation statement defines a subcomponent of the designentity in which it appears, associates signals or value with the ports of thatsubcomponent, and associates values with generics of that subcomponent.Simplified syntax:Label: Configuration configuration-nameGeneric map (generic-association-list);Port map (port-association-list);39 Generalized Substitution-boxVHDL4.1.7.7 Package:Formal Definition:A package declaration defines the interface to a package.Simplified syntax:Package package-name isPackage declarationsEnd [package] package-name;Package body:A package body defines the bodies of subprograms and the values of deferredconstants declared in the interface to the package.Simplified syntax:Package body package-name isPackage-body-declarationsSubprogram bodies declarationsEnd [package body] package-name;4.1.7.8 Attributes:Attributes are of two types: user defined and predefined.User definedFormal Definition:A value, function, type, range, signals, or constant that may be associated withone or more named entities in a description.40 Generalized Substitution-boxVHDLSimplified syntax:Attribute attribute-name: type--attribute declarationAttribute attribute-name of item: item-class is expressionattribute specificationDescription:Attributes allow retrieving information about named entities: types, objects,subprograms etc. Users can define mew attributes and then assign them to named entitiesby specifying the entity and the attribute values for it.Formal Definition:A value, function, type, range, signals, or constant that may be associated withone or more named entities in a description.Simplified syntax: objects attribute-name4.1.7.9 Process statement:Formal Definition: A process statement defines an independent sequential process representing the behavior of some portion of the designSimplified syntax:[process-label:] process [(sensitivity-list)];Process-declarationsBeginSequential-statementsend process [process-label];41 Generalized Substitution-boxVHDL4.1.7.10 Function:Formal Definition: A function call is a subprogram of the form of an expression that returns a value.Simplified syntax:Function function name(parameters) return type-- function declarationFunction function-name(parameters) return type is --- function definition.BeginSequential statementsEnd [function] function-name;4.7.11 Port:Formal Definition: A channel for dynamic communication between a block and itsenvironment.Simplified syntax:Port (port-declaration, port-declaration,-----);----port declarations:Port-signal-name: in port-signal-type: =initial-valuePort-signal-name: out port-signal-type: =initial-valuePort-signal-name: in out port-signal-type: =initial-valuePort-signal-name: buffer port-signal-type: =initial-valuePort-signal-name: linkage port-signal-type: =initial-value42 Generalized Substitution-boxVHDL4.1.7.12 Sensitivity list :Formal Definition :A list of signals a process is sensitive to.Simplified syntax:(Signal-name, signal-name, ---)Formal Definition4.1.7.13 Standard logic:Formal Definition:A nine-value resolved logic type.Std-logic is not a part of the VHDL standard. It isdefined in IEEE Std 1164.Simplified syntax:Type std-logic is(U, -- UninitializedX, -- Forcing Unknown0, -- Forcing 01, -- Forcing 1Z -- High ImpedanceW--Weak UnknownL--Weak 1---Dont Care);Type std-logic-vector is array (natural range ) of std-logicFunction resolved (s: std-logic-vector) return std-logic;Subtype std-logic is resolved std-logic;43 Generalized Substitution-boxVHDL4.8 Data Types:There are many data types available in VHDL. VHDL allows data to be represented in terms of high-level data types. These data types can represent individual wires in a circuit, or can represent collections of wires using a concept called an array.The preceding description of the comparator circuit used the data types bit andbit vector for its inputs and outputs. The bit data type (bit vector is simply an array of bits) values of '1' and '0' are the only possible values for the bit data type. Every data type in VHDL has a defined set of values, and a defined set of valid operations. Type checking is strict, so it is not possible, for example, to directly assign the value of an integer data type to a bit vector data type. (There are ways to get around this restriction, using what are called type conversion functions.) VHDL is rich language with many different data types.The most common data types are listed below:Bit: a 1-bit value representing a wire. (Note: IEEE standard 1164 defines a 9-valued replacement for bit called std-logic.)Bit vector: an array of bits. (Replaced by std-logic-vector in IEEE 1164.)Boolean: a True/False value.Integer: a signed integer value, typically implemented as a 32-bit data type.Real: a floating-point value.Enumerated: used to create custom data types.Record: used to append multiple data types as a collection.Array: can be used to create single or multiple dimension arrays.Access: similar to pointers in C or Pascal.File: used to read and write disk files. Useful for simulation.Physical: used to represent values such as time, voltage, etc. using symbolic units ofmeasure (such as 'ns' or 'ma').44 Generalized Substitution-boxVHDL4.9 Packages and Package Bodies:A VHDL package declaration is identified by the package keyword, and is used to collect commonly used declarations for use globally among different design units. You can think of a package as being a common storage area, one used to store such things as type declarations, constants, and global subprograms.A package can consist of two basic parts: a package declaration and an optionalpackage body. Package declarations can contain the following types of statements:Type and subtype declarationsConstant declarationsGlobal signal declarationsFunction and procedure declarationsAttribute specificationsFile declarationsComponent declarationsAlias declarationsDisconnect specificationsUse clausesItems appearing within a package declaration can be made visible to other design units through the use of a use statement.If the package contains declarations of subprograms (functions or procedures) or defines one or more deferred constants (constants whose value is not given), then a package body is required in addition to the package declaration. A package body must have the same name as its corresponding package declaration, but can be located anywhere in the design. The relationship between a package and package body is45 Generalized Substitution-boxVHDLsomewhat akin to the relationship between an entity and its corresponding architecture. While the package declaration provides the information needed to use the items defined within it (the parameter list for a global procedure, or the name of a defined type or subtype), the behavior of such things as procedures and functions must be specified within package bodies.46 Generalized Substitution-boxCHAPTER 5 VERILOG HDLCHAPTER 5VERILOG HDLVerilog HDL is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic-level to the gate-level to the switch-level. The complexity of the digital system being modeled could vary from that of a simple gate to a complete electronic digital system, or anything in between. The digital system can be described hierarchically and timing can be explicitly modeled within the same description.The Verilog HDL language includes capabilities to describe the behavioral nature of a design, the dataflow nature of a design, a design's structural composition, delays and a waveform generation mechanism including aspects of response monitoring and verification, all modeled using one single language. In addition, the language provides a programming language interface through which the internals of a design can be accessed during simulation including the control of a simulation run.The language not only defines the syntax but also defines very clear simulationsemantics for each language construct. Therefore, models written in this language can be verified using a Verilog simulator. The language inherits many of its operator symbols and constructs from the C programming language. Verilog HDL provides an extensive range of modeling capabilities, some of which are quite difficult to comprehend initially. However, a core subset of the language is quite easy to leam and use. This is sufficient to model most applications.5.1 History:The verilog HDL language was first developed by Gateway Design Automationin 1983 as hardware are modeling language for their simulator product, At that time ,it was a proprietary language. Because of the popularity of the,simulator product, Verilog HDL gained acceptance as a usable and practical language by a number of designers. In an effort to increase the popularity of the language, the language was placed in the public47 Generalized Substitution-boxCHAPTER 5 VERILOG HDLdomain in 1990. Open verilog International (OVI) was formed to promote Verilog. In 1992 OVI decided to pursue standardization of verilog HDL as an IEEE standard. This effort was successful and the language became an IEEE standard in 1995. The complete standard is described in the verilog hardware description language reference manual. The standard is called std 1364-1995.5.2 Major Capabilities: Listed below are the major capabilities of the Verilog hardware description:1. Primitive logic gates, such as and, or and nand, are built-in into the language.2. Flexibility of creating a user-defined primitive (UDP). Such a primitive could either be a combinational logic primitive or a sequential logic primitive.3. Switch-level modeling primitive gates, such as pmos and nmos, are also built-in into the language.4. Explicit language constructs are provided for specifying pin-to-pin delays, path delays and timing checks of a design.5. A design can be modeled in three different styles or in a mixed style. These styles are: behavioral style - modeled using procedural constructs; dataflow style - modeled using continuous assignments; and structural style - modeled using gate and module instantiations.There are two data types in Verilog HDL; the net data type and the register data type. The net type represents a physical connection between structural elements while a register type represents an abstract data storage element.Figure.5.1 shows the mixed-level modeling capability of Verilog HDL, that is, in one design, each module may be modeled at a different level.48 Generalized Substitution-boxCHAPTER 5 VERILOG HDLFig 5.1 Mixed Level Modeling1. Verilog HDL also has built-in logic functions such as & (bitwise-and) and I (bitwise-or).2. High-level programming language constructs such as conditionals, case statements, and loops are available in the language.3. Notion of concurrency and time can be explicitly modeled.4. Powerful file read and write capabilities fare provided.5. The language is non-deterministic under certain situations, that is, a model may produce different results on different simulators; for example, the ordering of events on an event queue is not defined by the standard.49 Generalized Substitution-boxCHAPTER 5 VERILOG HDL5.3 SYNTHESIS:Synthesis is the process of constructing a gate level net list from a register-transfer level model of a circuit described in Verilog HDL. The following figure.5.2 shows such process, synthesis system may as an intermediate step, generate a net list that is comprised of register-transfer level blocks such as flip-flops, arithmetic-logic-units, and multiplexers, interconnected by wires. In such a case, a second program called the RTL module builder is necessary. The purpose of this builder is to build, or acquire from a library of predefined components, each of the required RTL blocks in the user-specified target technologyFigure: 5.2 Synthesis processHaving produced a gate level net list, a logic optimizer reads in the net list andit optimizes the circuit for the user-specified area and timing constraints. These area and timing constraints may also be used by the module builder for appropriate selection or generation of RTL blocks. In this book, we assume that the target net list is at the gate level. The logic gates used in the synthesized net lists are described in Appendix B.The module building and logic optimization phases are not described in this book.The above figure shows the basic elements of Verilog HDL and the elementsused in hardware. A mapping mechanism or a construction mechanism has to be provided50 Generalized Substitution-boxCHAPTER 5 VERILOG HDLthat translates the Verilog HDL elements into their corresponding hardware elements as shown in figure: 5.3Fig: 5.3 Typical design process51 Generalized Substitution-boxCHAPTER 5 VERILOG HDL52 Generalized Substitution-boxS-BOXCHAPTER 6 S-BOX6.1 Cryptography:Cryptography (or cryptology; from Greek krypts, "hidden, secret";and graphein, "writing", or - -logia, "study", respectively) is the practice and study of techniques for secure communication in the presence of the third parties (called adversaries). More generally, it is about constructing and analyzing the protocols that overcome the influence of adversaries and which are related to various aspects in information security such as data confidentiality, data integrity, authentication and non-repudiation. Modern cryptography intersects the disciplines of mathematics and computer science,electrical engineering. Applications of cryptography include ATMcards computer passwords, and electronic commerce.Cryptography prior to the modern age was effectively synonymous with encryption ,the conversion of information from a readable state to apparent nonsense.The originator of an encrypted message shared the decoding technique needed to recover the original information only with intended recipients, thereby precluding unwanted persons to do the same. Since World War-I and the advent of the computer , the methods used to carry out cryptology have become increasingly complex and its application more wide.Modern cryptography is heavily based on the mathematical theory and computer science practice; cryptographic algorithms are designed around computational hardness assumptions,making such algorithms hard to break in practice by any adversary. It is theoretically possible to break such a system,but it is infeasible to do so by any of the known practical means.These schemes are therefore termed computationally secure ;more theoretical advances ,e.g., improvements in integer factorization algorithms, and faster computing technology require these solutions to be continually adapted. There exists an information-theoretically secure schemes that provably cannot be broken even with the unlimited computing power an example is the one-time pad but these schemes are more difficult to implement than the best theoretically breakable but computationally even secure mechanisms.Cryptology related technology has raised a number of legal issues.In the United Kingdom, addition to the Regulation of Investigatory Powers Act 2000 require a suspected criminal to hand over his or her decryption key if asked by law enforcement . Otherwise the user will face a criminal charge. The Electronic Frontier Foundation (EFF) was involved in a case in the United States which questioned whether requiring the need for suspected criminals to provide their decryption keys to law enforcement is against the law. The EFF argued that this is a violation of the right of not being forced to incriminate52oneself, as given in the fifth amendment. Symmetric-key cryptography refers to the encryption methods in which both the sender and receiver share the same key( or, less commonly, in which their keys are different, but related in an easily computable way). This was the only kind of encryption publicly known until June 1976.One round (out of 8.5) of the patented IDEA cipher, used in some versions of PGP for high-speed encryption of, for instance, e-mail.Symmetric key ciphers are implemented as either block ciphers or stream ciphers. A block cipher enciphers input in blocks of plaintext as opposed to individual characters, the input form used by a stream cipher.The Data Encryption Standard (DES) andthe Advanced Encryption Standard (AES) are block cipher designs which have been designated cryptography standards by the US government(though DES's designation was finally withdrawn the AES was adopted).Despite its deprecation as an official standard, DES (especially its still-approved and much more secure triple-DES variant) remains quite popular; it used across a wide range of applications, from ATM encryption to e-mail privacy and also to secure remote access. Many other block ciphers have been designed and released, with considerable variation in quality. Many have been thoroughly broken, such as FEAL.Stream ciphers, in contrast to the 'block' type, create an arbitrarily a long stream of key material, which is combined with the plaintext bit-by-bit or character-by-character, somewhat like the one- time pad. In a stream cipher, the output stream is created based on a hidden internal state which changes as the cipher operates. That an internal state is initially set up using the secret key material. RC4 is a widely used the stream cipher; see Category: Stream ciphers. Block ciphers can be used as the stream ciphers; see Block cipher modes of operation.53S-BOXCryptographic hash functions are a third type of cryptographic algorithm. They take a message of any length as input, and output a short, fixed length hash which can be used in (for example) a digital signature. For good hash functions, an attacker cannot find two messages that produce the same hash. MD4 is a longused hash function which is now broken ; MD5, a strengthened variant of MD4, is also widely used but it broken in practice. The U.S. National Security Agency(NSA) developedthe Secure Hash Algorithm series of MD5-like hash functions: SHA-0 was a flawed algorithm, the agency withdrew ; SHA-1 is widely deployed and more secure than MD5, cryptanalysts have identified attacks against it; the SHA-2 family improves on SHA-1, but it isn't yet widely deployed, and the U.S. standards authority thought it "prudent" from a security perspective to develop a new standard to "significantly improve the robustness of NIST's overall hash algorithm toolkit." Thus, a hash function design competition was meant to select a new U.S. national standard, to be called SHA-3, by 2012. The competition ended on October 2, 2012 when the NIST announced that Keccak would be the new SHA-3 hash algorithm.Message authentication codes (MACs) are much like cryptographic hash functions,except that a secret key can be used to authenticate the hash value upon receipt.Main article: Public-key cryptographyPublic-key cryptography, where different keys are used for encryption and decryptionSymmetric-key cryptosystems use the same key for encryption and decryption of a message, though a message or group of messages may have a different key than others. significant disadvantage of symmetric ciphers is the key management necessary to use them securely. Each distinct pair of communicating parties must ideally, share a different key, and perhaps each cipher text exchanged as well. The number of keys increases as the square of the number of network members, which very quickly requires complex keyGeneralized substitution box54management schemes to keep them all consistent and secret. The difficulty of securely establishing a secret key between two communicating parties, does not already exist in between them, also presents a chicken-and-egg problem which is a considerable practical obstacle for cryptography users in the real world.6.2 Substitution Box:In cryptography, an S-box (substitution-box) is a basic component of the symmetric key algorithms which performs substitution. In block ciphers, they are typically used to obscure the relationship between the key and the cipher text Shannon's property of confusion.In general, an S-box takes some number of input bits,m and transforms them into some number of output bits,n,where n is not equal to m.An mxn S-box can be implemented as a lookup table with 2m words of n bits each. Fixed tables are normally used, as in the Data Encryption Standard (DES), but in some ciphers the tables are generated dynamically from the key (e.g. the Blowfish and the Two fish encryption algorithms)One good example of a fixed table is this 64-bit S-box from DES (S5):Middle 4 bits of inputS5000 000 001 001 010 010 011 011 100 100 101 101 110 110 111 111 01010101010101010 001 110 010 000 011 101 101 011 100 010 001 111 110 000 111 100 0 00011010011110010 111 101 001 110 010 011 110 000 010 000 111 101 001 100 100 011 Out 1 0100011110101100erbits 1 010 001 000 101 101 110 011 100 111 100 110 010 011 001 000 111 0 00110110110101001 101 100 110 011 000 111 001 110 011 111 000 100 101 010 010 001 1 1001100101010011Given a 6-bit input, the 4-bit output is found by selecting the row using the outer two bits (the first and last bits), and the column using the inner four bits. For example, an input "011011" has outer bits "01" and inner bits "1101"; the corresponding output would be "1001".The 8 S-boxes of DES were the subject of intense study for many years out of a concern that a backdoor a vulnerability known only to its designers might have been planted in the cipher. The S-box design criteria were eventually published53S-BOX(in Coppersmith 1994) after the public rediscovery of differential cryptanalysis, showing that they had been carefully tuned to increase resistance against this specific attack. Biham and Shamir found that even small modifications to an S-box could significantly weaken DES.There has been a great deal of research into the design of good S-boxes, and much more is understood about their use in block ciphers than when DES was released.Any S-box where each output bit is produced by a bent function of the input bits, and where any linear combination of the output bits is also a bent function of the input bits, is a perfect S-box,Generalized substitution box54RESULTS AND CONCLUSIONCHAPTER 7RESULTS AND CONCLUSIONResults analysis:Generalized Substitution Box algorithm simulation results are discussed in the below wave forms with the help of an example. These waveforms are observed from the Modelsim.library IEEE;use IEEE.std_logic_1164.all;entity SBOX16x4 is port (SboxEna : in STD_LOGIC;SboxAddr : in STD_LOGIC_VECTOR (3 downto 0); SboxData : out STD_LOGIC_VECTOR (3 downto 0) );end SBOX16x4;architecture SBOX16x4 of SBOX16x4 is beginprocess (SboxEna,SboxAddr) beginif(SboxEna='1')then case SboxAddr iswhen "0000" => SboxData SboxData SboxData SboxData SboxData SboxData SboxData SboxData SboxData SboxData SboxData SboxData SboxData SboxData SboxData SboxData SboxData