GENERAL REQUIREMENTS FOR INTEGRATED · PDF fileESD protection during manufacture Specification...

of 36STACK 0001

Issue 12.2 Notice 2

GENERAL REQUIREMENTS FOR INTEGRATED CIRCUITS

JOINT COMPANY STANDARD

This Specification is issued by:STACK INTERNATIONALwww.stackinternational.com

Tel: +44 (0) 1727 829100Fax: +44 (0) 1727 821542

Copyright 19 November 1999 STACK International.This document may be reproduced with this copyright notice

GENERAL REQUIREMENTS of 36FOR STACK 0001

INTEGRATED CIRCUITS Issue 12.2 Notice 2

INTRODUCTION......................... Section 1Purpose and scopeUse of equivalent testsLiaisonOrder of precedenceTranslationCompliance with internal company standards

REFERENCED STANDARDS................. 2

TERMS AND DEFINITIONS ................... 3

ADMINISTRATION .................................. 4RegistrationSuspension of registrationAcceptance permit/ConcessionUpdates to this specificationWaivers

PROCEDURES ........................................ 5Product discontinuationESD protection during manufactureSpecification controlInternal quality auditSubcontract manufacturingTraceability

CHANGE NOTIFICATION (PCN) ........... 6

SHIPMENT CONTROLS ......................... 7Date code remarkingInner box formationDate code age on delivery

ELECTRICAL .......................................... 8Operating conditionsElectrical test

CONTENTS

MECHANICAL ............................Section 9Package dimensionsDevice markingMoisture sensitivityRobustness of hermetic sealsLead (termination) finishes

SHIP TO STOCK ...................................10

QUALITY ASSURANCE ....................... 11Quality systemSampling plansFailure analysis supportOutgoing quality

INCOMING INSPECTION ..................... 12Lot acceptanceSuspension of deliveriesLoss of approvalAQL/LTPD figures100% screeningIncoming test schedule ...................Table 3

QUALIFICATION....................................13PurposeSamplesReferencesIn process test resultsProduct monitor resultsMaintenance of qualification standardPre qualification questionnaireTechnology verificationArchivingQualification test schedule..............Table 4

QUALIFICATION OF CHANGES ..........14

SIMILARITY ASSESSMENT ............... 15

RELIABILITY............................Section 16Operating reliabilityFailure criteriaCorrective actionData accumulationSuspension of qualification approvalTable 6 operating life failure rates

PRODUCT MONITOR ........................... 17Monitor programProblem alertData reportingSamplesProduction maturity factorsDevice dissipationCorrective actionSuspension of qualification approvalAccumulated test dataTable 7 product monitor tests

ENVIRONMENTAL .............................. 18Self ignitionToxic materialsEnvironmental regulation compliance

SHIPMENT PACKAGING ..................... 19GeneralElectrostatic propertiesMagazine reuseTubesTrays

LABELS................................................. 20GeneralDry packOuter boxInner box

TEST CODE INFORMATION................ 21

DOCUMENT REVISION HISTORY ...... 22



1. INTRODUCTION

1.1 Purpose and Scope: This specification defines user quality, reliability and generalrequirements for integrated circuits .

1.2 Use of equivalent tests: To comply with the requirements of this specification, the suppliershall perform the tests as specified. Other test methods may be used, provided an adequate anddocumented technical assessment has been performed, which shows the specified testrequirement is being met. The technical assessment shall be supplied on request. The userreserves the right to reject on failure using the test as specified.

1.3 Liaison: Enquiries relating to this specification which concern product deliveries or ordersshall be addressed to the user. Enquiries relating to registration should be addressed to StackInternational, Tyttenhanger House, Coursers Road, Colney Heath, St Albans, AL4 0PG ,U.K. Tel: (0)1727 829100, Fax: (0)1727 821542.

1.4 Order of precedence: In case of conflict the following order of precedence shall apply:

a) The purchase document.b) The individual device specification.c) This specification.d) Any referenced documents.e) The data sheet.

1.5 Translation: If translated into other languages the English language version of thisspecification shall govern.

1.6 Compliance with internal standards: This document does not relieve the supplier of theirresponsibility to meet their own company internal requirements.



2. REFERENCED STANDARDS:

2.1 Unless otherwise specified the following documents form a part of this specification to theextent specified herein. Where no particular document revision is given the latest revision shallbe used.

EN100015-3 Protection of electrostatic sensitive devices in clean room environments.EIA 554 Assessment of outgoing nonconforming levels in parts per million.EIA 541 Packaging materials for ESD senstive items.EIA 556 Outer shipping container bar code label standard.EIA625 Requirements for handling electrostatic discharge sensitive (ESDS) devices.IEC 695-2-2 Fire hazard testing - Needle flame test.JESD22-A101 Steady state temperature humidity bias life test.JESD22-A102 Accelerated moisture resistance unbiased autoclave.JESD22-A104 Temperature cycling.JESD22-A106 Thermal shock.JESD22-A108 Bias life.JESD22-A110 Highly accelerated temperature and humidity stress test (HAST).JESD22-A112 Moisture induced stress sensitivity for plastic surface mount devices.JESD22-A113 Preconditioning of plastic surface mount devices prior to reliability testing.JESD22-A114 Electrostatic discharge (ESD) sensitivity tesing human body model (HBM).JESD22-B100 Physical Dimensions.JESD22-B102 Solderability test method.JESD22-B103 Vibration, variable frequency.JESD22-B104 Mechanical shock.JESD22-B107 Marking permanency.JESD46 Guidelines for user notification of Product/Process changes by Semiconductor

Suppliers.JESD47 Stress test driven qualification of integrated circuits.JESD78 IC Latchup test.J-Std-004 Requirements for soldering fluxes.J-Std-020 Moisture/reflow sensitivity classification for non hermetic solid state surface

mount devicesMil-Std-883 Test methods and procedures for microelectronics.Mil-Std-1189 Standard DOD bar code symbology.UL94 V0 Flammability of plastic materials.Mil-F-14256 Flux soldering liquid (rosin base).



3. TERMS AND DEFINITIONS

3.1 For the purposes of this specification, when the following terms are used in italics , they havethe meaning defined in this section:

Acceptance Permit User agreement to allow the delivery of a shipping lot which/concession: does not fully meet the requirements of this specification.Data Sheet: A device specification written by the device manufacturer.Device: Any integrated circuit to which this specification is applied.Device Specification: A device specification written by a user and agreed by the supplier.DPM: Defect per million.

Form/Fit/Function As defined in JESD46 ie:Form Visual appearance including color, marking and surface finish.Fit External dimensions and associated tolerances.Function Electrical, mechanical, thermal, quality, and reliability performance

characteristics.Incoming Lot: One or more shipments of a device, grouped together for the purpose of

incoming inspection, but including no more than the number ofshipments received in one week.

Inner Box: A box or bag containing devices in magazines.LTPD: Lot tolerance percent defective.Manufacturing Lot: A definite quantity of devices tracked at each manufacturing operation.

It is associated with a travel log and constitutes a group, homogeneouslyprocessed through all manufacturing operations under uniformmanufacturing conditions.

Magazine: Sticks, tubes, matrix trays, tape/reel etc.Outer Box: An outer shipping container, containing one or more inner boxes.Shipping Lot: A single lot of one or more outer boxes received by a user.PQQ: Pre qualification questionnaire.PPM: Parts per million.Room Temperature: 25oC ± 5oCSpecification: This specification together with all other documents referred to as

forming part thereof.

Supplier: The company identified by the logo, or name marked on the device.Topmin: Minimum operating temperature.Topmax: Maximum operating temperature.Triboelectric Charge: An electrical charge generated by frictional movement or separation of

two surfaces.User: A component purchaser requiring compliance to this specification.Waiver: A written notice that a requirement of this specification no longer applies

or is relaxed.



4. ADMINISTRATION

4.1 Registration: Registration is a formal supplier declaration that the suppliers standardqualification procedure, product monitor program and manufacturing processes are incompliance with this specification and that the other requirements of this specification are metwhen this specification is invoked by user documentation.

4.2 Suspension of registration: If it is determined that a registered supplier is not fully compliantwith this specification, and if after due discussion agreement cannot be reached to resolve theproblem, then registration may be suspended until the non compliance is corrected or acorrective action plan has been agreed.

4.3 Acceptance permits/Concessions:

a) In the event of the supplier wishing to ship devices which deviate from the requirements ofthe purchase order, relevant specifications, or this specification, prior consent must beobtained from the user.

b) Applications for such concessions must contain the following information:- Purchase Order Number.- Description of items.- Supplier type number.- User part number.- Quantities or time period affected.- Description of deviation(s).- Cause of deviations.- Reason for requesting acceptance.- Corrective measures being taken to overcome the deviation on subsequent deliveries.

c) Devices subject to application for a concession shall be held at the supplier's premisespending reply unless otherwise instructed by the user.

4.4 Updates to this specification: Updates to this specification will be circulated to all STACKregistered suppliers. A period of time will be defined at each release date depending on theextent of the change to allow suppliers to formally accept the new issue.

4.5 Waivers: Any waiver request requires the approval of the STACK membership. If granted thewaiver will stand as a change to this specification and as such is applicable to all suppliers. Waivers to this specification will not be given to individual suppliers.



5. PROCEDURES

5.1 Product discontinuation: The supplier shall provide to the user 12 months notice of last orderdates for single source devices and 6 months for multi sourced devices.

5.2 ESD protection during manufacture:All integrated circuits are considered to be static sensitive and shall be protected through thesupplier's manufacturing operation. Suppliers shall ensure that devices are not exposed to staticdamage and are not degraded or damaged due to static. EN100015-3, and EIA-625 areconsidered suitable standards for ESD precautions in wafer fab and probe.

5.3 Specification control: The supplier shall:

a) Have central or local record of the users part number and specification, against the productto be delivered.

b) Ensure the specifications on the purchase documents have been reviewed and accepted bypersonnel authorized to do so.

5.4 Internal quality audits: The supplier shall periodically audit each internal manufacturinglocation, to assess compliance with internal quality standards. The results of these audits andthe audit acceptance criteria, shall be available for on site inspection during a STACK audit.

5.5 Sub contract manufacturing: The supplier shall qualify and periodically audit all subcontracted operations to a quality standard equivalent to the suppliers internal operations.

5.6 Traceability:

a) The supplier shall have traceability for any device in a shipping lot through device marking(preferred on top surface) or magazine marking or inner box marking to identify themanufacturing route, ie:- groups of wafer lots- wafer fab location- assembly location- test location

b) The route code shall be supplied on request.

c) The procedure shall be available for inspection during audit.



6. PRODUCT OR PROCESS CHANGE NOTIFICATION (PCN)

6.1 Notification: In the event of the supplier proposing a change subsequent to the supply of theinitial qualification samples, then the supplier shall notify the user, in writing, at least 90 daysprior to incorporation in the delivered product. The user will respond within 30 days, to acceptthe change, reject the change or request further information.

6.2 Notification details: The PCN shall include the following items:

a) Title of change.b) Supplier type number(s) affected.c) Supplier notification identification number.d) Estimated last order and shipment dates for unchanged devices to be supplied on request.e) Estimated first shipment date of changed devices.f) Manufacturing location and product line affected.g) A thorough description of the proposed change.h) Means of distinguishing changed devices from unchanged devices. This may be a date code

or date code range.i) Sufficient engineering and/or qualification test data, including details of any qualification test

vehicle used and its applicability to the product change, shall be available on request todemonstrate that the change will not adversely affect device form, fit, function, quality orreliability, and that the changed product will continue to meet the specified requirements.

j) User part number of the affected device (preferred item but not mandatory).

6.3 Notifiable changes:a) Changes which affect device form, fit, function, quality or reliability.b) JESD46 may be used as a guide to changes requiring notificationc) Package dimension changes.d) Notifiable changes to tubes, trays or other magazines shall include:

- Dimensions: Min; Max and typical including wall thickness- Cross sectional shape- Material of construction- Ability to withstand temperature extremes- Electrostatic coating material (if any) and electrostatic performance- Transparency in so far as it affects visibility of devices and their marking- Basic color e.g. Red/green etc. but not shades of color



7. SHIPMENT CONTROLS

7.1 Date code remarking: If the date of assembly and test are both marked, the test date can beremarked if the device is retested at a later date. If only one date is marked to represent themanufacturing date and initial electrical test it shall not be changed.

7.2 Inner box formation:a) An inner box shall contain only devices of the same die revision/stepping level.b) It is preferred that devices shall also be from the same:

- wafer fab location.- assembly site.- outgoing QA electrical inspection site.

7.3 Date code age on delivery: The date codes (see paragraph 9.2) of devices shall not be olderthan 24 months referred to the incoming goods arrival date.

8. ELECTRICAL

8.1 Operating Conditions: As defined in the device specification or data sheet.

8.2 Electrical Test: All devices shipped must have passed a full electrical test per Test Code 1a orin the case of user specific devices a test program approved by the user.



9. MECHANICAL

9.1 Package dimensions:

9.1.1 If package dimensions are not specified by the user or by any industry standard, the latestagreed data sheet revision shall be the requirement.

9.1.2 Fine pitch packagesFor packages with lead pitch ≤ 0.5mm Coplanarity, Tweeze/Span, Bent lead/Skew & LeadFoot Angle shall be as specified in the relevant Jedec package outline. Tweeze span isdefined as inward /outward bending of the leads

9.2 Device marking:

9.2.1 Legibility: All the specified markings on the device shall be clearly legible.

9.2.2 Top surface: All of the following required markings shall be marked on the top side exceptwhere otherwise indicated below:

a) Pin 1 shall be identifiable either by a mark or by reference to a physical feature of thedevice.

b) The supplier's name or logo.c) The supplier type number or individual user part number as required. For memory

devices the supplier type number shall include a mask revision identifier.d) Date code of assembly or test. Four numerals Year, Year, Week, Week (YYWW) or 3

numerals (YWW) or one year numeral and one month character(YM) are acceptableformats. If both assembly and test date codes are marked the assembly code may bebottom marked.

e) A manufacturing route trace code. This item is preferred on the top side but may be onthe bottom side.

9.2.3 Small packages: If the marking area available on the device is too small to include all therequired marking, then, the magazine, or inner box containing the device, shall carry the fullmarking.

9.3 Moisture sensitivity: The moisture sensitivity of all non hermetic surface mount componentsshall be tested and classified according to JESD22-A112 or J-STD-020. The classification shallbe supplied on request.

9.4 Robustness of hermetic seals: Seal shall not be compromised by any normal handling, testingor manufacturing processes.



9.5 Lead (termination) finishes:

a) The following termination finishes are permitted as indicated provided they meet thesolderability requirements of this specification.

b) Thickness limits shall be met over 95% of termination surface. Appropriate measurementlocations shall be selected by the supplier. Note: 1um = 39.37 microinch = 0.03937 Mil

9.5.1 Hot solder dip:Applicable for Through Hole and SMD packages.It is not necessary for solder dipping to cover the entire lead. The area covered should beappropriate to the type of package: eg. J bend packages - area below base plane; Gull wingpackages - center of bottom radius to trimmed edge of lead.Sn/Pb composition: 70/30 to 50/50.Thickness: 5 um to 50 um.

9.5.2 Tin lead plate:Applicable for Through Hole and SMD packages.Sn/Pb composition: 95/5 to 60/40.Thickness: 5 to 50um.

9.5.3 Tin electroplate:Applicable for Through Hole packages only.Surface must be dense, homogenous and free of co-deposited organic material.Must be suitably treated to inhibit whisker growth.Thickness: 5 to 50um.

9.5.4 Gold:Not permitted unless specifically specified in the device specification or purchase documents.Composition: 99.7% gold.Thickness: 1.27um minimum.

9.5.5 Palladium over nickel plate :Thickness: Nickel 1um to 3um.

Palladium 0.076um to 0.251um.

10. SHIP TO STOCK

The supplier will be expected to work with individual users at their request towards achieving Shipto Stock status, whereby, incoming inspection and test is not performed. Users may have individualShip to Stock agreements.



11. QUALITY ASSURANCE

11.1 Quality system:a) The supplier shall have the appropriate ISO9000 or QS9000 registration and apply TQM

approach, or the supplier shall have established and documented a quality managementsystem of equivalent standard.

b) The system shall ensure that the requirements of this specification are met.c) The system shall provide for the prevention and ready detection of discrepancies and for

timely and positive corrective action.

11.2 Sampling Plans:Appropriate and statistically valid sampling plans shall be used and documented.

11.3 Failure Analysis Support:a) The supplier shall maintain an adequate failure analysis capability and provide a timely

response to failures returned for failure verification or failure analysis.b) Representative samples of devices returned as failures, shall be analyzed and a failure

analysis report issued to the originating user, typically within 30 days of the receipt by theanalytical facility of such returns.

c) For failure returns relating to a critical problem at a user, the failure analysis report shalltypically be issued within 7 days of receipt by the analytical facility.

Table 1

DEVICE FAMILY orCOMPLEXITY

PPM-2per EIA 554

Transistors: Gates:SSI 50 10 50MSI 500 100 50LSI 5000 1000 50VLSI 100K 20K 100ULSI 1000K 200K 100

11.4 Outgoing quality:

11.4.1 DPM levels: The supplier shall measure theoutgoing quality level in defects per million, forindividual devices or device families from uniformmanufacturing processes. The measurement ofoutgoing quality via in process measurements isacceptable in principle. The number of defects willinclude all devices non conforming to any functional,electrical, visual or mechanical specificationrequirement of a device. SLSI 1M 200K 150

Memory 10011.4.2 DPM calculation: The assessment methodand PPM calculation should be compatible withEIA554.

ASIC 100

11.4.3 Corrective action: If the outgoing qualitylevels given in Table 1 are not met, corrective actionshall be taken by the supplier.

Programmable logic whensupplied programmed andtested

100

PPM-3per EIA 55411.4.4 Data reporting: Outgoing quality data shall

be reported quarterly on request to individual users. Visual/mechanical 200



12. INCOMING INSPECTION

12.1 Lot acceptance: Users reserve the right to perform incoming lot acceptance on every lotreceived, using any:

a) Incoming test in Table 3.b) Qualification test in Table 4

Table 3 Incoming testPkgType

Test code per section 21 Insp.Level

AQL%

CPHB TC1a Electrical test II 0.065

CPHB TC2c Visual examination II 0.4

C H TC7 Hermeticity fine Mil 883 - 1014 II 0.65

C H TC7 Hermeticity gross Mil 883– 1014 II 0.25

Package types:C - Hermetic through holeP - Plastic through holeH - Hermetic SMDB - Non hermetic SMD

CPHB TC3 Dimensions II 0.1

12.2 Suspension of deliveries: The user may bring to the attention of the supplier any failure tomeet a qualification or incoming test and to require the supplier to withhold further deliveriesuntil the cause of the failure has been corrected.

12.3 Loss of approval: A failure of one or more shipping lots of a specific device to meet therequirements of this specification or the device specification shall constitute grounds for lossof approval. The action taken will depend on the nature of the problem found.

12.4 AQL/LTPD figures: The AQL/LTPD figures quoted are for the purpose of individualincoming lot rejection; they do not imply an overall acceptance quality level.

12.5 100% Screening: Users reserve the right to perform 100% screening on individual shippinglots received and to reject to the supplier any devices which do not meet the specifiedrequirements.



13. QUALIFICATION

13.1 Purpose:a) To demonstrate that a device has the CAPABILITY to meet the specified electrical, quality

and reliability requirements.b) To demonstrate that there is sufficient margin against the specification, so that, adequate

quality and reliability can be expected, in user applications.c) The qualification tests, are not intended to measure the quality or reliability of the device.

13.2 Samples:

13.2.1 Larger sample sizes: If a larger sample size than specified is used and failures allowed, thenthe result must meet an LTPD value of:Specified sample size 50 or less LTPD = 5%Specified sample size 76 LTPD = 3%

13.2.2 Additional samples: Users reserve the right, to take additional samples for a qualificationtest, where this is necessary, in order to reach a clear decision. For example, whendimension samples give a coplanarity result very close to the specified limit.

13.2.3 Consolidation of lots: Where production volumes of a device are low and the sample sizesspecified, are not economically feasible from one manufacturing lot, consolidation of lots ispermissible.

13.2.4 Reduced sample sizes: For commercial reasons the suppliers qualification procedures mayallow devices to be designated qualified and released to the market after testing to aqualification schedule which does not fully meet STACK requirements, i.e. reduced samplesize, reduced test time etc. This is acceptable provided test data continues to be accumulatedand corrective actions/repeat testing performed as necessary until the STACK qualificationlevel is reached or exceeded in a reasonable time.

13.3 References: These are given for guidance only. Reference shall always be made to theappropriate Test Code information for full test details.

13.4 In process test results:

a) If any of the Inspection or Package qualification tests are performed on a regular basis in themanufacturing line, these tests need not be repeated in new device qualification testing.

b) If qualification tests are not performed, manufacturing inspection results showing the currentquality level shall be included in the Qualification Report. Manufacturing package testresults shall be available on request.



13.5 Product monitor results: The supplier shall make reliability monitor data available onrequest, as part of the qualification procedure.

13.6 Maintenance of qualification standard: Regular quality and reliability test results, that areobtained from a monitor program, but which are not related to any particular customershipment, are an acceptable method of maintaining the qualification standard of thisspecification.

13.7 Pre-qual questionnaire: When requested by a user, the supplier shall complete a STACKPQQ and return it to the person named on the front sheet.

13.8 Technology verification:

a) As part of qualification, a user may assess the technology and materials of a deviceagainst the information given in the PQQ.

b) Non compliance with the PQQ or the non adequacy of its content are grounds forrejection.

13.9 Archiving: The qualification report and the test specification (not test program), used in thequalification shall be archived for a minimum of 3 years.



Table 4 Qualification Test ScheduleTestCode

PackageTypenote 3

TITLE Test

Reference

# oflots

SSperlot

Maxrej Note

3839

--

PROCESS RELIABILITYOxide IntegrityElectromigration

--

--

--

--

1c1d42292335

CPHBCPHBCPHBCPHBCPHBCPHB

ELECTRICAL EVALUATIONElectrical Test & DatalogElectrical CharacterisationInput/Output CapacitanceLatch-UpESD - Human Body ModelSystem level soft error per table 6

--

MIL 883-3012JESD78

JESD 22-A114-

33111-

50105

103-

00000-

11444

2a2b30

CPHBCPHBP B

INSPECTIONExternal Visual InspectionInternal Visual InspectionX-Ray Inspection

MIL 883-2009MIL 883-2010MIL 883-2012

111

2555

000

4

352046242115822

CPHBCPHBCHCPHBCPHBCPHBCPHBP BCPC H

PACKAGE TESTSDimensionsSolderability (76 leads / 5 devices min)Internal water vapor contentMarking PermanencyBond Strength (76 wires/5 devices min)Die Shear StrengthThermal ImpedanceFlammabilityLead integrity (15 leads/3 dev min)Lid torque

JESD 22-B100JESD 22-B102MIL 883-1018JESD 22-B107MIL 883-2011MIL 883-2019MIL 883-1012

UL94V0MIL 883-2004MIL 883-2024

1111111-11

57634

7653-35

0000000-00

910

C HCPHB

THERMAL TESTSThermal Shock sequence, 100 cyclesTemperature cycling sequence

JESD 22-A106JESD 22-A104

11

3232

00

22

71112132c1a

C HC HC HC HC HC H

MECHANICAL SEQUENCEHermeticity (fine/gross)Mechanical shockVibration, variable frequencyConstant acceleration, Y1 axisVisual examinationGuard banded electrical test

MIL 883-1014JESD 22-B104JESD 22-B103MIL 883-2001

1 32 0 2

16323334

CPHBCPHBCPHBCPHB

ELECTRICAL ENDURANCEHigh temperature operating lifeLTOL / Hot electron injectionWrite/erase endurance lifeData retention bake

JESD 22-A108

MIL 883-1033MIL 883-1033

3111

76222222

0000

1

18

36

P B

P B

MOISTURE ENDURANCETHB: 85oC/85%RH sequenceor: HAST sequenceAutoclave

JESD 22-A101JESD 22-A110JESD 22-A102

1

1

76

32

0

0

2

Note 1: Number of lotsSample size shown is required from each of 3 lots forqualification of new processes or new device families. Forindividual device qualifications 1 lot is required.

Note 2: Test SequencesFor tests that are specified as sequences, the samesamples shall successively receive all the tests in thesequence.

Note 3: Package TypesC – Hermetic through hole.H – Hermetic surface mounted.P – Plastic through hole.B – Non hermetic surface mounted.

Note 4: Sample sizesAs an alternative to using the specified sample size it isacceptable to test a range of similar devices with asmaller sample size in order to accumulate the samplesize specified.



14. QUALIFICATION OF CHANGES

14.1a) The principle of similarity may be applied in the qualification of changes.

b) What constitutes a change which requires qualification work is a matter of judgement, but ingeneral, a change must be qualified if there is a potential effect on performance, quality orreliability, or if there is any degree of uncertainty about the effect of the change.

c) Guidance on the qualification tests which the supplier should consider applying, for thevarious combinations of die, package and process changes, is shown in Table 3 of JEDECStd 47. The supplier shall perform tests defined in the qualification table, that areappropriate, or relevant to the change.

d) ASIC process stability and reproducibility across different manufacturing sites can beverified through measurement of critical electrical and physical process parameters ontransistor structures built into every wafer. This is considered equivalent to performingelectrical evaluation tests on individual designs produced on the transferred process. Onrequest the supplier shall perform full characterisation of any transferred device to resolvedesign issues arising from a process transfer.

15. SIMILARITY ASSESSMENT

15.1 Introduction:The principle of similarity may be applied in qualification, qualification of changes andproduct monitor testing. Definition of similarity shall be subject to audit.

15.2 Die changes: The supplier shall have documented and operate an appropriate set of die similarity rules.

15.3 Process/wafer fab changes: Process technologies must be examined module by module. Dissimilar modules shall be the focal points of analysis to determine what type of testing isrequired to properly confirm reliability.

15.4 Package/assembly changes:

a) Package families shall be grouped by configuration and materials of construction. Ingeneral, all members of the group that are equal to or smaller in dimensions and lead count, can be considered as similar to a qualified package, provided the assembly processtechnology and the assembly location are identical.

b) Packages should be qualified with the largest die they are designed to carry that is currentlyin production.



16. RELIABILITY

16.1 Operating reliability:a) Unless otherwise specified in the device

specification, the failure rate of devicesoperating in systems, at an ambient temperatureof +55oC, shall not exceed the figures in Table6 over a period of 20 years.

b) Results observed at a temperature other than+55oC, will be projected to this temperature,with 60% confidence using an activationenergy, appropriate to the failure mechanismobserved.

c) Refer to Test code 16 for calculation ofacceleration factors.

16.2 Failure criteria:a) A functional failure relative to the device

specification.b) A parameter limit failure relative to the device

specification.c) Intermittent faults due to the package pins, or

the interconnect system, from the pins to the diesurface, shall be regarded as failures.

d) Transitory faults attributable to the device shallbe regarded as failures.

16.3 Corrective action: If, when used within thespecified limits, the device does not satisfy thereliability requirements, the supplier shallinvestigate and take agreed actions to achieveconformity within the specification.

16.4 Data accumulation: The user reserves theright to apply accelerated life test and accumulatelife test data on any device, starting with the life testperformed for qualification.

16.5 Suspension of qualification approval: If thereliability data accumulated shows a device does notmeet the specified requirement, qualificationapproval may be suspended or revoked.

Table 6 Operating Life Failure Rates

FUNCTION COMPLEXITY FIT rate at 60%UCL & Tamb 55oC

Power diss. * = transistors BIP MOS

SSI < 350mWSSI > 350mWMSI < 350mWMSI > 350mWLSIVLSIVLSIULSISLSI

* < 50 * < 50 * < 500 * < 500 * < 5K * < 50K * < 100k * < 1000k * > 1M

5 10 10 15 30 30 - -

488122550100160250

Linear * < 400* > 400

23183

1849

Promafterprogramming

< 4k16k64k

224462

---

EpromorFlash

<1M2M4M8M16M32M64M

-------

345290100100100100

EEPROM 1M4M

--

2840

SRAM<4k16k64k256k1M4M16M

-------

142028405570100

DRAM 4M16M64M256M

----

36100100100

ASICThe supplier shall on request give a FIT rateprediction (based on a demonstrablemethodology) for the application andenvironmental conditions intended.

PALFPLALCA

Afterprogramming"

1504040

15-35

DRAMSRAM

System level soft single bit errorrate @ 90% UCL

2000 FIT1000 FIT

EEPROMEPROMFLASH

Write erase endurance& Data retention max reject rate

Underreview



17. PRODUCT MONITOR

17.1 Monitor program:a) The supplier shall have a continuous monitor program to demonstrate, that the requirements

of this specification are met, on an ongoing basis, for each manufacturing operation.

b) Statistical Process Control: The supplier shall control wafer production, assembly processand final test using statistical analysis. Any deviation shall be analyzed, the root causedetermined and the consequent corrective actions implemented. Parametric and yield datafrom probe and final tests shall be analyzed against in-line or electrical process control data.

c) Table 7 shows the minimum test requirements for a conventional stress driven monitor. Theuse of a Failure Mechanism Driven approach to optimise reliability monitoring isencouraged. Ongoing qualification test data and accumulated reliability monitor test datamay be assessed in a structured way to reduce reliability monitor testing when failuremechanisms are shown to be eliminated by process controls and to increase testing orintroduce new tests when failures are detected.

17.2 Problem alert: In the case of serious failure the STACK office and individual users shall benotified by a problem ALERT.

17.3 Data reporting: Reliability monitor data accumulated over the preceding six month period,shall be available to users on request, at one months notice.

17.4 Samples:a) Appropriate sample sizes shall be selected.b) Samples shall be randomly selected from representative package and process family

devices.c) All package types and all process families but not necessarily all package/process

combinations shall be monitored.d) Package tests shall use the largest die size the package is designed to carry that is

currently in production.e) Sample lots will be added to the monitor at intervals appropriate for each test.

17.5 Production maturity factors: The FIT rates in Table 6 represent devices in matureproduction. Maturity factors (MF) may be used to multiply the values in Table 6.

Production time (months) 0 - 12 12 - 24 24+

Maturity factor (MF) 4 2 1

17.6 Device dissipation: Where the device dissipation in the oven is significantly less than innormal operation this shall be taken into account in FIT rate calculations.



17.7 Corrective action: Failure to meet the limits in Table 7 shall trigger appropriate correctiveaction by the supplier.

17.8 Suspension of qualification approval: Continued failure to meet the limits in Table 7 maylead to qualification approval being suspended or revoked.

17.9 Accumulated test data:a) Failure rates and levels may be a rolling average with data accumulation period

appropriate to the production quantity level.

b) For HTOL test, the minimum total sample size (SS) required over the data

accumulation period, may be calculated using: SS = tAFITS2

10c)(B, Chi 92

×××× where:

Chi2 (60%,0) = 1.83Chi2 (60%,1) = 4.04Chi2 (60%,2) = 6.21

FITS = see Table 6c= number of failuresB= upper confidence limit

A = = AT x AV (see test 16)t = time under bias in oven

Table 7 Product Monitor Tests:a) Any test frequently performed in manufacturing need not be repeated in QA product

monitor.b) Package types subject to each test are as given in Table 4.

Test Codes TITLE Max Failure Notes

16 + 1a Early life Note 4 1,2

16 + 1a Long term life Note 5 2, 6

34 Data retention bake 0.5% 3

10 Temperature cycling 0.5% 3

9 100 Thermal shocks 0.5% 3

18 + 26 85/85 or HAST + precondition 0.5% 3

4 Marking permanence 0.5% 3

20 Water vapor content 0.5% 3

5 Solderability 0.5% 3

Notes to table 7: 1. Duration up to 168h. 2. Failure rate calculated as shown in Test 16. 3. Failure levels are actual number of failures divided by the quantity tested. 4. Early life FIT rate = 2 x Table 6 value x prod. maturity factor (section 17.5). 5. Long term life FIT rate = 1 x Table 6 value x prod. maturity factor. 6. HTOL on devices may be substituted by WLR testing to a STACK approved standard.



18. ENVIRONMENTAL

18.1 Self ignition: When a device fails, whether it is due to an electrical overload or an inherentfault in the device, it shall not ignite, explode or emit harmful or toxic material.

18.2 Toxic materials: No toxic effects shall result from handling, usage or disposal of the itemin accordance with the provisions of this, and the referenced specifications and documents.

18.3 Environmental regulation compliance: The supplier shall fully comply with all applicableenvironmental regulations. The supplier will continuously reduce the impact of itsoperations and products on the environment by reducing emissions and waste, by the use ofpost consumer materials, by product stewardship and by other means as necessary. Compliance with the environmental requirements shall be a major consideration for supplierselection.

19 SHIPMENT PACKAGING

19.1 General:

19.1.1 ESD protection: All integrated circuits are considered to be static sensitive and must besupplied in suitable protective packaging with electrostatic properties meeting therequirements of EIA 541 unless otherwise specified in this section.

19.1.2 Specification compliance after shipment: The method of packing for land, sea or airtransportation shall adequately protect the device from being degraded in any way duringtransit to the address on the Purchase Order.

19.1.3 Device orientation: Devices shall all have the same orientation within a magazine.

19.1.4 User instructions: Any special handling requirements or precautions eg : placing ofdesiccants resealing of containers maximum number of 24h 125oC bake cycles allowablewhich must be observed for storage or reshipment shall be stated on the packing and wherenecessary, supporting documentation shall be supplied with each inner box.

19.2 Electrostatic properties:See Test Code 44 for information on test methods.

19.2.1 Electrostatic shield: The inner box or magazine must contain an electrostatic shield ofsurface resistivity less than 106 ohms/square.

19.2.2 Magazine surface resistivity: Packing material in direct contact with the device pins shallhave a surface resistivity less than 1012 ohms/square.



19.2.3 Inner box surface characteristics: All surfaces of the inner box other than an electrostaticshield shall meet the following:

Surface resistivity: 105 to 1012 ohms/square.Charge decay in 2 sec: 5kv to less than 100v.Triboelectric charge: Not to exceed 100v.

19.3 Magazine reuse:

a) Tubes, trays or other magazines which depend for their electrostatic properties on surfacecoatings shall be limited to a defined number of load/unload cycles. The specifiedsurface resistivity shall be met after the defined number of cycles and data shall beavailable to justify the limit chosen. Coated magazines may be "reset" to zero loadcycles by a suitable recycling process which includes recoating.

b) Magazines which utilize bulk material properties may be reused.

19.4 Tubes:

19.4.1 Cushioning material: Ceramic devices packaged in tubes shall have an adequate amount ofcushioning material to ensure that the devices are not damaged as a result of movementwithin the tubes.

19.4.1 Partial tubes: Full tubes shall be shipped with a maximum of one partly-filled tube per innerbox.

19.4.3 Marking access: The material of the tube shall be transparent or contain a slot to allowinspection of top markings.

19.4.4 Opening: Tubes shall be openable at either end.

19.5 Trays:

19.5.1 For devices with a moisture sensitivity classification according to JESD22-A112 orJ-STD-020 of 4 or higher, the tray shall have a bake capability of 125oC min.

19.5.2 Bake temperature limit to be marked on tray.

19.5.3 No more than 10 full trays to be stacked in height with one further tray as a cover.



20. LABELS

20.1 General:20.1.1 Human readable content: The content shown for each label in this section shall be available

in human readable form on the outside of the relevant package.

20.1.2 Machine readable content: Bar codes for those items specified shall be included in 3 of 9code (bar code 39) per Mil Std 1189 or EIA556 or equivalent compatible standard.

20.1.3 Warning notices: Any necessary warning notices or symbols to ensure the safety of thecontents shall be included as appropriate. In the case of electro-static or moisture sensitivedevices, it is preferred that this is indicated in letters at least 4mm high.

20.2 Label Content

Dry pack label: Bar code

(a) Date of sealing and sealed life or expiration date.

(b) Time and storage condition limits after opening.

(c) Bake conditions if usage conditions after opening are violated.

(d) Moisture sensitivity classification per JESD22-A112 or J-STD-020

Outer box label: This label is typically implemented as a shipping note attachedto the outer box. For security reasons items (d) , (e) & (f) can be omitted with theagreement of the user

(a) Delivery address.

(b) Purchase Order number. *

(c) User part number. *

(d) Supplier device type number. *

(e) The supplier's name.

(f) Quantities enclosed of each device type. *

Inner box label:

(a) Supplier device type number. *

(b) User part number. (preferred but not mandatory) *

(c) Purchase order number. (preferred but not mandatory) *

(d) Quantity of devices. *

(e) Date code. *

(f) Lot number. *

(g) Assembly location. (preferred but not mandatory)

(h) Test location. (preferred but not mandatory)



21. TEST CODE INFORMATION

TEST 1 ELECTRICAL TEST

TEST 1a Guard Banded Electrical Test:Electrical test performed at the worst still air ambient temperature in the range of Topmin to Topmax.If for convenience, the test is carried out at a temperature which is not the worst one then full guardbanding allowance shall be made. Characterization data shall be made available on request tojustify the test limits chosen for guard banded tests.The test shall include:a) DC test to datasheet.b) AC test to datasheet.c) Functional Test:

- Fault coverage for stuck at 1 & 0 should typically exceed 95%- Special tests where applicable, eg. pattern sensitivity etc.- Functionality verification to the device specification.

TEST 1c Electrical Test and Data Log:Devices shall be tested and datalogged at Topmin, 25oC and Topmax, with results from the datalogmade available to the user as a written report containing the following:a) Statistics for each measured parameter, including Min, Max and Mean. Standard deviation and

CP/CPK may also be included at the suppliers discretion.b) Histograms of "critical" parameters.

TEST 1d Electrical Characterisation:Purpose: To check variation within the device specification limits and to explore parametricbehavior outside the device specification limits to look for marginality in the device design orprocess.Results: These shall be presented on parameter variation with supply voltage and other relevantparameters.Shmoo plots: Shall be included for "critical" parameters including timings, input and outputthresholds vs supply voltage etc.Temperature Trends: Temperature coefficients for "critical" parameters and supply currents shallbe given as part of the characterisation.

TEST 1e Population Parameter Drift:Devices shall pass Test 1a both before and after endurance testing and results of main parametersshall be datalogged.a) Individual devices are not required to be serialized.b) Adequate parameter stability shall be confirmed.c) Statistical measures of population drift shall be reported. The drift of the population mean for

any parameter shall be less than 10% of the initial population mean.d) Functional failures may be excluded from calculation of mean values.



TEST 2 VISUAL INSPECTION:

TEST 2a External Visual Inspection: Purpose, apparatus and procedure shall be as specified inMil Std 883, Method 2009.

Hermetic package failure criteria: As per Mil Std 883, Method 2009.

Plastic package failure criteria: Mil Std 883, Method 2009 with the addition of the followingmoulding defect criteria. Where no measurement criteria is given, the defect is a reject if visible at3X magnification:

a) Incomplete fill of package form.b) Inner lead exposed.c) Rough surface > 10% of the total area in any site of package.d) Pin holes.e) Surface blister.f) Blister void (surface blister already broken or can be broken by a needle).g) Blister near a power package mounting tab.h) Ejection pin defects in any direction and in any part of the marking area which are >

0.1mm in any direction.i) Any crack or gap at interface of metal and resin visible at 10X magnification.j) Flash on lead > 0.5mm from package body.k) Flash on power package mounting tab hole.l) Cap and frame misalignment > 0.1mm.m) Broken package.n) Resin mark around ejector hole > 0.1mm in any direction.

TEST 2b Internal Visual Inspection:Mil Std 883, Method 2010, Condition B. Only the criteria given which is relevant to the deviceunder inspection need be applied.Normally supplier results prior to encapsulation will be used. If decapsulation is employed, dueallowance will be made for damage caused in the decapsulation process.

TEST 2c Visual Examination:a) An external examination of the marking shall be performed, without magnification, or with a

viewer having a magnification no greater than 3X.b) A visual examination of the case, leads, or seals shall be performed at a magnification between

10X and 20X.c) Evidence of defects or damage to the case, leads or seals or illegible markings shall be

considered a failure. Damage to the marking caused by fixturing or handling during tests, shallnot be a cause for device rejection.



TEST 3 DIMENSIONS:Mil Std 883, Method 2016 or JESD22-B100

TEST 4 MARKING PERMANENCY:Not applicable to laser marking.The use of CFC solvents is not a requirement.The sample "groups" may each consist of one device. Each group shall be tested with a differentsolvent.JESD22-B107 solutions a, b and corMil Std 883, Method 2015 solutions a, b and d

TEST 5 SOLDERABILITY:This test is intended to assure that devices stored in the as received condition and packaging shallretain solderability after delivery for a minimum of 12 months in "standard atmospheric conditions"of ambient temperature and relative humidity in the range 5 to 30oC, 20 to 70%RH.

Test Method: JESD22-B102 or Mil Std 883, Method 2003.

Flux: Non activated flux - Type R of Mil-F-14256 or Type ROL of J-STD-004.

Ageing: 8 hours steam.

Temperature:a) Through Hole Devices:

245oC for 5 sec.

b) Surface Mount Devices:215oC ± 2oC for 5 sec ± 1s.

Palladium plated devices:The supplier may choose to perform the test at 215oC ± 2oC for 10s ± 1s but the user reservesthe right to perform the test as specified and to reject on failure.

TEST 6 BOND STRENGTH:Minimum bond strength as specified in Mil Std 883, Method 2011, Test condition D.Recording of failure categories is not required.Plastic packages shall be tested before encapsulation.



TEST 7 HERMETICITY:Not applicable to non hermetic packages.

Fine: Mil Std 883, Method 1014, Condition A or B.thenGross: Mil Std 883, Method 1014, Condition C.

TEST 8 LEAD INTEGRITY:Mil Std 883, Method 2004, Condition B2 lead fatigue followed by hermeticity test (TC7) forhermetic packages only.Not applicable to SMD and PGA.

Dual in line packages: A minimum of 4 leads on each sample device to receive 3 inward bends of15o. If corner pins have reduced width or thickness then at least 1 corner pin shall be tested on eachdevice such that all 4 corner pins are included in the sample.

TEST 9 THERMAL SHOCK SEQUENCE:Mil Std 883, Method 1011, Condition B or JESD22-A106, Condition C.Liquid to liquid thermal shocks.10sec maximum transfer time between liquids.2 minutes minimum dwell time in each liquid.Applicable to hermetic packages only.

End point tests: Hermeticity - test code 7.Visual examination - test code 2c.Guard banded electrical test - test code 1a.

TEST 10 TEMPERATURE CYCLING:Mil Std 883, Method 1010 Condition B or JESD22-A104 Condition B.1000 air to air thermal cycles.1 minute maximum transfer time.10 minutes minimum dwell time.Solder preconditioning to be applied for non hermetic SMD as per test code 26

End point tests: Hermeticity - test code 7 (hermetic devices only).Visual examination - test code 2c.Guard banded electrical test - test code 1a.

The supplier shall apply the specified number of -55 to +125oC cycles. Alternative number ofcycles and temperature extremes with Tmin ≤ -40C are acceptable if the supplier can show the stresslevel is equivalent.



TEST 11 MECHANICAL SHOCK:JESD22-B104 Condition B or Mil Std 883, Method 2002, Condition B:5 pulses 1500g, each pulse 0.5msec duration.

TEST 12 VIBRATION (VARIABLE FREQUENCY):JESD22-B103 or Mil Std 883, Method 2007 Condition A.Peak acceleration: 20g.

TEST 13 CONSTANT ACCELERATION:Mil Std 883, Method 2001.Applicable only to cavity packages and devices with bonds and solder joints not molded in.Apply Y1 axis only.The supplier shall select a test condition appropriate to the package mass, area and perimeter length.Condition E: 30,000g for mass < 5 gram.Condition D: 20,000g for cavity or inner seal perimeter > 50mm.

TEST 15 FLAMMABILITY:UL94 V0The bulk material test is mandatory but the supplier may meet this test requirement by usingmaterial manufacturers test data.

If bulk material is not available IEC695-2-2 needle flame is a suitable method for tests on individualdevices.



TEST 16 HTOL TEST:

Test Method:JESD22-A108 or Mil Std 883, Method 1005.The supplier shall apply a static or dynamic life test which best relates to the device type.

General:a) Devices shall be cooled to room temperature prior to the removal of bias.b) Interruption of bias for up to one minute for the purpose of moving the devices to cool down

positions shall not be considered removal of bias.

End point measurements:a) Following bias removal the devices shall be maintained at less than 30oC ambient until tested.b) Electrical endpoint testing shall be completed within 48 hours of removal of bias.c) Electrical test 1e population parameter drift.

Qualification conditions:a) 1000h at Tamb ≥ 125oC. Higher test temperatures for shorter test times may be used provided

the stress is equivalent and anomalous failures do not result from the higher test temperature.b) Maximum operating voltage.c) If internal power dissipation causes Tj to exceed Tjmax or activate a thermal shutdown circuit,

the test temperature may be reduced and the test time extended.d) By using the temperature and voltage acceleration factors defined herein, the field life simulated

by the qualification test shall be stated in the Qualification Report.

Test results assessment:Product monitor results accumulated from periods of accelerated life test may be used to assess earlylife and long term failure rates, using:

Where:Chi2 (60%,0) = 1.83Chi2 (60%,1) = 4.04Chi2 (60%,2) = 6.21

B = upper confidence limit.c = number of observed defects.N = number of devices tested.

FIT = VT

92

AAtN210c)(B, Chi××××

× AV = voltage acceleration factor.AT = temperature acceleration factor.t = test duration of up to 168 hour for early life calculations or

total test duration minus early life period for long term lifecalculations



Temperature acceleration factor: The supplier shall use the activation energy indicated fromrelevant failure analysis data. Where no relevant data is available, an activation energy of 0.7eVmay be used, but it must be recognised that this will not take account of oxide failure mechanisms.

Table 8 examples of AT for Ea = 0.7eV Toven(oC)

t(hours)

∆Tja(oC)

AT Field life(years)

e

T

1-

T

1

KE

T ovenjsysj

a

= A

125 1000

015304560

7855413125

8.96.34.73.62.8

125 2000

015304560

7855413125

17.812.69.37.15.6

Where:Ea = Activation energy.K = 8.617 x 10-5 eV/oK.Tj sys oK = 273 + ∆Tja + Tsys.Tj oven oK = 273 + ∆Tja + Toven.T sys = 55oC system ambient.∆Tja = Junction temp rise due to

power dissipation150 1000

015304560

2601701178361

29.719.413.39.57.0

Supply voltage acceleration factor:

a) If a supply voltage higher than the nominal operating voltage is used, a voltage accelerationfactor may be used in FIT rate calculations.

b) Relationships are typically of the form shown below but any formula and constant values maybe used for which the supplier has supporting evidence. This evidence shall be provided onrequest.

−=

V2V1 CeAv

Where:C = constantV1 = stress voltageV2 = operating voltage



TEST 18 MOISTURE ENDURANCE:Test sequenceSolder preconditioning (test 26) - non hermetic SMD.Visual examination (test 2c) - non hermetic SMD.Guard banded electrical test (test 1a).THB test: 85oC/85%RH or HASTGuard banded electrical test (test 1a).

Temperature Humidity Bias85/85 Test

Highly Accelerated temperatureand humidity Stress Test

JESD22-A101 JESD22-A110Relative humidity 85% ± 5% Relative humidity 85% ± 5%Temperature 85oC ± 2o Temperature 130oC ± 2o

Duration 1000 hours Duration 96h

The supplier may use other HAST conditions as an alternative to 85/85 THB test when the supplier has adequate evidence of correlation using those conditions. The conditions used must be stated inthe Qualification Report.

TEST 20 INTERNAL WATER VAPOR CONTENT:5000 PPM maximum water vapor content at 100oC.Mil Std 883, Method 1018.Procedure 1 mass spectrometry.

TEST 21 THERMAL IMPEDANCE:Mil Std 883, Method 1012The maximum thermal impedance θjc and θja shall be as defined in the device specification.

TEST 22 LID TORQUEMil Std 883, Method 2024.

TEST 23 ESD - HUMAN BODY MODEL:a) JESD22-A114 or Mil Std 883, Method 3015b) Time delay between pulses ≤ 1s.c) Electrical Test 1a with no failures after ESD testing to ≥ 1000 volts on 3 samples.d) ESD classification to be recorded in the Qualification Report.e) 1 positive and 1 negative pulse for each pin combination.

Similarity: Sample testing among groups of similar pins is acceptable. The similarity basis shall bestated in the qualification report. Users reserve the right to test any pin to pin combination and toreject on failure.



TEST 24 DIE SHEAR STRENGTH:Mil Std 883, Method 2019.Plastic packages shall be tested before encapsulation.

TEST 26 SOLDER PRECONDITIONING:

Not applicable to hermetic packages

a) Moisture conditioning appropriate to the device moisture sensitivity classification followed bythree vapor phase, convection or IR reflow soldering operations in accordance with JESD22-A113 & J-Std-020.

Package thickness ≥ 2.5mm & all BGA.Pkg. thickness < 2.5mm & Pkg. volume ≥350mm3

Pkg. thickness <2.5mm& Pkg. volume <350mm3

Convection 220 +5/-0 oC Convection 235 +5/-0 oCVPR 215 – 219 oC VPR 235 +5/-0 oCIR/Convection 220 +5/-0 oC IR/Convection 235 +5/-0 oC

b) The moisture conditioning and soldering operation(s) applied, shall be stated in theQualification Report.

c) The moisture conditioning shall be as specified or give an equivalent moisture weight gain.d) If wave soldering capability is required by a device specification agreed with the supplier, it

shall be demonstrated by immersing the device in flux followed by immersion in solder at260oC for 10 seconds. This operation may include soldering devices onto a pcb with apreheat ramp rate of up to 10oC/sec. To avoid solder bridging problems on some fine pitchpackages oil may be used in place of solder for wave soldering simulation.

TEST 29 LATCH-UP:Applicable to CMOS technologiesEIA/Jedec Standard EIA/JESD78Power supply overvoltage and current injection into I/O pinsTest conditions used shall be recorded in the qualification report

Failure criteria 1.4 x Inom or Inom +10mA whichever is greater ordevice no longer meets functional or parametricrequirements of the device specification.

PSOV pulse 1.5 x max VsupplyPositive current pulse +(Inom+100mA) or 1.5xInom whichever is greater in

magnitudeNegative current pulse -100mA or -0.5xInom whichever is greater in magnitude



TEST 30 X-RAY INSPECTION:a) The construction quality of plastic devices shall be assessed in relation to the criteria in MIL

Std 883, Method 2012. Only the criteria given which is relevant to plastic devices need beapplied.

b) The number and size of sub surface voids in plastic encapsulation material shall be assessedby Acoustic Microscopy, X-Ray or other suitable method. The supplier shall haveappropriate acceptance criteria.

TEST 32 LTOL / HOT ELECTRON INJECTION:Applicable to sub-micron MOS technologies.End point: Electrical Test 1e - Population parameter drift.Test conditions:

Absolute max Vcc, for DRAM.Maximum Vcc for other devices.Duration 1000 hours.Junction temperature equal to or colder than -10oC.Dynamic operation.

TEST 33 WRITE/ERASE ENDURANCE LIFE:Applicable to floating gate technologiesElectrically programmable /erasable non volatile memory devicesMil Std 883, Method 1033.The supplier shall determine the write/erase and subsequent data retention properties of the deviceusing a combination of write/erase cycling and high temperature bake testing.

The test shall extend to the maximum number of write/erase cycles specified. Appropriate interimbake and electrical test points shall be selected by the supplier.

For each applicable technology the relationship between the number of write/erase cycles and dataretention period (hours) shall be available via supplier website, data sheet, application notes etc. orbe available on request.

Procedure for one write/erase test cycle:a) Write the device with a suitable pattern.b) Electrical test (first and last cycles only).c) Erase the Device.d) Write the inverse of the pattern in (a).e) Electrical test (first and last cycles only).f) Erase the device.



TEST 34 DATA RETENTION BAKE:Applicable to floating gate technologiesMIL Std 883, Method 1033.Electrically programmable /erasable non volatile memory devices.Procedure:

a) Electrical test 1a.b) Write the device with a suitable pattern.c) Bake at 150oC for 1000 hours minimum.d) Read and confirm the data pattern still valide) Electrical Test 1a.

The test time should be extended if necessary to demonstrate the specified data retention period.If test at 150oC causes anomalous failure mechanisms, the test temperature may be reduced and thetest time extended

TEST 35 SYSTEM LEVEL SOFT ERROR RATE:This test applies to DRAM and SRAM. For SRAM references to refresh may be ignored.

Reporting: The following shall be stated in the Qualification Report. Items (a) to (d) shall bechosen by the supplier:

a) Sample size.b) Test duration (hrs).c) Test temperature.d) Refresh type e.g. RAS only, CbR, Burst, etc....e) Number of soft errors found.

Sample size/Test Duration: For qualification the number of device-hours must be adequate todemonstrate that the soft error rate does not exceed the figure specified in Table 6.

Test conditions:a) Supply Voltage = Vcc minimumb) Cycle time = 500 nsc) Refresh period = maximum specified refresh interval (period)d) Test temperature = 55oCe) The test shall be performed at the minimum voltage level specified for data retention.

Data pattern:a) Write and verify checkerboard once, then read/refresh continuously.b) Repeat with complementary checkerboard.c) Test with checkerboard and complementary checkerboard patterns shall be performed

for approximate equal durations.

Accelerated testing: Accelerated testing using the "hot source" irradiation method is not acceptableas substitute for system level soft error test.



TEST 36 AUTOCLAVE:Jedec JESD22-A102 Condition CTemperature 121oC.Relative humidity 100%.No bias.Duration 96 hours.End point test: Electrical test 1a – Guard banded electrical test.

TEST 38 OXIDE INTEGRITY:The supplier shall perform appropriate testing to demonstrate oxide integrity, eg. Time DependentDielectric Breakdown (TDDB).

The data shall cover all critical oxide layers.Details of test methods and results shall be provided as a written report, on request.Process monitor test results eg. Qbd and Vbd testing are acceptable.

Oxide integrity may be demonstrated by test results using Ea=0.3eV from voltage acceleratedtesting on test structures or devices. If other acceleration factors are used they must be justified byexperimental data or be published figures. Any published figures used should generally be fromoxide of similar (+/- 20%) thickness grown using the same method (steam, dry etc).

TEST 39 ELECTROMIGRATION:The supplier shall perform appropriate testing to characterize the metallisation system anddemonstrate for the layout dimensions used: > 100,000 hours for 0.1% cumulative failures.

The requirement to perform electromigration testing is not limited to sub micron technologies.Larger geometries are subject to electromigration wear out mechanisms.

Characterisation data may be for the metallisation and contact process as a whole, using acceleratedcurrent and temperature testing of test structures on the wafer rather than individual device types.Acceleration factors must be justified by experimental data.

Process monitor test results are acceptable.



TEST 42 INPUT/OUTPUT CAPACITANCE:MIL Std 883 method 3012.This test is only required for new process/design qualifications.

The device shall be biased at nominal operating voltage. Capacitance measurements shall be madeat all logic levels for digital devices and normal biased condition for analog devices.

TEST 44 ELECTROSTATIC PROPERTIES OF MATERIALS:

Electrostatic properties shall be as specified after conditioning of 48 hours at 23oC ± 3oC and12%RH ± 3%.

Any appropriate test method may be used, examples are contained in EIA 541. This testrequirement may be met by a certificate of conformance from the material supplier.

22. DOCUMENT REVISION HISTORY

22.1 Issue History:

29 May 1975 Issue 104 March 1976 Issue 225 June 1976 Issue 311 May 1977 Issue 414 September 1977 Issue 502 April 1979 Issue 602 August 1979 Issue 711 April 1983 Issue 820 September 1984 Issue 923 February 1987 Issue 1003 August 1989 Issue 1119 December 1990 Issue 11.130 October 1992 Issue 1215 September 1993 Issue 12.131 January 1996 Administrative update:

Issue remains at 12.1.13 October 1997 Issue 12.220 July 1998 12.2 notice 119 November 1999 12.2 notice 2

END OF SPECIFICATION

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