General Description Features - Maxim Integrated
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Rev: 102108 DS33M33 Demo Kit General Description The DS33M33 demo kit (DK) is an easy-to-use evaluation board for the DS33M33 and the DS33M33 Ethernet-over-SONET/SDH devices. The demo kit contains an option for either T3 or E3. The T3E3 links are complete with line interface, transformers, and network connections. Maxim’s ChipView software is provided with the demo kit, giving point-and-click access to configuration and status registers from a Windows®-based_PC. On-board LEDs indicate receive loss-of-signal, queue overflow, Ethernet link, Tx/Rx, and interrupt status. Windows is a registered trademark of Microsoft Corp. Demo Kit Contents DS33M33DK Board CD Including: ChipView Software DS33M33 Definition Files DS33M33DK Definition File DS33M33DK Data Sheet DS33M33 Data Sheet Features ♦ Demonstrates Key Functions of DS33M33 Ethernet Transport Chipset ♦ Includes Ethernet PHY Supporting 10/100 and Gigabit Modes ♦ Includes Optical SFP Module for SONET/SDH Interface ♦ Network Connectors, Transformers, and Termination Ease Connectivity ♦ Careful Layout Provides Signal Integrity ♦ On-Board Processor and ChipView Software Provide Point-and-Click Access to the DS33M33 and DS3154 Register Set ♦ Software-Controlled (Register Mapped) Configuration Switches Facilitate Clock and Signal Routing ♦ All System Side and Overhead Pins are Easily Accessible for External Data Source/Sink ♦ LEDs Programmed Through GPIO Pins Provide Status ♦ Easy-to-Read Silkscreen Labels Identify the Signals Associated with All Connectors, Jumpers, and LEDs Ordering Information PART TYPE DS33M33DK Demo Kit for DS33M33 ________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Transcript of General Description Features - Maxim Integrated
Rev: 102108 DS33M33 Demo Kit
General Description
The DS33M33 demo kit (DK) is an easy-to-use evaluation board for the DS33M33 and the DS33M33 Ethernet-over-SONET/SDH devices. The demo kit contains an option for either T3 or E3. The T3E3 links are complete with line interface, transformers, and network connections. Maxim’s ChipView software is provided with the demo kit, giving point-and-click access to configuration and status registers from a Windows®-based_PC. On-board LEDs indicate receive loss-of-signal, queue overflow, Ethernet link, Tx/Rx, and interrupt status.
Windows is a registered trademark of Microsoft Corp.
Demo Kit Contents DS33M33DK Board CD Including:
ChipView Software DS33M33 Definition Files DS33M33DK Definition File DS33M33DK Data Sheet DS33M33 Data Sheet
Features ♦ Demonstrates Key Functions of DS33M33
Ethernet Transport Chipset ♦ Includes Ethernet PHY Supporting 10/100 and
Gigabit Modes ♦ Includes Optical SFP Module for SONET/SDH
Interface ♦ Network Connectors, Transformers, and
Termination Ease Connectivity ♦ Careful Layout Provides Signal Integrity ♦ On-Board Processor and ChipView Software
Provide Point-and-Click Access to the DS33M33 and DS3154 Register Set
♦ Software-Controlled (Register Mapped) Configuration Switches Facilitate Clock and Signal Routing
♦ All System Side and Overhead Pins are Easily Accessible for External Data Source/Sink
♦ LEDs Programmed Through GPIO Pins Provide Status
♦ Easy-to-Read Silkscreen Labels Identify the Signals Associated with All Connectors, Jumpers, and LEDs
Ordering Information PART TYPE
DS33M33DK Demo Kit for DS33M33
________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
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Table of Contents
1. BOARD FLOORPLAN .....................................................................................................................3
2. PC BOARD ERRATA.......................................................................................................................3
3. FILE LOCATIONS............................................................................................................................4
4. BASIC OPERATION ........................................................................................................................5 4.1 POWERING UP THE DEMO KIT..........................................................................................................5
4.1.1 General .................................................................................................................................................. 5 4.2 BASIC DS33M33 INITIALIZATION......................................................................................................5
4.2.1 Additional configuration for DS33M33 ................................................................................................... 5 4.3 MONITOR AND CAPTURE ETHERNET TRAFFIC ...................................................................................5
5. JUMPERS AND CONNECTORS .....................................................................................................6
6. LINE-SIDE CONNECTIONS ............................................................................................................9
7. SYSTEM CONNECTORS ................................................................................................................9
8. MICROCONTROLLER.....................................................................................................................9
9. POWER-SUPPLY CONNECTORS ..................................................................................................9
10. CONNECTING TO A COMPUTER ..................................................................................................9
11. INSTALLING AND RUNNING THE SOFTWARE..........................................................................10
12. ADDRESS MAP .............................................................................................................................11 12.1 OVERHEAD CPLD REGISTER MAP..............................................................................................11 12.2 CONTROL AND STATUS REGISTERS ............................................................................................12
13. ADDITIONAL INFORMATION/RESOURCES................................................................................16 13.1 DS33M33 INFORMATION............................................................................................................16 13.2 DS33M33DK INFORMATION.......................................................................................................16 13.3 TECHNICAL SUPPORT.................................................................................................................16
14. COMPONENT LIST........................................................................................................................16
15. SCHEMATICS ................................................................................................................................21
List of Figures Figure 1-1. DS33M33DK Board Floorplan................................................................................................................... 3 Figure 15-1. DS33M33 PCB Layout and Schematic Hierarchy Block Page Listing.................................................. 21
List of Tables Table 3-1. Definition and Configuration Files .............................................................................................................. 4 Table 5-1. Jumpers and Connectors ........................................................................................................................... 6 Table 12-1. Address Map .......................................................................................................................................... 11 Table 12-2. Register Map for Overhead CPLD (Reference Designator U01) ........................................................... 11
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1. Board Floorplan
Figure 1-1. DS33M33DK Board Floorplan
2. PCB Errata There are no errata for the DS33M33DK02A0.
MICROPROCESSOR
SFP LEDs
SERIAL PORT (57600-8-N-1)
DS3154 T3E3 TRANSFORMER AND NETWORK
CONNECTIONS (T3E3) CLOCKS AND
CLOCK SELECTION
USB
DRIVER CONFIGURATION
POWER (5V)
ETHERNET PHY AND
CONNECTOR
REDUNDANT SONET OPTICAL SFP
PRIMARY SONET OPTICAL SFP
SFP LEDs
DS33M33
SPI C
ONFI
G JU
MPER
S
ETHERNET CONFIGURATION
JUMPERS
DDR
SYSTEM SIDE JUMPERS
DS33M33-TO-LIU
OVERHEAD FPGA AND
TEST POINTS ADDRESS DATABUS TEST POINTS
COMM SELECT JUMPERs
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3. File Locations
This demo kit relies upon several supporting files, which are provided on the CD and are available as a zip file from the Maxim website www.maxim-ic.com/DS33M33DK. All locations are given relative to the directory in the CD/zip file called “DS33M33_def_ini_”. Table 3-1 shows the DS33M33, DS3154, and FPGA register definition files and configuration files.
Table 3-1. Definition and Configuration Files FILE NAME FILE USAGE
. \parallel_mode\ _DS33M_GlobalSonet.def Top level definition file to select in ChipView’s register mode. This file will autoload the remaining definition files for the DS33M33 when parallel mode is used. (Note the wan files still need to be loaded (either DS)).
.\parallel_mode\DS3154DC.def
.\parallel_mode\ds33M_BufferMan.def
.\parallel_mode\ds33M_EncapDecap.def
.\parallel_mode\ds33M_GlobalEth.def
.\parallel_mode\ds33M_group.def
.\parallel_mode\ds33M_LanSubscriber.def
.\parallel_mode\DS33M_port1.def
.\parallel_mode\DS33M_port2.def
.\parallel_mode\DS33M_port3.def
.\parallel_mode\DS33M_serial_1234.def
.\parallel_mode\DS33M_TEST.def
.\parallel_mode\ds33M_Vcat.def
.\parallel_mode\Overhead_FPGA.def
DS33M33 dependent files. These are called by _DS33M_GlobalSonet.def file, which is listed above.
.\parallel_mode\m33_eos_vcg0_port2_port3_mii.mfg File for manually configuring the DS33M33 for EoS VC3 with two ports assigned to VCG1.
.\parallel_mode\m33_eos_vc3_mii100.mfg File for manually configuring the DS33M33 for EoS VC3 mode.
.\parallel_mode\m33_eopos_ds3.mfg File for manually configuring the DS33M33 for EoPoS DS3 mode.
.\parallel_mode\enc_dec_lb.mfg Encap/decap loopback/
.\parallel_mode\m30_rx_tx.mfg M30 mode Rx and Tx configuration. This file configures the MAC for GMII mode and requires a Gigabit Ethernet link.
.\parallel_mode\norm_ds3154_dlb.mfg
.\parallel_mode\m33_pos_au3_liu.mfg Two files for configuring the LIU in M33 mMode and configuring the DS33M33 in PoS AU3 mode.
.\ spi_mode.zip Configuration mode files for SPI™ 3-wire bus mode. The default mode for this demo kit is parallel mode. To avoid accidental use the SPI mode files have been provided in a zip format.
.\ ParitalConfig_DS33M_100mBit.mfg
.\ ParitalConfig_DS33M_GigaBit.mfg Files to change Ethernet speed in the MAC and Global Ethernet section.
SPI is a trademark of Motorola, Inc.
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4. Basic Operation
Note: In the following sections, software-related items are identified by bolding. Text in bold refers to items directly from the EV kit software. Text in bold and underlined refers to items from the Windows operating system.
4.1 Powering Up the Demo Kit • Connect PCB power jack to the wall adapter. • Connect RS232 serial cable, or USB cable between the host PC and demo kit. • Verify that the jumpers are configured as described in Table 5-1.
4.1.1 General
• Upon power-up the power LEDs (DS30, DS31, DS32 green) will be lit. Note that with DS33M3301A0 board revision, the LED DS31 will be red when power conditions are correct.
• PHY LINK LED should be lit if an Ethernet cable is connected. Following are several basic system initializations.
4.2 Basic DS33M33 Initialization This section covers two basic methods for configuring the DS33M33.
1. Device Driver-Based Configuration: (Note: The DS33M3302A0 board revision does not come loaded with device drivers). If the pins J20.1+J20.2 are Jumpered the device driver will auto configure the DS33M33 upon power-up. This enables traffic to pass from the Ethernet port to the serial port. Consult the device driver documentation for further details. To load the GUI interface for the device drivers, go to the ChipView register mode Tools menu and select Tools→Plugins→DS33M30/M33 Device Driver Demo.
2. Register-Based Configuration: EoS VC3 with two ports assigned to VCG1. a. Remove jumper J20.1+J20.2 to disable device drivers, and reset the board. b. Launch ChipView.exe and select Register View. c. When prompted for a definition file, pick the file named _DS33M33_GlobalMicroport.def. Several
additional definition files will load. d. Go to the File menu and select File→Memory Config File→Load .MFG file. When prompted,
select the file named m33_eos_vcg0_port2_port3_mii.mfg.
4.2.1 Additional Configuration for DS33M33
• Using either a patch or crossover cable, connect the Ethernet connector to an ordinary PC or network test equipment. This should cause the link LED to turn on.
• Place a loopback connector at the SONET network side; the optical LOS LEDs should go out. • At this point any packets sent to the DS33M33 are echoed back. Incoming packets (i.e., ping) should
cause the Activity LED to blink. • Note that ChipView.exe display settings can be changed using the Options→Settings menu.
4.3 Monitor and Capture Ethernet Traffic • Although ping is mentioned, it is not the recommended frame source for testing. The ping command goes
through the computer’s TCPIP stack, and sometimes is not sent out the PC’s network connector (i.e., if the PC’s ARP cache is out of date). Additionally, ping requires two PCs, as a Windows PC with only one adapter cannot ping itself (i.e., a local ping gets sent to local host instead of out the connector). With that said, ping is still a valuable test once the prototyping stage is complete.
• Generation and capture of arbitrary (raw) packets can be accomplished using CommView. A time-limited demo is available at www.tamos.com/products/commview.
• Wireshark (formerly Ethereal) is a free packet capture utility. Download is available at www.wireshark.org. • Adding additional Ethernet ports to a PC is rather simple when a USB-to-Ethernet adapter is used. This
allows for end-to-end testing using a single PC. When using two adapters, the PC has a different IP address for each adapter. Test equipment allows selection of either adapter. Operating system-based
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network traffic is sent out the default adapter, which usually is the adapter that has recently had connection to a live network.
5. Jumpers and Connectors
Jumpers and connectors are listed in Table 5-1. They are listed in order of appearance on the PCB from left to right, top to bottom (as viewed with SONET connectors port on the left side of the board).
Table 5-1. Jumpers and Connectors SILKSCREEN REFERENCE FUNCTION BASIC
SETTING SCHEMATIC
PAGE DESCRIPTION
J05 Overhead Test Points J05.5+J05.6 Jumpered 2
Jumpers to connect overhead CPLD to DS33M33. Connector is marked to show that the odd numbered pins belong to the CPLD.
J02 Spare Connector Not used 23 Spare pins connected to overhead CPLD.
J08 Overhead Test Points — 2
Jumpers to connect overhead CPLD to DS33M33. Connector is marked to show that the odd numbered pins belong to the CPLD.
JB01 (bottom of PCB) JTAG — 24 CPLD JTAG header.
Jumper P2+1 (low) P2+1 (low)
26
If auto negotiation is enabled, this setting advertises capability for 10/100/1000 speeds. If auto negotiation is disabled, then this setting forces 10Mb mode.
Jumper P2+3 (high) P2+3 (high)
26
If auto negotiation is enabled this setting advertises capability for 10/100 speeds. If auto negotiation is disabled, this setting is not legal.
JP05 + JP02 Bias PHY Speed1 + Speed0
Jumper P2+3(high) P2+1 (low)
26
If auto negotiation is enabled, this setting advertises capability for 1000 speeds. If auto negotiation is disabled, this setting forces 1000Mb mode.
Note: In Gigabit mode the DS33M33 Mac must be configured with indirect Mac register MACCR bit 15 set.
JP03 Bias PHY ANEN Jumper P2+3 (high) 26 Jumper P2+3 to enable auto
negotiation.
JP04 Bias PHY Duplex Jumper P2+3 (high) 26 Jumper P2+3 to enable full duplex;
jumper P1.2 to force half duplex.
JP06 Bias PHY ManMDIX Jumper P2+1 (high) 26
Default MDIX setting P2+3 PHY is set to straight mode; P2+1 PHY is in crossover mode.
JP07 Bias PHY NonIEEE Jumper P2+3 (high) 26 Jumper P2+3 to enable IEEE
compliant operation.
JP08 Bias PHY MultiEn Jumper P2+1 (high) 26
PHY advertisement setting. P2+3 selects multiple node priority (switch or hub); P1+2 selects single node priority (NIC).
JP09 Bias PHY MdixEn Jumper P2+1 (high) 26 P2+3 disables pair swap mode,
P2+1 enables pair swap mode
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SILKSCREEN REFERENCE FUNCTION BASIC
SETTING SCHEMATIC
PAGE DESCRIPTION
JP10 Bias PHY MacClkEn Jumper P2+3 (low) 26
P2+3 PHY clock to mac output is disabled, P1+2 PHY clock to mac output is enabled. Mac clock only needs to be enabled in Gigabit mode.
DS14 LED activity — 26 Flashes for PHY Tx-Rx activity.
DS15 DS16 DS17
LED link speed 1 of the 3
should be lit (when linked)
26
LED to indicate link speed–1000, 100, or 10Mbps. Only one of the three LEDs should be lit. See JP05 + JP02 description for setting in GMII vs. MII mode.
DS18 LED duplex — 25 LED is on in full-duplex mode.
JB03 JB02 PHY Test Points — 19
PHY test points. The connector pinout is compatible with existing PHY cards, but cannot be used with U04 on the board.
J16 JTAG Jumper J16.1+J16.3 8 DS33M33 JTAG.
J20 Runtime options NA 1 Currently the device drivers do not fit in flash, and are not loaded to the DK.
J31 JTAG — 31 FPGA JTAG.
JP25 JP26 Comm Port
Jumper P1+2 P1+2
15
Jumper pins 1+2 to select the RS232 transceiver. Jumper pins 2+3 to select the USB to serial converter.
SW01 Reset — 11 System reset button. J21 Test Points — 8 Databus test points, pins D0–D15
J24 Test Points — 8 Address bus test points pins A0–A13.
J23 Test Points — 8 Test points for DS33M33 CS, WR RD, and INT.
JP22 JP21 JP20
SPI Bias SWAP CPHA CPOL
Jumper P1+2 8
Jumper pins 2+1 to connect to processor parallel databus. Leave jumper off to pull pin low, jumper pins 2+3 to pull pin high.
JP14 JP13 JP12 JP11
SPI connection CS
MISO MOSI SCK
Jumper P1+2 8
Jumper Pins 2+1 to connect to parallel databus. Jumper pins 2+3 to connect to SPI port.
J30
Pin Bias IFSEL_SIZE
IFSEL_STYLE SPISEL
HIZ DCESEL RMIISEL
ALE
Jumper IFSEL_STYLE
HIZ_N (parallel mode)
8 Jumper to pull high, leave jumper off to pull low.
J19 Clock select Jumper P2+4 6 Clock selection for PHY and Ethernet side of DS33M33.
JP01 Clock select Jumper P1+2 6 Clad clock selection, jumper P1+2 to drive with 19.44MHz. Jumper P2+3 to drive with 77.76MHz clock.
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SILKSCREEN REFERENCE FUNCTION BASIC
SETTING SCHEMATIC
PAGE DESCRIPTION
J09 J10
SerDes analog test points — 3, 4
Test points to view analog +- differential SerDes signals. To loopback DS33M33 Tx→Rx remove the SFP and jumper P3+5 and P2+6.
J03 J04 SFP test points Jumper P9+10 3 Test points for SFP module.
DS02 DS03 SFP MOD0 — 3 Lit when a SFP module is installed.
DS08 DS09 SFP TXDISABLE — 3 Lit when Tx is enabled.
DS05 DS04 SFP LOS — 3 Lit when fiber optic cable is
removed.
J06 J07 SFP LOS / M33 LOS Jumper P2+3 3, 4
Jumper P2+3 to connect SFP LOS to DS33M33 LOS. Jumper P2+4 to pull DS33M33 high. Jumper P2+6 to pull DS33M33 low.
U03 SFP Installed 3, 4 Primary SFP module. U02 SFP Not Installed 3, 4 Redundant SFP module. J33 Software Debug — 15 ONcE EBDI. J32 JTAG — 20 LIU JTAG. J13 J15 J18
RCLK RNEG RPOS
Jumpered 9 LIU-to-DS33M33 connections.
J13 J15 J18
TCLK TNEG TPOS
Jumpered 9 LIU-to-DS33M33 connections.
JP16 JP23 JP24
LIU Port Clocks Not used 9 Jumper 1+2 to drive TCLKn with OscSel. Jumper 2+3 to drive TCLKn with RCLKn.
J22 J25 J26 J27
JB05 JB06 J28 J29
RX3 TX3 RX1 TX1
RX4 (bottom of PCB) TX4 (bottom of PCB)
RX2 TX2
— 8 Rx Tx jumpers.
JP17 LIU_T3MCLK Jumper P2+3 20
Jumper P2+3 to drive with T3 Osc. Jumper P1+2 to drive with T3_MCLK_IO.
JP18 LIU_ALT_MCLK Jumper P2+3 20
Jumper P2+3 to drive with Osc Sel. Jumper P1+2 to drive with Alternate MCLK.
JP19 LIU_E3MCLK Jumper P2+3 20
Jumper P2+3 to drive with E3 Osc. Jumper P1+2 to drive with E3_MCLK_IO.
JP15 Osc Select Jumper P2+3 20 Jumper P2+3 to drive with T3 Osc.
Jumper P1+2 to drive with E3 Osc.
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6. Line-Side Connections
The DS33M33DK has two optical ports: one Ethernet port and three T3E3 ports.
7. System Connectors
System-side signals can be accessed from test point headers. The headers are clearly labeled with signal information.
8. Microcontroller
The microcontroller has factory-installed firmware in on-chip nonvolatile memory. This firmware translates memory access requests from the RS-232 serial port into register accesses on the DS33M33 and the FPGAs.
9. Power-Supply Connectors
Connect a 5.0V wall adapter to the PCB power jack. LED DS1 provides indications that a 5.0V supply is connected properly. The board power supplies (3.3V, 2.5V, and 1.8V) are regulated to supply proper voltages to various circuits on the board.
10. Connecting to a Computer
Both USB and serial modes are supported.
To connect through a RS-232 serial port, set jumpers JP25 and JP26 jumpers to pins 1+2, identified in the silkscreen as UART,PROC. Connect a standard DB-9 serial cable between the serial port on the DS33M33DK and an available serial port on the host computer. The host computer must be a Windows-based PC. Be sure the cable is a standard straight-through cable rather than a null-modem cable. Null-modem cables prevent proper operation.
To connect through USB, set jumpers JP25 and JP26 jumpers to pins 3+2, identified in the silkscreen as USB,PROC. Connect a USB cable between the DS33M33DK USB connector and the PC. The host computer must be a Windows-based PC, which should automatically recognize the device as a virtual com port and assign the device drivers. If drivers are not automatically assigned, direct the New Hardware wizard to the driver files on the CD in the folder marked USBdrivers_CP210x.
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11. Installing and Running the Software
ChipView is a general-purpose program that supports a number of Maxim demo kits. To install the ChipView software, run Chipview.msi from the disk included in the DS33M33DK box or from the zip file downloadable on our website at www.maxim-ic.com/DS33M33DK.
After installation, run the ChipView program with the DS33M33DK board powered up and connected to the PC. If the default installation options were used, one easy way to run ChipView is to click the Start button on the Windows toolbar and select Programs→ChipView→ChipView. In the opening screen, click the Register View button. Select the correct serial port in the Port Selection dialog box, then click OK.
Next, the Definition File Assignment window appears. This window has subwindows to select definition files for up to four separate boards on other Maxim evaluation platforms. In the active subwindow, select the _DS33M_GlobalSonet.def definition file from the list shown, or browse to find it in another directory. Press the Continue button.
After selecting the definition file, the main part of the ChipView window displays the DS33M33’s register map. To select a register, click on it in the register map. When a register is selected, the full name of the register and its bit map are displayed at the bottom of the ChipView window. Bits that are logic 0 are displayed in white, while bits that are logic 1 are displayed in green.
The ChipView software supports the following actions:
• Toggle a bit. Select the register in the register map and then click the bit in the bit map. • Write a register. Select the register, click the Write button, and enter the value to be written. • Write all registers. Click the Write All button and enter the value to be written. • Read a register. Select the register in the register map and click the Read button. • Read all registers. Click the Read All button.
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12. Address Map
Address space begins at 0x81000000. All offsets given in the following tables are relative to 0x81000000. Registers in the FPGA can be easily modified using the ChipView host-based user interface software along with the definition file named Overhead_FPGA.def.
Table 12-1. Address Map
OFFSET DEVICE DESCRIPTION 0X6000 FPGA Overhead CPLD and Clock/Signal Routing 0X4000 DS3154 DS3154 Line Interface Unit 0X0000 DS33M33 DS33M33 Registers
12.1 Overhead CPLD Register Map
Table 12-2. Register Map for Overhead CPLD (Reference Designator U01)
OFFSET REGISTER NAME TYPE DESCRIPTION
0X0001 ATOH_CFG Control ATOH Configuration 0X0002 ATOHEN_CFG Control ATOHEN Configuration 0X0003 GPIOAwr Control GPIO A Output Enable + Write Value 0X0004 GPIOBwr Control GPIO B Output Enable + Write Value 0X0005 DTOH_STAT Read-Only DTOH Status 0X0006 DTOH_SEL Control DTOH Configuration 0X0007 GPIOrd_STAT Read-Only GPIO Read Values 0X0008 RDOH_STAT Read-Oonly RDOH Status 0x000A RDOH_SEL Control RDOH Select 0x000D TAOH_CFG Control TAOH Configuration 0x000F TAOHen_CFG Control TAOHen Configuration
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12.2 Control and Status Registers Register Name: ATOH_CFG Register Description: ATOH Configuration Register Offset: 0x0001 Bit # 7 6 5 4 3 2 1 0 Name Default 0 0 0 0 0 0 0 0 This register sets the overhead transport data byte value, which is positioned by the following register, ATOHEN_CFG.
Register Name: ATOHEN_CFG Register Description: ATOHEN Configuration Register Offset: 0x0002 Bit # 7 6 5 4 3 2 1 0 Name Default 0 0 0 0 0 0 0 0 Byte enable for overhead transport byte, the data value in ATOH_CFG is positioned in the overhead as specified by ATOHEN_CFG. Examples follow:
ATOHEN_CFG ATOH_CFG RESULT 0 NA Data is not written onto the overhead when ATOHEN_CFG = 0.
0x01 0x54 Data value 0x54 is written onto the first byte of the transport overhead. 0x81 0x54 Data value 0x54 is written onto the last byte of the transport overhead. 0x## 0xNN Data value 0xNN is written to the 0x## byte of the transport overhead.
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Register Name: GPIOAwr Register Description: GPIO A Output Enable + Write Value Register Offset: 0x0003 Bit # 7 6 5 4 3 2 1 0 Name — — GPIOa3
Output En GPIOa3 Value
GPIOa2 Output En
GPIOa2 Value
GPIOa1 Output En
GPIOa1 Value
Default 0 0 0 0 0 0 0 0 Bits 5 and 4: DS33M33 GPIOA_3 Three-State and Level
0x = FPGA three-states GPIOA_3 pin 00 = FPGA drives GPIOA_3 pin with 0.0V 01 = FPGA drives GPIOA_3 pin with 3.3V
Bits 3 and 2: DS33M33 GPIOA_2 Three-State and Level
0x = FPGA three-states GPIOA_2 pin 00 = FPGA drives GPIOA_2 pin with 0.0V 01 = FPGA drives GPIOA_2 pin with 3.3V
Bits 1 and 0: DS33M33 GPIOA_1 Three-State and Level
0x = FPGA three-states GPIOA_1 pin 00 = FPGA drives GPIOA_1 pin with 0.0V 01 = FPGA drives GPIOA_1 pin with 3.3V
Register Name: GPIOBwr Register Description: GPIO B Output Enable + Write Value Register Offset: 0x0004 Bit # 7 6 5 4 3 2 1 0 Name — — GPIOb3
Output En GPIOb3 Value
GPIOb2 Output En
GPIOb2 Value
GPIOb1 Output En
GPIOb1 Value
Default 0 0 0 0 0 0 0 0 Bits 5 and 4: DS33M33 GPIOB_3 Three-State and Level control
0x = FPGA three-states GPIOB_3 pin 00 = FPGA drives GPIOB_3 pin with 0.0V 01 = FPGA drives GPIOB_3 pin with 3.3V
Bits 3 and 2: DS33M33 GPIOB_2 Three-State and Level control
0x = FPGA three-states GPIOB_2 pin 00 = FPGA drives GPIOB_2 pin with 0.0V 01 = FPGA drives GPIOB_2 pin with 3.3V
Bits 1 and 0: DS33M33 GPIOB_1 Three-State and Level control
0x = FPGA three-states GPIOB_1 pin 00 = FPGA drives GPIOB_1 pin with 0.0V 01 = FPGA drives GPIOB_1 pin with 3.3V
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Register Name: DTOH_STAT Register Description: DTOH Status Register Offset: 0x0005 Bit # 7 6 5 4 3 2 1 0 Name STAT7 STAT6 STAT5 STAT4 STAT3 STAT2 STAT1 STAT0 Default 0 0 0 0 0 0 0 0 Read value of 1 of 81 bytes selected by DTOH_SEL. Register Name: DTOH_SEL Register Description: DTOH Configuration Register Offset: 0x0006 Bit # 7 6 5 4 3 2 1 0 Name SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 Default 0 0 0 0 0 0 0 0 Byte select for overhead transport byte, the overhead byte specified by DTOH_CFG is written to DTOH_STAT. Examples:
DTOH_SEL DTOH_STAT RESULT 0 First byte The first byte of the transport overhead is written to DTOH_STAT.
0x80 Last byte The last byte of the transport overhead is written to DTOH_STAT. Register Name: GPIOrd_STAT Register Description: GPIO Read Values Register Offset: 0x0007 Bit # 7 6 5 4 3 2 1 0 Name — GPIOA3 GPIOA2 GPIOA1 — GPIOB3 GPIOB2 GPIOB1 Default 0 0 0 0 0 0 0 0 Bit 6: DS33M33 GPIOA3 Pin Value Reflects the value of DS33M33 GPIOA3 pin. Bit 5: DS33M33 GPIOA3 Pin Value Reflects the value of DS33M33 GPIOA2 pin. Bit 4: DS33M33 GPIOA3 Pin Value Reflects the value of DS33M33 GPIOA1 pin. Bit 2: DS33M33 GPIOA3 Pin Value Reflects the value of DS33M33 GPIOB3 pin. Bit 1: DS33M33 GPIOA3 Pin Value Reflects the value of DS33M33 GPIOB2 pin. Bit 0: DS33M33 GPIOA3 Pin Value Reflects the value of DS33M33 GPIOB1 pin.
_________________________________________________________________________________________________ DS33M33DK
Rev: 102108 15 of 48
Register Name: RDOH_STAT Register Description: RDOH Status Register Offset: 0x0008 Bit # 7 6 5 4 3 2 1 0 Name — — — — — — — — Default 0 0 0 0 0 0 0 0 Read value from the member and byte selected by RDOH_SEL[7:4] and RDOH_SEL[3:0]
Register Name: RDOH_SEL Register Description: RDOH Select Register Offset: 0x000A Bit # 7 6 5 4 3 2 1 0 Name IF3 IF2 IF1 IF0 B3 B2 B1 B0 Default 0 0 0 0 0 0 0 0 Bits 7 to 4: Overhead interface Member Select. Writing IF[3:0] to a value of 0 disables. Writing 1 to 10 selects among the 10 members used in RDOH_STAT.
Bits 3 to 0: Byte Select. Writing B[3:0] to a value of 0-to-N selects the Nth byte in the member selected.
Register Name: TAOH_CFG Register Description: TAOH Configuration Register Offset: 0x000D Bit # 7 6 5 4 3 2 1 0 Name RCLK8 RCLK7 RCLK6 RCLK5 RCLK4 RCLK3 RCLK2 RCLK1 Default 0 0 0 0 0 0 0 0 Value to be written to the member and byte selected by TAOHen_CFG[7:4] and TAOHen_CFG [3:0]
Register Name: TAOHen_CFG Register Description: TAOH Enable Configuration Register Offset: 0x000F Bit # 7 6 5 4 3 2 1 0 Name IF3 IF2 IF1 IF0 B3 B2 B1 B0 Default 0 0 0 0 0 0 0 0 Bits 7 to 4: Overhead interface Member Select. Writing IF[3:0] to a value of 0 disables. Writing 1 to 10 selects among the 10 members used in TAOH_STAT.
Bits 3 to 0: Byte Select. Writing B[3:0] to a value of 0-to-N selects the Nth byte in the member selected.
_________________________________________________________________________________________________ DS33M33DK
Rev: 102108 16 of 48
13. Additional Information/Resources
13.1 DS33M33 Information For more information about the DS33M33, refer to the DS33M33 data sheet at www.maxim-ic.com/DS33M33.
13.2 DS33M33DK Information For more information about the DS33M33DK, refer to the DS33M33DK Quick View page at www.maxim-ic.com/DS33M33DK.
13.3 Technical Support For additional technical support, submit your questions at www.maxim-ic.com/support.
_________________________________________________________________________________________________ DS33M33DK
Rev: 102108 17 of 48
14. Component List DESIGNATION QTY DESCRIPTION SUPPLIER PART
C08, CB34, CB36, CB37, CB38, CB39, CB40, CB41, CB42, CB58, CB64, CB66, CB67, CB68, CB72,
CB79, CB92, CB101, CB104, CB112, CB170
21 L_0603 CERAM .01uF 50V 10% X7R AVX 06035C103KAT
See next row (begins with C02) 61 L_0603 CERAM .1uF 16V 20% X7R AVX 0603YC104MAT
C02, C04, C05, C07, C10, C15, C18, CB05, CB06, CB09, CB10, CB11, CB12, CB16, CB21, CB22, CB23, CB25, CB28, CB33, CB43, CB44, CB45, CB47, CB53, CB54, CB63, CB65, CB69, CB77, CB83, CB85, CB88, CB89, CB94, CB95, CB97,
CB98, CB113, CB115, CB116, CB118, CB122, CB126, CB128, CB134, CB135, CB137, CB138, CB140, CB142, CB143, CB144, CB146, CB148, CB156, CB160, CB168, CB177, CB186, CB187
DB01 1 SCHOTTKY DIODE, 1 AMP 40 VOLT International Rectifier 10BQ040
DS01, DS06, DS07, DS10, DS11, DS12, DS13, DS31 8 LED, RED/GREEN, SMD LITEON 160-1172-1-ND
GND_TP01, GND_TP02, GND_TP03, GND_TP04,
GND_TP11, GND_TPB01, GND_TPB02, GND_TPB03,
GND_TPB06
9 STANDARD GROUND CLIP KEYSTONE 4954
DS14, DS15, DS16, DS17 4 LED, GREEN/GREEN, SMD LUMEX 67-1362-1-ND J34 1 L_CONN, DB9 RA, LONG CASE AMP 747459-1
UB02, UB04, UB06 3 SPI SERIAL EEPROM 2M 8 PIN SOIC 2.7V to 3.6V Atmel AT25F2048N-
10SU-2.7
RPB24, RPB26 2 RESISTOR, 4 PACK, 50 OHM 2PCT QUAD 0603 KOA CN1J4TTD500G
U10 1 IC, SINGLE-CHIP USB TO UART BRIDGE, 28 PIN QFN SIL CP2101
J32 1 L_TERMINAL STRIP, 10 PIN, DUAL ROW, VERT DO NOT POPULATE DNP DNP
U04 1 GIG PHYTER V, 10/100/1000 ETHERNET PHYSICAL LAYER, 128 PIN QFP
National Semiconductor DP83865DVH
U07 1 QUAD DS3/E3/STS1 LIU 144P BGA Maxim DS3154
U05 1 IC, ETHERNET OVER SDH/SONET (EoS), -40C TO 85C, 256-PIN CSBGA Maxim DS33M33N
XB01 1 XTAL LOW PROFILE 8.0MHZ ECL EC1-8.000M
See next row (begins with C01) 79 0603 CERAM 4.7uF 6.3V MULTILAYER Digi-Key ECJ-1VB0J475M
C01, C03, C06, C09, C11, C12, C13, C14, C16, C23, CB03, CB04, CB07, CB14, CB15, CB17, CB18, CB19, CB20, CB24, CB26, CB27, CB29, CB30, CB31, CB32, CB46, CB49, CB55, CB60, CB62, CB70, CB73, CB74, CB75, CB76, CB78, CB82, CB84, CB86, CB90, CB91, CB93, CB96, CB100, CB102, CB103, CB106, CB107, CB109, CB110, CB114, CB117, CB119, CB120, CB121, CB123, CB127, CB129, CB131, CB132, CB133, CB136, CB139, CB141, CB147, CB150, CB153, CB154,
CB162, CB163, CB165, CB167, CB173, CB175, CB181, CB182, CB183, CB190
See next row (begins with CB50) 20 0603 CERAM .1uF 16V 10% Panasonic ECJ-1VB1C104K
_________________________________________________________________________________________________ DS33M33DK
Rev: 102108 18 of 48
CB50, CB56, CB57, CB61, CB71, CB80, CB81, CB87, CB99, CB105, CB108, CB149, CB151, CB152, CB155, CB161, CB166, CB172, CB179, CB180
See next row (begins with C17) 21 1206 CERAM 10uF 10V 20% Panasonic ECJ-3YB1A106M
C17, C19, C20, C21, C22, C24, CB188 , CB01, CB02, CB08, CB13, CB35, CB48, CB51, CB52, CB59, CB111, CB124, CB125, CB130, CB169
CB164, CB184 2 L_1206 CERAM 1uF 16V 10% Panasonic ECJ-3YB1C105K CB178 1 1206 CERAM 4.7uF 25V 10% X5R Panasonic ECJ-3YB1E475K
CB158, CB159, CB185, CB189 4 L_D CASE TANT 68uF 16V 20% Panasonic ECS-T1CD686R
RB09, RB10 2 RES 0603 100 Ohm 1/16W 1% Panasonic ERJ-3EKF1000V RB12, RB13 2 RES 0603 1.00K Ohm 1/16W 1% Panasonic ERJ-3EKF1001V
RB17, RB19, RB20, RB21, RB22, RB23, RB24, RB25 8 RES 0603 332 Ohm 1/16W 1% Panasonic ERJ-3EKF3320V
RB16 1 RES 0603 9.76K Ohm 1/16W 1% Panasonic ERJ-3EKF9761V R02, R04, R05, RB04, RB27 5 RES 0603 0.0 Ohm 1/16W 5% Panasonic ERJ-3GEY0R00V RB01, RB02, RB29 , RB05 4 L_RES 0603 10K Ohm 1/16W 5% Panasonic ERJ-3GEYJ103V
R03 1 RES 0603 1.0M Ohm 1/16W 5% Panasonic ERJ-3GEYJ105V R01, RB06, RB11 3 RES 0603 2.0K Ohm 1/16W 5% Panasonic ERJ-3GEYJ202V
RB08 1 RES 0603 2.2K Ohm 1/16W 5% Panasonic ERJ-3GEYJ222V RB14, RB15 2 RES 0603 30 Ohm 1/16W 5% Panasonic ERJ-3GEYJ300V
RB07, RB26 , RB28, RB30 4 RES 0603 330 Ohm 1/16W 5% Panasonic ERJ-3GEYJ331V RB03, RB18 2 RES 0805 10K Ohm 1/10W 1% Panasonic ERJ-6ENF1002V
SW01 1 SWITCH MOM 4PIN SINGLE POLE Panasonic EVQPAE04M
RPB18 1 RESISTOR, 4 PACK, 100 OHM 5PCT QUAD 0603 Panasonic EXB-V8V101JX
RPB01, RPB02, RPB05, RPB14, RPB20, RPB30, RPB36, RPB48,
RPB52 9 RESISTOR, 4 PACK, 1K OHM 5PCT
QUAD 0603 Panasonic EXB-V8V102JX
RPB03, RPB08, RPB10, RPB11, RPB12, RPB13, RPB29, RPB32, RPB33, RPB40, RPB41, RPB43, RPB45, RPB47, RPB49, RPB50, RPB51, RPB54, RPB55, RPB56, RPB57, RPB58, RPB60, RPB61,
RPB62, RPB63, RPB64
27 RESISTOR, 4 PACK, 10K OHM 5PCT QUAD 0603 Panasonic EXB-V8V103JX
RPB19, RPB21, RPB28 3 RESISTOR, 4 PACK, 2.2K OHM 5PCT QUAD 0603 Panasonic EXB-V8V222JX
RP02, RP03, RP04, RP05, RP06, RP07, RP08, RP09, RP10, RP11,
RP12, RP13, RPB15, RPB16, RPB17, RPB23, RPB25, RPB27, RPB31, RPB34, RPB35, RPB37,
RPB44
23 RESISTOR, 4 PACK, 30 OHM 5PCT QUAD 0603 Panasonic EXB-V8V300JX
RP01, RPB04, RPB06, RPB07, RPB09, RPB22, RPB38, RPB39, RPB42, RPB46, RPB53, RPB59
12 RESISTOR, 4 PACK, 330 OHM 5PCT QUAD 0603 Panasonic EXB-V8V331JX
L01, L02, LB01, LB02, LB03, LB04 6 1uH ±10% 0805 Multilayer Ceramic
400 mA TDK GLF2012T1R0M
_________________________________________________________________________________________________ DS33M33DK
Rev: 102108 19 of 48
J01, J30 2 HEADER, 14 PIN, DUAL ROW, VERT Samtec HDR-TSW-107-14-T-D
J11 1 CONNECTOR, SINGLE LEVEL, GIGABIT RJ-45, 10 PIN
Halo Electronics HFJ11-1G02E
U08 1 IC, FPGA, 1.2V, 20X20 TQFP, 144 PIN LAT LFE2-6E-5TN144C
U01 1 IC, FPGA, 1.2V, 20X20 TQFP, 144 PIN LAT LFEC3E-3T144C
DS04, DS05, DS28 , DS19, DS20, DS21, DS22, DS23, DS24, DS25,
DS26, DS27 12 L_LED, RED, SMD Panasonic LN1251C
DS02, DS03, DS08, DS09, DS29 , DS18, DS30, DS32 8 L_LED, GREEN, SMD Panasonic LN1351C
UB09 1 IC, LINEAR REG 1.5W, 1.8V or Adj, 1A, 16TSSOP-EP Maxim MAX1793EUE-18
UB08 1 IC, LINEAR REG 1.5W, 2.5V or Adj, 1A, 16TSSOP-EP Maxim MAX1793EUE-25
UB10, UB11, UB13 3 IC, LINEAR REG 1.5W, 3.3V or Adj, 1A, 16TSSOP-EP Maxim MAX1793EUE-33
UB01, UB03 2 IC, LDO REGULATOR WITH RESET,1.20V OUTPUT 300 MA, 6 PIN SOT23
Maxim MAX1963EZT120-T
UB07 1 MICROPROCESSOR VOLTAGE MONITOR, 3.08V RESET, 4PIN SOT143
Maxim MAX811TEUS-T
U09 1 MMC2107 PROCESSOR Motorola MMC2107
J03, J04, J23 3 TERMINAL STRIP, 10 PIN, DUAL ROW, VERT Digi-Key S2012-05-ND
J33 1 100 MIL 2*7 POS JUMPER NA NA J35 1 TYPE B SINGLE RT ANGLE, BLACK Digi-Key WM17108-ND
JB08 1 100 MIL 2 POS JUMPER NA NA
See next row (begins with JP01) 27 100 MIL 3 POS JUMPER NA NA
JP01, JP02, JP03, JP04, JP05, JP06, JP07, JP08, JP09, JP10, JP11, JP12, JP13, JP14, JP15, JP16, JP17, JP18, JP19, JP20, JP21, JP22, JP23, JP24, JP25, JP26, JPB01
TPB01, TPB02, TPB03 3 TEST POINT, 1 PLATED HOLE, DO NOT STUFF NA NA
U06 1 DOUBLE DATA RATE (DDR) SDRAM 2-2-2 TIMING 256MBITX16 TSSOP MICRON MT46V16M16TG-
75E
U11, U12 2 CYPRESS SRAM 4Mbit*8 CYPRESS CY62148DV30L-70SXI
UB14 1 Dual RS-232 transceivers with 3.3V/5V internal capacitors MAXIM MAX3233E
JB02 1 TEST POINTS FOR SMD 50 PIN, 2 ROW VERTICAL NA NA_NOTPOPULAT
ED UB05 , UB12 2 HIGH SPEED INVERTER FAIRCHILD NC7SZ86
J24 1 NON POPULATED HEADER, 14 PIN, DUAL ROW, VERT Samtec NOPOP-HDR-TSW-
107-14-T-D
JB05, JB06 2 DO NOT POPULATE L_2 PIN HEADER, .100 CENTERS, VERTICAL Samtec NOPOP-TSW-102-
07-T-S
J09, J10 2 TERMINAL STRIP, 6 PIN, DUAL ROW, VERT NOT POPULATED Samtec NOPOP-TSW-103-
07-T-D
J21 1 NOPOP TERMINAL STRIP, 16 PIN, DUAL ROW, VERT Samtec NOPOP-TSW-108-
07-T-D
YB04 1 OSCILLATOR, CRYSTAL CLOCK, 5.0V - 34.368 MHZ SaRonix NTH089AA-34.368
YB05 1 SOCKETED OSCILLATOR, CRYSTAL CLOCK, 3.3V - 25.000 MHZ SaRonix NTH089AA3-
25.000+SOCKET
YB03 1 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 44.736 MHZ SaRonix NTH089AA3-44.736
_________________________________________________________________________________________________ DS33M33DK
Rev: 102108 20 of 48
JB09 1
CONN 2.1MM/5.5MM PWRJACK RT ANGLE PCB, closed frame, high current 24VDC@5A also requires 5V ACDC adapter INPUT 100-240VAC 50-60HZ 0.6A OUTPUT DC 5V 2.6A. PN DMS050260-P5P-SZ. MODEL 3Z-161WP05
CUI, INC PJ-002AH
JB03 1 PLUG, SMD, 50 PIN, 2 ROW VERTICAL Samtec SFM-125-L2-S-D-LC
U02, U03 2 SFP host / receptacle PARTS_KIT SFP_HOST-TYCO
HB01, HB02, HB03, HB04, HB05 5 Rubber bumper 0.5 inch NA SJ5518-0
YB01 1 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 19.44 MHZ SaRonix SOCKET+NTH089A
3-19.44
YB02 1 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 77.76 MHZ SaRonix SOCKET+NTH089A
3-77.7600
T01 1 XFMR, OCTAL T3/E3, 1 TO 2, SMT 32 PIN Pulse T3049
CB145, CB157, CB171, CB174, CB176 5 D CASE TANT 470uF 6.3V 20% KEM T491D477M006AS
J22, J25, J26, J27, J28, J29 6 L_2 PIN HEADER, .100 CENTERS, VERTICAL Samtec TSW-102-07-T-S
J06, J07, J12, J13, J14, J15, J17, J18, J19, J20, JB04, JB07 12 TERMINAL STRIP, 6 PIN, DUAL
ROW, VERT Samtec TSW-103-07-T-D
J16, J31, JB01 3 L_TERMINAL STRIP, 10 PIN, DUAL ROW, VERT Samtec TSW-105-07-T-D
J02, J05, J08 3 TERMINAL STRIP, 16 PIN, DUAL ROW, VERT Samtec TSW-108-07-T-D
_________________________________________________________________________________________________ DS33M33DK
Rev: 102108 21 of 21 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products , 120 San Gabrie l Dr ive , Sunnyvale , CA 94086 408-737-7600 © 2008 Maxim Integrated Products
15. Schematics
The DS33M33DK schematics are featured in the following pages. The schematic contains five hierarchal blocks: Microcontroller, DS3154, Ethernet PHY, Ethernet Test Points, and Overhead CPLD.
All signals inside a hierarchy block are local, with exception for VCC and ground. In-port and out-port connectors are used to allow signals inside a hierarchy block to become accessible as pins on the hierarchy blocks symbol. From here blocks are wired together as if they were ordinary components. Figure 15-1 shows the system diagram in terms of hierarchal blocks with schematic page numbers given for each functional block.
Figure 15-1. DS33M33 PCB Layout and Schematic Hierarchy Block Page Listing
µP BLOCK
PAGE 1 SYMBOL
SCHEMATIC PAGES 13-18
DS3154 LIU BLOCK PAGE 9 SYMBOL
SCHEMATIC PAGES 20-22
OVERHEAD CPLD PAGE 10 SYMBOL
SCHEMATIC PAGES 23-24
DS33M33
SCHEMATIC PAGES 1-10
POWER SUPPLY
SCHEMATIC PAGES 11-12
ETHERNET PHY PAGE 6 SYMBOL
SCHEMATIC
PAGES 19, 25-26
SONET SFP PAGES 4-5
LIU TEST POINTS PAGE 9
DDR PAGE 7
CLOCKS AND CONFIGURATION PAGES 6,8
is a registered trademark of Maxim Integrated Products.
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JT
CLK
JT
MS
JT
RS
T*
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
A[11]
A[12]
A[13]
V3_3
2 65
431
CO
NN
_6P
_U
_m
otp
rocre
scard
_dn
MIC
RO
PR
OC
ES
SO
RH
IER
AR
CH
YB
LO
CK
ALE
_D
UT
RD
_D
S
MIS
C_IO
<12..1>
WR
_R
W
EN
_S
OU
RC
E_T
IME
EN
AB
LE
_D
RV
SP
I_M
ISO
SP
I_S
CK
SP
I_C
S
SP
I_M
OS
I
A_D
UT
_<
13..0>
CS
_X
1
INT
2
D_D
UT
<7..0>
INT
3IN
T4
EN
AB
LE
_C
LB
K
CS
_X
2
CS
_X
3
RE
SE
T_IN
PR
OC
_O
SC
IN
RE
SE
T_O
UT
M3X
OH
_A
TO
H
M3X
OH
_A
TO
HS
OF
M3X
OH
_A
TO
HC
LK
CP
LD
_A
TO
H
CP
LD
_R
DO
HV
LD
CP
LD
_A
TO
HS
OF
CP
LD
_A
TO
HC
LK
CP
LD
_D
TO
H
CP
LD
_D
TO
HS
OF
CP
LD
_D
TO
HC
LK
CP
LD
_A
TO
HE
NM
3X
OH
_A
TO
HE
N
M3X
OH
_T
AO
HE
N
M3X
OH
_T
AO
HS
OF
M3X
OH
_T
AO
HV
LD
CP
LD
_O
H1
CP
LD
_O
HC
LK
CP
LD
_T
AO
HE
N
CP
LD
_T
AO
HS
OF
CP
LD
_T
AO
HV
LD
CP
LD
_R
DO
H
CP
LD
_R
DO
HS
OF
CP
LD
_T
AO
HM
3X
OH
_T
AO
H
M3X
_S
FP
2_R
DN
M3X
_S
FP
1_R
DN
M3X
_S
FP
2_T
DN
M3X
_S
FP
1_T
DP
M3X
_S
FP
1_T
DN
M3
X_
LO
S1
M3X
_LO
S2
M3X
_S
FP
2_T
DP
M3X
OH
_R
DO
HS
OF
M3X
OH
_R
DO
H
M3X
OH
_R
DO
HV
LD
M3X
OH
_O
HC
LK
M3
XO
H_
OH
1
M3X
OH
_A
TO
H
M3X
OH
_T
AO
H
M3X
OH
_T
AO
HE
N
M3X
OH
_A
TO
HE
N
M3X
OH
_D
TO
HS
OF
M3X
OH
_D
TO
H
M3X
OH
_D
TO
HC
LK
M3X
_S
FP
2_R
DP
M3X
_S
FP
1_R
DP
303030
100
100
30
100
.01U
F
.01U
F
.01U
F
.01U
F
30
RB
09
RB
10
U05
F13
G13
G14
F14
F12
G12
B15
M16
F16
K13
M14
K16
D16
J12
H14
J13
L16
E16
H13
J14
J15
K14
P16
H16
N16
G16
RP
B1
5
4321
5678
RP
B1
64321
5678
RP
04
4321
5678
RP
03
4321
5678
RP
B1
7
4321
5678
J08
12
34
56
78
910
1112
1314
1516
J05
12
34
56
78
910
1112
1314
1516
RP
B1
8
4321
5678C
B34
CB
37
CB
36
CB
40
ST
EV
ES
CU
LLY
2/1
2(B
LO
CK
)
10/0
3/2
007
2/2
6(T
OT
AL)
CR
-2:
@\_
RC
_LIB
\.\_
RC
_T
OP
_D
N_\(
SC
H_1):
PA
GE
2
DS
33M
33D
K01A
0O
VE
RH
EA
D.
P.2
,10
,23
-24
T3
E3
LIU
I/F
.P
.2,9
,20
-22
BLO
CK
NA
ME
:_rc
_to
p_dn_.
2A
610C
4
10B
7
10C
7
10C
7
10C
7
10C
7
10C
7
10C
42A
6
2A
6
10C
7
10C
7
10C
5
10B
7
10B
7
10C
7
10C
7
10C
52A
6
3C
63B
5
4C
64B
5
3C
53D
6
4C
54D
6
4C
54D
6
4B
6
3B
6
3C
53D
6
2B
6
2C
6
2C
6
2B
6
3D
63B
5
4C
64B
5
PA
GE
:
DA
TE
:T
ITLE
:
EN
GIN
EE
R:
AA
BB
CC
DD
112 2
334 4
556 6
778 8
DS
33M
33_U
OVERHEADI/F TRANSPORTOVERHEADI/F
STS-3SYSTEMI/F
RD
NB
RD
PB
RD
NA
RD
PA
TD
NB
TD
PA
TA
OH
OH
CLK
TD
NA
OH
1
TA
OH
SO
F
TA
OH
EN
TA
OH
VLD
RD
OH
RD
OH
SO
F
RD
OH
VLD
AT
OH
AT
OH
EN
AT
OH
SO
F
DT
OH
DT
OH
SO
F
DT
OH
CLK
AT
OH
CLK
LO
SA
LO
SB
TD
PB
CO
NN
_16P
2 4 8
10 12 14 16
31 7 9 11 13 1556
CO
NN
_16P
2 4 8
10 12 14 16
31 7 9 11 13 1556
MO
D0
ISG
RO
UN
DE
DIN
TH
ES
FP
PU
LLU
PS
FO
RO
PE
ND
RA
INP
INS
TH
ISS
UB
CIR
CU
ITIS
FO
RO
BS
ER
VA
TIO
NA
ND
LO
OP
BA
CK
ON
LY
NO
TF
OR
PR
OD
UC
TIO
NU
SE
PLA
CE
/R
OU
TE
CA
PS
AN
DT
ES
TP
OIN
T
SU
CH
TH
AT
TH
EY
CA
NR
EM
OV
ED
WIT
HO
UT
IMP
AC
T
SE
RV
ES
AS
DE
VIC
ED
ET
EC
T
SF
P2_R
AT
E
SF
P2_LO
S
SF
P2
_M
OD
1
SF
P2_T
X_F
AU
LT
SF
P2_M
OD
2
SF
P2_M
OD
0
10K
10K
M3X
_S
FP
2_R
DN
M3X
_S
FP
2_R
DP
M3X
_S
FP
2_T
DP
.1UF
4.7UF
1U
H
4.7UF
4.7UF
.1UF
1U
H
330
SF
P2_I2
C_C
LK
SF
P2_T
XD
ISA
BLE
SF
P2_V
CC
T
SF
P2_V
CC
R
SF
P2_T
X_F
AU
LT
SF
P2_I2
C_S
DA
SF
P2_D
EV
_D
ET
EC
T
SF
P2_LO
S
SF
P2_R
AT
E
SF
P2_M
OD
0
SF
P2_T
XD
ISA
BLE
SF
P2_M
OD
2
SF
P2
_M
OD
1
SF
P2_LO
S
SF
P2_D
EV
_D
ET
EC
T
SF
P2_I2
C_C
LK
SF
P2_I2
C_S
DA
SF
P2_V
CC
R
SF
P2_T
X_F
AU
LT
SF
P2_V
CC
T
SF
P2_R
AT
E
M3X
_S
FP
2_T
DN
M3X
_S
FP
2_T
DP
M3X
_S
FP
2_R
DP
M3X
_S
FP
2_R
DN
.01UF
.01UF
M3X
_S
FP
2_T
DN
1KM
3X
_LO
S2
SF
P2_LO
S
SF
P2_T
XD
ISA
BLE
SF
P2_LO
S
SF
P2_M
OD
0
RE
DG
RE
EN
GR
EE
N
CB33
CB31
LB
04
CB32
CB24
CB23
LB
02
J03
12
34
56
78
910
U02
212223242526272829
3031
8654 7
121319 1832
1516 14
109
11
12
0 17
DS
02
12
RP
B0
9
4321
5678
DS
08
12
DS
05
12
RP
B1
1
4321
5678
RP
B1
2
4321
5678
CB42
J09
12
34
56
CB39
J06
12
34
56
RP
B1
4
4321
5678
ST
EV
ES
CU
LLY
DS
33M
33D
K01A
0
3/1
2(B
LO
CK
)
10/0
3/2
007
3/2
6(T
OT
AL)
CR
-3:
@\_
RC
_LIB
\.\_
RC
_T
OP
_D
N_\(
SC
H_1):
PA
GE
3
SE
RD
ES
.P
.3-4
BLO
CK
NA
ME
:_rc
_to
p_dn_.
3B
23A
1
3B
73B
23A
53A
1
3B
3
3C
23A
3
3C
3
3B
33A
5
2B
23C
6
2B
23D
6
3D
62B
2
3B
2
3C
23A
5
3D
2
3D
3
3A
73C
2 3C
2
3B1
3B
73A
73A
53A
1
3A
73A
1
3A
73A
5
3A
53A
3
3A
7
3A
7
3B
73B
23A
73A
5
3A
3
3A
3
3A
3
3B
5
3A
73A
3
3B
5
3B
23A
7
3C
52C
2
3C
52B
2
2B
23B
5
2B
23B
5
3D
62C
2
2B
23B
23A
73A
53A
1
3C
23A
3
3B
73B
23A
73A
1
3B
33A
7
PA
GE
:
DA
TE
:T
ITLE
:
EN
GIN
EE
R:
AA
BB
CC
DD
112 2
334 4
556 6
778 8
V3_3
2 65
431
CO
NN
_6P
_U
V3_3
2 65
431
CO
NN
_6P
_U
V3_3
V3_3
SF
P_H
OS
T
CGNDCGNDCGNDCGNDCGNDCGNDCGNDCGND
CGNDCGNDCGND
VE
ER
RD
-
RD
+
VC
CT
VC
CR
VE
ER
TD
+
VE
ET
VE
ET
TD
-
VE
ER
VE
ER
LO
S
RA
TE
MO
D-D
EF
1
MO
D-D
EF
0
MO
D-D
EF
2
TX
_D
ISA
BLE
TX
_F
AU
LT
VE
ET
V3_3
6
10
84
12
3 5 7 9
CO
NN
_10P
PU
LLU
PS
FO
RO
PE
ND
RA
INP
INS
TH
ISS
UB
CIR
CU
ITIS
FO
RO
BS
ER
VA
TIO
NA
ND
LO
OP
BA
CK
ON
LY
NO
TF
OR
PR
OD
UC
TIO
NU
SE
PLA
CE
/R
OU
TE
CA
PS
AN
DT
ES
TP
OIN
T
SU
CH
TH
AT
TH
EY
CA
NR
EM
OV
ED
WIT
HO
UT
IMP
AC
T
MO
D0
ISG
RO
UN
DE
DIN
TH
ES
FP
SE
RV
ES
AS
DE
VIC
ED
ET
EC
T
SF
P1_M
OD
2
SF
P1
_M
OD
1
SF
P1_V
CC
R
M3X
_S
FP
1_R
DN
.1UF
4.7UF
1U
H
4.7UF
4.7UF
1U
H
330
SF
P1_R
AT
E
SF
P1_LO
S
SF
P1_V
CC
TS
FP
1_V
CC
R
SF
P1_I2
C_S
DA
SF
P1_T
XD
ISA
BLE
SF
P1_I2
C_C
LK
SF
P1_T
X_F
AU
LT
SF
P1_D
EV
_D
ET
EC
T
.1UF
SF
P1_D
EV
_D
ET
EC
T
SF
P1_I2
C_C
LK
SF
P1_I2
C_S
DA
SF
P1_T
X_F
AU
LT
SF
P1_T
XD
ISA
BLE
SF
P1_M
OD
2
SF
P1_M
OD
0
SF
P1
_M
OD
1
SF
P1_R
AT
E
SF
P1_LO
S
M3X
_S
FP
1_T
DN
M3X
_S
FP
1_T
DP
M3X
_S
FP
1_R
DP
M3X
_S
FP
1_R
DN
.01UF
.01UF
M3X
_S
FP
1_T
DP
M3X
_S
FP
1_T
DN
M3X
_S
FP
1_R
DP
10K 10K
SF
P1_M
OD
0
SF
P1_R
AT
E
SF
P1_LO
S
SF
P1_T
X_F
AU
LT
1KM
3X
_L
OS
1S
FP
1_LO
S
SF
P1_LO
S
SF
P1_T
XD
ISA
BLE
SF
P1_M
OD
0
GR
EE
NG
RE
EN
RE
D
SF
P1_V
CC
T
CB22
CB29
J04
12
34
56
78
910
LB
03
CB17
CB30
CB16
LB
01
U03
212223242526272829
3031
8654 7
121319 1832
1516 14
109
11
12
0 17
RP
B0
6
4321
5678
DS
03
12
DS
09
12
DS
04
12
RP
B0
1
4321
5678
RP
B1
0
4321
5678
RP
B0
3
4321
5678
CB41
J10
12
34
56
CB38
J07
12
34
56
10/0
3/2
007
ST
EV
ES
CU
LLY
4/1
2(B
LO
CK
)
4/2
6(T
OT
AL)
DS
33M
33D
K01A
0
CR
-4:
@\_
RC
_LIB
\.\_
RC
_T
OP
_D
N_\(
SC
H_1):
PA
GE
4
SE
RD
ES
.P
.3-4
BLO
CK
NA
ME
:_rc
_to
p_dn_.
4C
3
4B
3
4D
3
2C
24B
5
4B
24A
7
4B
74B
24A
74A
5
4B
54B
5
4C
2
4C
24A
54B
2
4A
74C
24B
1
4A
3
4A
3
4A
3
4A
74A
3
4A
54A
3
4A
7
4A
74A
5
4A
7
4A
74A
1
4B
74A
74A
54A
1
4D
62C
2
4D
62C
2
2C
24C
6
2C
24C
6
4C
52C
2
4C
52C
2
2C
24B
5
4B
34A
5
4B
24A
1
4B
74B
24A
54A
1
4C
24A
3
2B
24B
24A
74A
54A
1
4B
74B
24A
74A
1
4C
24A
3
4B
34A
7
4D
2
PA
GE
:
DA
TE
:T
ITLE
:
EN
GIN
EE
R:
AA
BB
CC
DD
112 2
334 4
556 6
778 8
2 65
431
CO
NN
_6P
_U
2 65
431
CO
NN
_6P
_U
V3_3
V3_3
V3_3
SF
P_H
OS
T
CGNDCGNDCGNDCGNDCGNDCGNDCGNDCGND
CGNDCGNDCGND
VE
ER
RD
-
RD
+
VC
CT
VC
CR
VE
ER
TD
+
VE
ET
VE
ET
TD
-
VE
ER
VE
ER
LO
S
RA
TE
MO
D-D
EF
1
MO
D-D
EF
0
MO
D-D
EF
2
TX
_D
ISA
BLE
TX
_F
AU
LT
VE
ET
V3_3
V3_3
6
10
84
12
3 5 7 9
CO
NN
_10P
30
ET
H_R
X_E
RR
ET
H_R
XD
<7..0>
01234567
ET
H_T
XD
<7..0>
0123
30
4567
30
30
GTXCLK
M3X_LAN_CLKO
M3X_LAN_CLK
M3X_RMIISEL
M3X_DCESEL
ETH_RX_CRS
ETH_COL_DET
ETH_MDIO
ETH_MDC
ET
H_T
X_E
N
ET
H_T
X_C
LK
GM
II_T
X_E
R_
ET
H_R
XD
V
ET
H_R
X_C
LK
RP
08
4321
5678
RP
B2
7
431
5678
RP
10
4321
5678
R7
T7
P11
T5
T3
T2
P12
R12
T12
T8
R8
P8
T9
R9
P9
T10
R10
P10
R1
1
T1
1
T6
R3
P4
R4
T4
P5
R5
P6
R6
P3
RP11
4
3
2
1
5
6
7
8
R2
2
U05
10/0
3/2
007
5/2
6(T
OT
AL)
5/1
2(B
LO
CK
)
CR
-5:
@\_
RC
_LIB
\.\_
RC
_T
OP
_D
N_\(
SC
H_1):
PA
GE
5
DS
33M
33D
K01A
0
ST
EV
ES
CU
LLY
ET
HE
RN
ET
.P
.5-6
,19
,25
-26
BLO
CK
NA
ME
:_rc
_to
p_dn_.
6C
4
6C
36D
3
6C
36C
4
6A16C4
6A7
6A5
8B2
8B2
6D4
6D4
6B4
6B4
6C
3
6C
3
6B
16C
4
6D
4
6D
3
PA
GE
:
DA
TE
:T
ITLE
:
EN
GIN
EE
R:
AA
BB
CC
DD
112 2
334 4
556 6
778 8
DS
33M
33_U
ET
HE
RN
ET
MA
CI/F
LANCLKO
TX
D[1
]
TX
D[3
]
TX
D[2
]
TX
D[4
]
TX
D[6
]
TX
D[5
]
RX
D[1
]
RX
D[0
]
RX
D[4
]
RX
D[2
]
RX
D[3
]
RX
D[5
]
RX
D[7
]
RX
D[6
]
TX
D[7
]
TX
D[0
]
RX
CLK
RX
ER
R
RX
DV
TX
EN
TX
ER
R
TX
CLK
CRS
COL
DCESEL
MDC
MDIO
RMISEL
GTXCLK
LANCLKI
US
ED
INR
MII
MO
DE
(50
MH
Z)
ET
H_R
EF
_C
LK
ISO
NLY
CLK
AA
ND
CLK
BT
ES
TP
OIN
TS
AR
EIN
TH
ELIU
BLO
CK
RE
FC
LK
&C
LK
CT
ES
TP
OIN
TS
AR
EIN
TH
EP
HY
BLO
CK
CL
OC
KT
ES
TP
OIN
TS
:
NO
TC
ON
NE
CT
ION
TO
AR
ES
OU
RC
EC
AR
DIS
INT
EN
DE
DF
OR
US
EA
ST
ES
TP
OIN
TS
ET
HE
RN
ET
CO
NN
EC
TO
R(I
.M.
BU
S)
25M
HZ
OS
C_T
O_P
RO
C
ET
H_T
XD
<7..0>
CLK
_T
O_M
AC
GT
XC
LK
ET
H_C
OL_D
ET
ET
H_R
XD
<7..0>
GM
II_T
X_E
R_
I23
I24
1UH
4.7UF
.1UF
M3X
_C
LA
DC
LK
_T
O_LIU
30
I22
2.2K
30
30
25.0
00M
HZ
_3.3
V_S
OC
KE
T
CLK
_T
O_M
AC
AV
_LA
N_C
LK
PY
25M
HZ
OS
C
M3X
_LA
N_C
LK
O
M3X
_C
LK
CRE
FC
_25M
JM
P_
3M
3X
_C
LA
DC
LK
GM
II_T
X_E
R_
19.4
4M
HZ
_3.3
V_S
OC
KE
T
4.7UF
.1UF
77.7
6M
HZ
_3.3
V_S
OC
KE
T
CLK
_T
O_M
AC
GT
XC
LK
AV
_LA
N_C
LK
ET
H_R
XD
<7..4>
ET
H_T
XD
<7..4>
RE
SE
T_LA
N
ET
H_R
XD
<3..0>
ET
H_R
X_C
LK
ET
H_R
XD
V
ET
H_R
X_C
RS
ET
H_R
X_E
RR
ET
H_T
XD
<3..0>
ET
H_T
X_C
LK
ET
H_T
X_E
N
ET
H_M
DIO
ET
H_M
DC
PY
25M
HZ
OS
C
PH
Y_IN
T
M3X
_LA
N_C
LK
30
RB08
YB
02
45
18
JP
01
13
2
RB
15 R
B14
YB
01
45
18
YB
05
45
18
J19
12
34
56
RP
13
4321
5678
RP
B2
3
4321
5678
L01
C01
C02
C03
C04
6/2
6(T
OT
AL)
ST
EV
ES
CU
LLY
6/1
2(B
LO
CK
)
10/0
3/2
007
CR
-6:
@\_
RC
_LIB
\.\_
RC
_T
OP
_D
N_\(
SC
H_1):
PA
GE
6
DS
33M
33D
K01A
0
ET
HE
RN
ET
.P
.5-6
,19
,25
-26
BLO
CK
NA
ME
:_rc
_to
p_dn_.
6B
1
25A
7v
19B
3v
25B
1v
19B
3v
6A
7
25B
7v
19B
3v
6A
15A
4
19C
3v
5A
525A
1v
6B
15C
6
9B
2
25B
1v
19B
3v
6B
16C
3
5A
4
19B
3v
6B
4
1A
8
25B
4v
6B
4
5A
4
10B
71D
2
10B
71D
3
25A
7v
19B
3v
6C
45C
6
25B
7v
19B
3v
5A
46C
4
25B
1v
19B
3v
6C
36A
7
6C
45B
619B
3v
25B
7v
5B
26D
319C
3v
25B
7v
5C
319C
3v
25A
1v
5A
519C
3v
25A
1v
5C
319B
3v
25A
1v
6C
45B
619C
3v
25B
7v
19B
3v
PA
GE
:
DA
TE
:T
ITLE
:
EN
GIN
EE
R:
AA
BB
CC
DD
112 2
334 4
556 6
778 8
VC
C1
OS
C
GN
DO
UT
SIN
GLE
50
PIN
FO
RC
ON
NE
CT
ION
TO
ET
HE
RN
ET
CA
RD
US
ED
ON
BO
TT
OM
OF
MO
TH
ER
BO
AR
D
CO
NN
EC
TO
RS
ET
HE
RN
ET
(LA
N)
I.M
.C
AR
DP
LU
G-C
ON
NE
CT
OR
S
HIE
RA
RC
HY
BL
OC
K_phy_im
bus_m
b_dn
PH
Y_IN
T
OS
C25M
MD
C
MD
IO
PT
2_T
X_E
N
PT
2_R
X_C
LK
PT
2_C
OL_D
ET
PT
1_T
X_E
N
PT
1_T
X_C
LK
PT
1_T
XD
<3..0>
PT
1_R
X_E
RR
PT
1_R
X_C
RS
PT
1_R
XD
V
PT
1_R
X_C
LK
PT
1_C
OL_D
ET
PT
1_R
XD
<3..0>
GM
II_T
X_E
R_
GM
II_C
LK
TO
MA
C_B
UF
SP
AR
E
GM
II_C
LK
FR
OM
_M
AC
RE
SE
T_B
PT
2_T
X_C
LK
PT
2_T
XD
<3..0>
PT
2_R
X_E
RR
PT
2_R
X_C
RS
PT
2_R
XD
V
PT
2_R
XD
<3..0>
LA
N_C
LK
V3_3
GMIIONLY
_phy_dp83865bvh_dn
HIE
RA
RC
HY
BL
OC
K
SP
AR
E<
4..1>
CLK
TO
MA
C_T
ES
TP
NT
CLK
TO
MA
C
GM
II_C
LK
FR
OM
_M
AC
CO
L_D
ET
RX
_E
RR
PH
Y_IN
T
RX
D<
7..0>
TX
D<
7..0>
RX
DV
RX
_C
LK
RX
_C
RS
TX
_C
LK
TX
_E
N
TX
_E
R_
RE
SE
T_B
MD
IOM
DC
PH
YO
SC
25M
LA
N_C
LK
2 65
431
CO
NN
_6P
_U
VC
C1
OS
C
GN
DO
UT
VC
C1
OS
C
GN
DO
UT
V3_3
V3_3
FO
RD
DR
11D
DR
_B
A0
DD
R_
BA
1
DD
R_C
AS
DD
R_R
AS
DD
R_
WE
DD
R_C
KE
DD
R_
CK
DD
R_
CS
DD
R_C
KIN
V
DD
R_LD
M
DD
R_U
DM
DD
R_LD
QS
DD
R_U
DQ
S
DD
R_D
Q<
15..0>
DD
R_D
Q<
15..0>
DD
R_V
RE
F
DD
R_
A<
12
..0
>
DD
R_V
RE
F
4.7UF
4.7UF
.1UF
.1UF
.1UF
.1UF
4.7UF
4.7UF
12109876543210
01235 46789
10111214 1315
1.00K1.00K
.01UF.01UF
4.7UF4.7UF
0123456789101112
0123456789
101112131415
DD
R_
CS
DD
R_
CK
DD
R_LD
M
DD
R_C
KE
DD
R_C
KIN
V
DD
R_C
AS
DD
R_B
A0
DD
R_
BA
1
DD
R_R
AS
DD
R_
WE
DD
R_U
DM
DD
R_U
DQ
S
DD
R_LD
QS
.01UF
.1UF
4.7UF
CB75 CB76
CB72 C08
RB12 RB13
U06
29
28
4142 303132353637383940
26
27
22
45
46
44
24
5019
257
59
60
62
63
65
457810111354
56
20
16
17
43
14
25
53
23
47
51
118
33
55
3
15
9
61
49
66
4834
52
64
58
12
6
21
CB58
CB102
CB49
CB90
CB83
CB85
CB146
CB89
CB74
CB110
CB63
U05
D12
C13
D13
C14
A14
B13
A13
A12
B1
1
C12
A1
1
B10
C1
1
D1
1 D9
B9
A9
A10
D10
C3
C4
D4
C5
D5
C6
D6
D7
A7
B6
A6
A5
B5
B4
A4
A3
B8
C7
C10
A8
B7
C9
B12
DD
R_
A<
12
..0
>
10/0
3/2
007
7/2
6(T
OT
AL)
7/1
2(B
LO
CK
)
CR
-7:
@\_
RC
_LIB
\.\_
RC
_T
OP
_D
N_\(
SC
H_1):
PA
GE
7
DS
33M
33D
K01A
0
ST
EV
ES
CU
LLY
DD
RM
EM
OR
Y.
P.7
BLO
CK
NA
ME
:_rc
_to
p_dn_.
7B
8
7B
8
7B
8
7B
8
7B
8
7B
8
7B
8
7B
8
7B
8
7B
8
7A
8
7C
5
7C
5
7A
4
7A
1
7C
4
10B
37D
2
7C
8
10B
37D
5
7C
3
7C
3
7C
3
7C
3
7C
3
7C
3
7B
3
7C
3
7C
3
7C
3
7C
3
7C
1
7C
1
PA
GE
:
DA
TE
:T
ITLE
:
EN
GIN
EE
R:
AA
BB
CC
DD
112 2
334 4
556 6
778 8
SD
RA
MI/
F
DS
33M
33_U
SD
UD
M
SD
WE
*
SD
RA
S*
SD
BA
[1]
SD
BA
[0]
SD
A[1
]
SD
A[0
]
SD
A[4
]
SD
A[3
]
SD
A[2
]
SD
A[6
]
SD
A[5
]
SD
A[9
]
SD
A[7
]
SD
A[8
]
SD
A[1
1]
SD
A[1
0]
SD
A[1
2]
SD
CA
S*
SD
CLK
N
SD
CLK
EN
SD
LD
M
SD
CLK
P
SD
CS
*S
DD
Q[0
]
SD
DQ
[2]
SD
DQ
[1]
SD
DQ
[3]
SD
DQ
[5]
SD
DQ
[4]
SD
DQ
[6]
SD
DQ
[7]
SD
DQ
[8]
SD
DQ
[9]
SD
DQ
[10]
SD
DQ
[11]
SD
DQ
[12]
SD
DQ
[13]
SD
DQ
[14]
SD
DQ
[15]
SD
UD
QS
SD
LD
QS
V2_5
MT
46V
16M
16B
G75
A8
A9
A10/A
P
A11
A12
A1
A2
A3
A4
A5
A6
A7
BA
0
BA
1
CA
S
RA
S
WE
CK
E
CK
CS
CK
_IN
V
LD
M
UD
M
DNUDNU
NCNCNCNCNC
VSSQVSSQ
VSSQVSSQVSSQ
VSSVSSVSS
VDDVDDVDD
VDDQVDDQ
VDDQVDDQVDDQ
VREF
A0
DQ
0
DQ
1
DQ
3
DQ
2
DQ
6
DQ
4
DQ
5
DQ
7
DQ
8
DQ
9
DQ
11
DQ
10
DQ
13
DQ
14
DQ
12
LD
QS
DQ
15
UD
QS
V2_5
V2_5
RE
MO
VE
TH
ISIN
VE
RT
ER
TO
MA
KE
US
EO
FT
HE
JU
MP
ER
OP
TIO
NS
FO
RA
LE
(AB
OV
E)
AS
TE
ST
PO
INT
SF
OR
PR
OT
OB
OA
RD
(NO
TN
EE
DE
D)
INS
TA
NT
IAT
EP
ULLU
PF
OR
INT
INF
PG
A
MT
0&
MT
2A
TT
AC
ED
TO
RP
AC
K
DO
UB
LE
CH
EC
KB
IAS
NE
ED
SF
OR
MT
1
ALE
SH
OU
LD
BE
TIE
DH
IGH
FO
RN
ON
-MU
LT
IPLE
XE
DA
DD
RE
SS
OP
ER
AT
ION
AN
DT
IED
TIE
DLO
WD
UR
ING
SP
IM
OD
E(S
PIS
EL=
1).
M3X
_JT
MS
CS
_X
1
M3
X_
CS
JM
P_
3
13
M3
X_
CS
D2_S
PI_
CLK
DA
TA
<7
..0
>
SP
I_S
S
2
JM
P_
3
INV
ER
TE
R
M3X
_IN
T
M3X
_IN
T
RD
_D
S
13
WR
_R
W
5
1K
10K
1
DA
TA
<7
..0
>
D7_S
PI_
CP
OL
DA
TA
<7
..0
>
DA
TA
<7
..0
>D
0_S
PI_
MIS
OS
PI_
SC
K
7
6
5
10
JM
P_
3
10K
330
1K
10K
42 86
10 12
0
3 5 7 9 11
AD
DR
<13..0>
431
10 12
0
14
7 9 11 15 DA
TA
<1
5..
0>
2 86
D5_S
PI_
SW
AP
10K
1KD
6_S
PI_
CP
HA
M3X
_M
T0
M3
X_
MT
1
M3X
_M
T2
M3X
_A
LE
M3X
_R
MIIS
EL
M3X
_D
CE
SE
L
M3X
_H
IZ_N
M3X
_S
PIS
EL
M3X
_T
ES
T_E
NM
3X
_IF
SE
L_S
TY
LE
M3X
_IF
SE
L_S
IZE
M3X
_JT
RS
T_N
M3X
_S
PIS
EL
M3X
_A
LE
M3
X_
JT
DI
M3X
_JT
DO
SP
I_M
ISO
JM
P_
3
DA
TA
<7
..0
>
D1_S
PI_
MO
SI
SP
I_M
OS
I
DA
TA
<7
..0
>
1KM
3X
_JT
CLK
RP
B5
0
4321
5678
J30
12
34
56
78
910
1112
1314
RP
B5
2
4321
5678R
PB
53
4321
5678
DS
28
J16
12
34
56
78
910
RP
B3
2
4321
5678
JP11 13
2
JP14 13
2
JP13 13
2
JP12 13
2
RP
B3
6
4321
5678
JP22 13
2
JP21 13
2
JP20 13
2
RP
B3
3
4321
5678
UB
05
14
RP
B4
9
4321
5678R
PB
48
4321
5678
RP
B2
9
4321
5678
J24
12
34
56
78
910
1112
1314
J21
12
34
56
78
910
1112
1314
1516
J23
12
34
56
78
910
BIA
S+
CO
NF
IG.
P.8
CR
-8:
@\_
RC
_LIB
\.\_
RC
_T
OP
_D
N_\(
SC
H_1):
PA
GE
8
8/2
6(T
OT
AL)
8/1
2(B
LO
CK
)
DS
33M
33D
K01A
0
ST
EV
ES
CU
LLY
10/0
3/2
007
BLO
CK
NA
ME
:_rc
_to
p_dn_.
8C
21A
8
1D
31A
88D
3
1B
5
8D
48C
6
1D
38C
1
1D
31B
88A
8
9C
110B
51A
81D
3
9C
110B
51A
81D
3
1B1
9C
310B
51A
88B
38C
68D
3
1B1
9C
310B
51A
88B
38D
38D
48D
6
1B1
1B1
9C
310B
51A
88B
38C
68D
38D
6
9C
310B
51A
88B
38C
68D
38D
48D
6
1B1
9C
310B
51A
88B
38C
68D
38D
48D
6
1B1
9C
31A
88B
31C1
1A
5
1A
29C
110B
51A
8
1B1
9C
310B
51A
88C
68D
38D
48D
6
1C1
1C1
1B
5
1B
5
1B
5
8A
21A
81D
3
5A
4
1B
5
1C
5
8A
21B
58B
21A
81D
3
1C
5
1D
3
1A
5
10B
58D
6
1B
5
8D
68D
4
1C1
1C1
1C
5
1C
5
1C
5
1B
8
8D
4
1B1
PA
GE
:
DA
TE
:T
ITLE
:
EN
GIN
EE
R:
AA
BB
CC
DD
112 2
334 4
556 6
778 8
V3_3
6
10
84
12
3 5 7 9
CO
NN
_10P
CO
NN
_16P
2 4 8
10 12 14 16
31 7 9 11 13 1556
V3_3
2
3 7 13
8
5 9 11
64
10 12 14
1
CO
NN
_1
4P
V3_3
V3_3
NC
7S
Z86_U
V3_3
V3_3
2
3 7 13
8
5 9 11
64
10 12 14
1
CO
NN
_1
4P
V3_3
CO
NN
_10P
531 7
TM
S
TC
K
TD
I
TD
O
VC
CG
ND
DA
TA
BU
ST
AP
SW
RO
NG
[0:7
]T
HIS
HA
SB
EE
NF
IXE
DIN
TH
EF
PG
A.
BU
GF
IX:
PC
BR
EV
01A
0H
AD
TH
E
PLA
CE
TE
ST
PO
INT
ST
OA
LLO
WLO
OP
BA
KT
--R
PO
RT
/P
INA
SS
IGN
ME
NT
SD
S33M
33_R
CLK
1IS
AT
PIN
F3
DS
33M
33_R
CLK
3IS
AT
PIN
J2
DS
33M
33_R
CLK
2IS
AT
PIN
H3
M33_T
NE
G3
M33_T
PO
S3
DA
TA
[7..
0]
TE
3_IN
TWR
_R
WR
D_
DS
330
M33_T
PO
S1
M33_T
CLK
2
M33_T
PO
S2
AD
DR
[5..
0]
RE
SE
T_
SY
S
54321
330
M33_T
NE
G3
M33_R
CLK
3
M33_R
NE
G3
M33_T
CLK
3
M33_R
PO
S3
M33_T
PO
S3
M33_G
PIO
B3
M33_G
PIO
A3
M33_R
CLK
2
M33_R
NE
G2
M33_T
CLK
2
M33_R
PO
S2
M33_G
PIO
B2
M33_G
PIO
A2
M33_R
CLK
1
M33_R
NE
G1
M33_T
CLK
1
M33_R
PO
S1
M33_T
PO
S1
M33_G
PIO
B1
M33_G
PIO
A1
M33_T
NE
G1
M33_T
NE
G1
M33_T
CLK
1
M33_R
NE
G1
M33_R
CLK
1
M33_R
PO
S1
M33_R
NE
G2
M33_R
CLK
2
M33_R
PO
S2
M33_R
NE
G3
M33_R
CLK
3
M33_R
PO
S3
M33_T
NE
G2
1K1K
10K
10K
M3X_CLKA
RE
D_G
RE
EN
M33_G
PIO
B1
M33_G
PIO
A1
M33_G
PIO
A3
M33_G
PIO
B3
M33_G
PIO
A2
M33_G
PIO
B2
M33_T
CLK
3
0 1 2 3 4 5 6 7
M33_T
NE
G2
M33_T
PO
S2
M3X_CLKB
TE
3_L_C
S
0
M3X
_C
LA
DC
LK
_T
O_LIU
RE
D_G
RE
EN
RE
D_G
RE
EN
J12
12
34
56
J14
12
34
56
J17
12
34
56
J18
12
34
56
J15
12
34
56
J13
12
34
56
U05
G2
F2
F3
G4
E2
E3
F4
D2
U05
L4
K3
J2 K4
J3
J4 J5 K5
U05
H5
J6
H3
H4
H2
G3
H6
G5
RP
B0
5
4321
5678 RP
B0
2
4321
5678
DS
07
1 2
3 4
DS
06
1 2
3 4
DS
01
1 2
3 4
RP
B0
7
4321
5678
RP
B0
4
4321
5678
J01
12
34
56
78
910
1112
1314
RP
B1
3
4321
5678
RP
B0
8
4321
5678
9/2
6(T
OT
AL)
CR
-26
:@
\_R
C_LIB
\.\_
RC
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OP
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N_\(
SC
H_1):
PA
GE
1_I9
@\_
RC
_LIB
\.\_
DS
33M
30D
K_D
N_\(
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H_1):
PA
GE
7
04/1
5/2
007
9/1
2(B
LO
CK
)
CR
-9:
@\_
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_LIB
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RC
_T
OP
_D
N_\(
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H_1):
PA
GE
9
ST
EV
ES
CU
LLY
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33M
30M
31M
33E
E01A
0
T3
E3
LIU
I/F
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-22
BLO
CK
NA
ME
:_rc
_to
p_dn_.
9A
6
9A
6
21D
7v
21D
3v
21C
8v
21C
7v
21C
3v
21C
2v
8D
68D
48D
38C
68B
31A
810B
51B
120D
8v
1B
8
21C
8v
1D
31A
810B
58C
1
21C
4v
1D
31A
810B
58C
1
9D
6
9C
6
9B
6
21D
6v
21D
2v
21C
6v
21C
3v
21C
2v
8B
51A
810B
51A
2
20B
5v
1B
51A
811B
310B
4
9C
4
9C
1
9C
1
9C
4
9C
19C
4
10C
49A
5
10C
49A
5
9D
1
9D
1
9D
4
9C
1
10C
49A
5
10C
49A
5
9D
1
9D
1
9D
4
9D
19D
4
10C
49A
5
10C
49A
5
9D
4
9D
6
9D
6
9D
8
9D
8
9D
8
9C
8
9C
8
9B
8
9A
8
9A
8
9A
8
9C
6
20A
3v
10B
71D
3
9A
6
9D
4
9C
4
20A
2v
10B
71D
2
21C
4v
1A
8
20A
5v
6C
6
PA
GE
:
DA
TE
:T
ITLE
:
EN
GIN
EE
R:
AA
BB
CC
DD
112 2
334 4
556 6
778 8
2
3 7 13
8
5 9 11
64
10 12 14
1
CO
NN
_1
4P
213 4
213 4
213 4
V3_3
DS
33M
33_U
PO
RT
RLC
LK
RN
EG
/RLC
V
TLC
LK
RP
OS
/RD
AT
TP
OS
/TD
AT
GP
IOB
GP
IOA
TN
EG
DS
33M
33_U
PO
RT
RLC
LK
RN
EG
/RLC
V
TLC
LK
RP
OS
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AT
TP
OS
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AT
GP
IOB
GP
IOA
TN
EG
DS
33M
33_U
PO
RT
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RN
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/RLC
V
TLC
LK
RP
OS
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AT
TP
OS
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AT
GP
IOB
GP
IOA
TN
EG
2 65
431
CO
NN
_6P
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2 65
431
CO
NN
_6P
_U
2 65
431
CO
NN
_6P
_U
2 65
431
CO
NN
_6P
_U
2 65
431
CO
NN
_6P
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2 65
431
CO
NN
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blo
ck_dn
HIE
RA
RC
HY
BL
OC
K
AD
DR
0
DA
TA
7D
AT
A6
DA
TA
5D
AT
A4
DA
TA
3D
AT
A2
DA
TA
1D
AT
A0
LIU
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PO
S1
LIU
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NE
G1
E3_MCLK_IO
T3_MCLK_IO
ALTERNATE_MCLK
RS
TIN
T
RD
_D
SC
S
LIU
_T
CLK
1
AD
DR
2A
DD
R1
LIU
_R
PO
S3
LIU
_R
NE
G3
AD
DR
3
LIU
_T
NE
G3
LIU
_T
CLK
3
LIU
_T
PO
S3
LIU
_R
CLK
3
LIU
_T
PO
S2
LIU
_T
CLK
2
LIU
_T
NE
G2
LIU
_R
PO
S2
LIU
_R
CLK
2
LIU
_R
NE
G2
LIU
_R
PO
S1
LIU
_R
CLK
1
LIU
_R
NE
G1
WR
_R
W
AD
DR
4A
DD
R5
M33_G
PIO
A3
M3X
_C
LK
C
M3X
_C
LK
B
M3X
_C
LK
A
M3X
_C
LA
DC
LK
M33_G
PIO
B2
M33_G
PIO
B3
M33_G
PIO
B1
M33_G
PIO
A2
M33_G
PIO
A1
RE
SE
T_S
YS
CP
LD
_A
TO
HE
N
CP
LD
_T
AO
HE
N
CP
LD
_C
S
WR
_R
W
CP
LD
_A
TO
HC
LK
CP
LD
_A
TO
HS
OF
CP
LD
_D
TO
H
CP
LD
_D
TO
HC
LK
CP
LD
_D
TO
HS
OF
CP
LD
_T
AO
H
CP
LD
_A
TO
H
CP
LD
_O
H1
CP
LD
_O
HC
LK
CP
LD
_R
DO
H
CP
LD
_R
DO
HS
OF
CP
LD
_R
DO
HV
LD
CP
LD
_T
AO
HS
OF
CP
LD
_T
AO
HV
LD
RD
_D
S
DD
R_V
RE
F
AD
DR
<3
..0
>
DA
TA
<7
..0
>
U05
B16
A16
K1
M1
L1
N1
M15
F15
L15
E15
K1
5
D15
D1
F1
H1
P15
H1
5
E1
G1
J1
N15
G15
E5
E9
E12 E8
10/2
6(T
OT
AL)
10/0
3/2
007
10/1
2(B
LO
CK
)
CR
-10
:@
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C_LIB
\.\_
RC
_T
OP
_D
N_\(
SC
H_1):
PA
GE
10
DS
33M
33D
K01A
0
ST
EV
ES
CU
LLY
OV
ER
HE
AD
.P
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0,2
3-2
4
BLO
CK
NA
ME
:_rc
_to
p_dn_.
23D
6v
9A
69A
5
23D
7v
6A
71D
2
23D
7v
9B
21D
2
23D
7v
9B
21D
3
23D
7v
1D
36C
6
23D
6v
9B
69A
5
23D
6v
9A
69A
5
23D
6v
9C
69A
5
23D
6v
9B
69A
5
23D
6v
9C
69A
5
23B
4v
8D
68D
48D
38C
68B
31A
89C
31B
1
24B
4v
1B
51A
811B
39B
1
23A
5v
2B
7
23A
6v
2C
7
23C
7v
23B
7v
8B
51A
89C
11A
2
23C
7v
1A
8
23C
7v
1D
31A
89C
18C
1
23A
5v
2B
7
23A
5v
2B
7
23A
5v
2B
7
23A
4v
2B
7
23A
5v
2B
7
23A
6v
2C
7
23A
5v
2B
7
23A
6v
2C
7
23A
6v
2C
7
23A
6v
2C
7
23A
5v
2C
7
23A
5v
2B
7
23A
6v
2C
7
23A
6v
2C
7
23C
7v
1D
31A
89C
18C
1
7D
57D
2
23C
4v
PA
GE
:
DA
TE
:T
ITLE
:
EN
GIN
EE
R:
AA
BB
CC
DD
112 2
334 4
556 6
778 8
V1_8
V3_3
V1_8
V1_8
V2_5
overh
eadcpld
_dn_
HIE
RA
RC
HY
BL
OC
K
CP
LD
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HC
LK
M33_G
PIO
B2
M33_G
PIO
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D
CP
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LK
C
CP
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A
CP
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LA
DC
LK
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LD
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LD
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HS
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CP
LD
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DO
HV
LD
CP
LD
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HS
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CP
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H
CP
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H1
CP
LD
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H
CP
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CP
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LK
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7..0>
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M33_G
PIO
A1
M33_G
PIO
A2
M33_G
PIO
A3
M33_G
PIO
B1
PW
R&
GN
D
DS
33M
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VDD33[6..1]
VDD18[12..1]TVSSA
TVSSB
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1_1_8V
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3_1_8V
CVSS1
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DP
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VD
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VSS[22..1]
VSSQ[7..1]
CVDD_1.8V
CVDD_1.8V
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RHVSSA
TVSS1
VR
EF
AVSS
TVSS3
TVSS2
TV
DD
B_1.8
V
RV
DD
B_1.8
V
TV
DD
A_1.8
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HV
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B_3.3
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RV
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A_1.8
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HV
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A_3.3
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TV
DD
2_1_8V
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DQ
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..1]
TR
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TR
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TO
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V2.5
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4.7UF
4.7UF
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4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
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4.7UF
4.7UF
4.7UF
GR
EE
N
RE
SE
T_
SY
S
10UF
4.7UF
.1UF
.01UF
.1UF
.1UF
4.7UF
4.7UF
10UF
10UF
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4.7UF
10UF
3.0
8V
330
.1UF
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.01UF
4.7UF
4.7UF
10UF
4.7UF
.1UF
.1UF
.1UF
330
4.7UF
470UF
.1UF
4.7UF
470UF
.1UF
4.7UF
470UF
4.7UF
4.7UF
470UF
1.8
V
BU
FF
ER
2.5
V
4.7UF
.1UF
4.7UF
.1UF
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4.7UF
V1
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4.7UF
.1UF
4.7UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
4.7UF
10UF
V2
_5
GR
EE
N
CB60
CB81
C12
CB61
CB108
CB86
CB35
CB104
CB50
CB80
CB82
CB91
CB51
CB111
CB99
CB87
CB109
CB52
SW
01
1 234
UB
07
13
24
RB
28
DS
30
12
CB57
CB56
CB59
CB170
C13
CB103
CB48
CB181
CB166
CB105
CB144
RB
30
DS
32
12
C16
CB1451 2
UB
12
14
C18
C23
CB171
1 2
UB
08
10 17
2 3 4 5
12 13 14 15
611
7
CB156
CB175
CB1741 2
CB163
CB150
CB1571 2
UB
09
10 17
2 3 4 5
12 13 14 15
611
7
CB55
CB71
CB06
CB05
CB12
CB128
CB138
CB25
CB119
CB133
CB141
CB14
CB131
CB123
CB120
CB122
CB115
CB116
CB142
CB118
CB126
CB127
CB136
CB26
CB27
CB04
CB117
CB03
CB140
CB187
CB186
CB132
CB182
C15
CB183
CB21
CB28
CB148
CB143
CB121
CB129
CB139
11/2
6(T
OT
AL)
10/0
3/2
007
11/1
2(B
LO
CK
)
BLO
CK
NA
ME
:_rc
_to
p_dn_.
PA
RE
NT
BLO
CK
:<
CO
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AR
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T_N
AM
E>
CR
-11
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C_LIB
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N_\(
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GE
11
DS
33M
33D
K01A
0
ST
EV
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CU
LLY
PO
WE
R.
P.1
1-1
2
1B
51A
810B
49B
1
PA
GE
:
DA
TE
:T
ITLE
:
EN
GIN
EE
R:
AA
BB
CC
DD
112 2
334 4
556 6
778 8
V3_3
V3_3
V5_0
MA
X1793_U
IN2
OU
T1
OU
T3
SE
T
GN
D
GN
D
IN1
IN3
IN4
OU
T2
SH
DN
RS
T
OU
T4
MA
X1793_U
IN2
OU
T1
OU
T3
SE
T
GN
D
GN
D
IN1
IN3
IN4
OU
T2
SH
DN
RS
T
OU
T4
V1_8
NC
7S
Z86_U
V2_5
V3_3
V3_3
MA
X811_U
RE
SE
T*
VC
C
GN
D
MR
*
V3_3
V1_8
V2_5
V3_3
V3_3
V2_5
MO
UT
ING
HA
RD
WA
RE
3.3
V1%
RE
GU
LA
TO
R
10UF
330
PO
WE
RO
K
.1UF
3.3
V
3.3
V
3.3
V
PO
WE
RO
K
10UF
68UF
10UF
0.00.0
0.0
68UF
68UF
10UF
4.7UF
.1UF
.1UF
4.7UF
.1UF
10UF
4.7UF
.1UF
.1UF
4.7UF
.1UF
.1UF
1A
MP
68UF
10UF
10UF
10UF
10UF
100O
100M
ZH
4.7UF
4.7UF
470UF
RED_GREEN
10UF
DB
01
21
C22
C20
CB188
CB155
CB161
CB167
CB152
CB151
CB162
CB169
CB149
CB180
CB190
CB179
CB172
CB173
CB13
C17
CB1851 2
CB189
1 2
UB
13
10 17
2 3 4 5
12 13 14 15
611
7
CB158
1 2
C24
R05
DS
31
1
2
3
4
CB154
CB153
R04 R02
CB1761 2
RPB59
4
3
2
1
5
6
7
8
C21
CB1591 2
UB
11
10 17
2 3 4 5
12 13 14 15
611
7
C19
GN
D_T
P01
UB
10
10 17
2 3 4 5
12 13 14 15
611
7
GN
D_T
P02
GN
D_T
PB
01
GN
D_T
P11
GN
D_
TP
B0
2
GN
D_
TP
04
GN
D_
TP
B0
3
JB
09
21
GN
D_T
P03
GN
D_
TP
B0
6H
B0
3
HB
01
HB
02 H
B0
5
HB
04
L1
C1
BLO
CK
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PB28B(VREF1_4)
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PB28A(VREF2_4)
PB18A
PB16B
PB16A
PB14B
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PB18B
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22A
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PR2A(VREF1_2)
PR2B(VREF2_2)
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PT10A(PCLKT0_0)
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ST
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PA
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:
DA
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:
EN
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EE
R:
AA
BB
CC
DD
112 2
334 4
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V2_5
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50
49
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45
44
43
42
41
40
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3837
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28
27
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22
2117117
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25
26
20
1991
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46
45
44
43
42
41
40
39
3837
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3231
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9
28
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22
2117117
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1991
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PA
RE
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:@
\_rc
_lib
\.\_
rc_to
p_dn_\(
sch_1):
page13_i2
04@
\_rc
_lib
\.\_
ds3154_liu
blo
ck_dn\(
sch_1):
Page1
T3
E3
LIU
I/F
.P
.2,9
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46B
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VDD8
VDD7
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12
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56
21/2
6(T
OT
AL)
2/3
(BLO
CK
)
10/0
3/2
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BLO
CK
NA
ME
:_ds3154_liu
blo
ck_dn.
PA
RE
NT
BLO
CK
:\_
rc_to
p_dn_\
DS
33M
33D
K01A
0
CR
-47
:@
\_rc
_lib
\.\_
rc_to
p_dn_\(
sch_1):
page13_i2
04@
\_rc
_lib
\.\_
ds3154_liu
blo
ck_dn\(
sch_1):
Page2
ST
EV
ES
CU
LLY
T3
E3
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I/F
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.2,9
,20
-22
47B
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547B
4
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1
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PA
GE
:
DA
TE
:T
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:
EN
GIN
EE
R:
AA
BB
CC
DD
112 2
334 4
556 6
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CK
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TE
VE
SC
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BLO
CK
NA
ME
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p_dn_.
PA
RE
NT
BLO
CK
:\_
rc_to
p_dn_\
DS
33M
30M
31M
33E
E01A
0
T3
E3
LIU
I/F
.P
.2,9
,20
-22
CR
-48
:@
\_rc
_lib
\.\_
rc_to
p_dn_\(
sch_1):
page13_i2
04@
\_rc
_lib
\.\_
ds3154_liu
blo
ck_dn\(
sch_1):
Page3
21C
8
21C
321C
6
21C
521C
2
21C
4
21C
3
21D
3
21D
4
21D
3
21D
7
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2
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3
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7
21C
5
21C
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8
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2
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3
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5 21C
6
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3
21C
7
21C
7
21C
2
21C
6
21C
3
21C
5
21C
8
21D
5
21D
6
21D
8
21C
2
21C
5
21C
7
21C
3
PA
GE
:
DA
TE
:T
ITLE
:
EN
GIN
EE
R:
AA
BB
CC
DD
112 2
334 4
556 6
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G
S
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1:2 1:2
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ME
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SI
CP_DUT_CLKC
7 6 5 4 3 2 0
DA
T<
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CP_DUT_CLKA
CP_DUT_CLKB
0123
WR
RD
CP
LD
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S
CPLD_DTOHSOF
CPLD_ATOHCLK
CPLD_ATOHEN
CPLD_RDOHVLD
CPLD_OHCLK
CPLD_OH1
CPLD_TAOH
CPLD_TAOHSOF
CPLD_TAOHEN
CPLD_TAOHVLD
CPLD_RDOH
CPLD_ATOH
CPLD_ATOHSOF
CPLD_DTOH
CP_DUT_CLADCLK
CPLD_RDOHSOF
CP_DUT_CLKB
CP_DUT_CLKC
M33_GPIOA1
M33_GPIOB1
M33_GPIOA2
M33_GPIOB2
M33_GPIOB3
M33_GPIOA3
M33_GPIOB1
M33_GPIOA2
M33_GPIOB2
M33_GPIOA3
M33_GPIOB3
M33_GPIOA1
ME
M_S
CK
RE
D_G
RE
EN
RE
D_G
RE
EN
CP_DUT_CLADCLK
1
97
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CPLD_DTOHCLK
ME
M_
SO
ME
M_
CS
0.0
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CP_DUT_CLKA
RE
D_G
RE
EN
10B
5^
RB
04
U0
1
39
40
41
42
43
45
46
47
48
49
50
51
53
56
57
58
59
60
61
62
64
65
66
67
68
69
70
20
21 22
23
25
26
27
29 30 31
32 33 34 352 3 4 5 6 7 8 9
88
87
86
85
83
82
81 79
78
77
76
75
7410
7
10
6
10
5
10
4
10
3
10
2
101
10
0
142
141
140
139
138
137
135
134
133
132
131
130
129
127
124
123
122
121
120
119
118
116
115
114
113
112
111
DS
10
1
23
4
RP
01
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12
1
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4
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11
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Page1
11B
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11C7^
11C5^
11C5^
11C5^
11C7^
11C7^
11C5^
11C5^
11B7^
11C7^
11C7^
11B7^
11B7^
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49D7 11B7^
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PL9B
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PT17A/PCLKT0_0
PT15A
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PT12B
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PB17A/PCLKT5_0
PB19A/VREF1_4
PB19B/CS*
PB20A/VREF2_4
PT14A/TDQS14
PT10A
PT10B PB10B
PB23A
PB22A/BDQS22
PB21A/D2/SPID5
PB18B/CS1*
PL11A
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PL18B
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PB17B/PCLKC5_0
PB16A/VREF2_5
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PB15A
PB14B
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PB13B
PB11B
PB11A
PB10A
PL16A
PB20B/D0/SPID7
PB21B/D1/SPID6
PB22B/D3/SPID4
PB23B/D4/SPID3
PB25B/D6/SPID1
PB24B/D5/SPID2
PL2A
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1_7
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PL7B
PL8B
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PT25B
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PT23A
PT22B
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PT21B
PT20A
PT21A
PT20B
PT19B/VREF2_1
PT13B
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PT19A/VREF1_1
PT18B
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CB11
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\.\o
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eadcpld
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sch_1):
Page2
11B
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GND10
GND9
GND8
GND7/GND0
GND6B/GND5
GND3B
GND3A/GND4
GND2/GND1
GND1
GND0
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CK
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AA
BB
CC
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112 2
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IOIOIO IO IO IO
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1
