GATE-ALL-AROUND MOSFETS BASED ON …...GATE-ALL-AROUND MOSFETS BASED ON VERTICALLY STACKED...

GATE-ALL-AROUND MOSFETS BASED ON

VERTICALLY STACKED HORIZONTAL NANOWIRES

HANS MERTENS,

IMEC, LEUVEN, BELGIUM

Semicon Europa, TechArena, Advanced Materials Session, 15/11/2017

THIS PRESENTATION: SILICON GATE-ALL-AROUND

2

SiGe 40 nm

Si Si

8-nm Si

nanowires

WF metalMetal

gate

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.510

-12

10-10

10-8

10-6

10-4

10-2

Dra

in c

urr

ent (A

)

VGS

(V)

NMOSPMOS

LG = 28 nm

STI

ILINILIN

SiGe

Si

Processing: Device demonstration:

ISAT

OUTLINE

Introduction: Motivation and scope

Process flow animation by Coventor SEMulator3D

GAA device fabrication: SiGe/Si processing, nanowire

release, ...

GAA CMOS based on dual work function metal gates

Summary

3

OUTLINE




release, ...


Summary

4

MOTIVATION

5

FinFET

Gate-all-

aroundPlanar

Gate

Si

Gate-all-around (GAA):

– Optimal electrostatic

control, ultimate CMOS

scaling

Lateral:

– Natural evolution of

FinFETs

Stacking:

– More active volume,

higher drive current Fin

Stack of

lateral

nanowires

Wrapped

by gate

from all sides

STI

Scaling scenario

Illustration of

50% area scaling

per generation*

* Actual pitch scaling per

generation is slowing

down

MOTIVATION

6

N16

N10

N7

N5

N3

90; 64

64; 45

45; 32

30; 24

20; 18

10

20

30

40

50

60

70

80

90

10 20 30 40 50 60 70 80 90 100

Meta

l p

itch

(n

m)

Contacted Gate Pitch, CGP (nm)

50%

50%

50%

N14/N16

MOTIVATION

7

Mx = Metal

LE3 = litho/etch times 3

SADP=Self-aligned dual

patterning

SAQP=Self-aligned quadruple

pat.

SE=single exposure

N16

N10

N7

N5

N3

90; 64

64; 45

45; 32

30; 24

20; 18

193i Mx LE3 cliff

193i Mx SADP cliff

193i Mx SAQP cliff

19

3i C

GP

SA

DP

cli

ff

19

3i L

I L

E3

c

liff

EUV SE cliff

EU

V S

E c

liff

19

3i C

GP

SA

QP

cli

ff

10

20

30

40

50

60

70

80

90

10 20 30 40 50 60 70 80 90 100

Meta

l p

itch

(n

m)


50%

50%

50%

N14/N16 1st challenge:

Patterning cliffs

must be overcome

New patterning

techniques required

MOTIVATION

8

N16

N10

N7

N5

N3

90; 64

64; 45

45; 32

30; 24

20; 18

193i Mx LE3 cliff

193i Mx SADP cliff

193i Mx SAQP cliff

19

3i C

GP

SA

DP

cli

ff

19

3i L

I L

E3

c

liff

EUV SE cliff

EU

V S

E c

liff

19

3i C

GP

SA

QP

cli

ff

10

20

30

40

50

60

70

80

90

10 20 30 40 50 60 70 80 90 100

Meta

l p

itch

(n

m)


FinFET electrostatic limit (~40 nm*)

N14/N16

G G G

C C C C C C C

CGP LG

*Liebmann et al., VLSI

(2016)

2nd challenge:

Contacted Gate Pitch:

- Gate length

- Spacer width

- Contact width

Sufficiently long to

switch off device

MOTIVATION

9

N16

N10

N7

N5

N3

90; 64

64; 45

45; 32

30; 24

20; 18

193i Mx LE3 cliff

193i Mx SADP cliff

193i Mx SAQP cliff

19

3i C

GP

SA

DP

cli

ff

19

3i L

I L

E3

c

liff

EUV SE cliff

EU

V S

E c

liff

19

3i C

GP

SA

QP

cli

ff

10

20

30

40

50

60

70

80

90

10 20 30 40 50 60 70 80 90 100

Meta

l p

itch

(n

m)


FinFET electrostatic limit (~40 nm*)GAA

N14/N16

G G G

C C C C C C C

CGP LG< ~16nm

2nd challenge:

Contacted Gate Pitch:

- Gate length

- Spacer width

- Contact width

GAA: LG scaling

beyond FinFET

*Liebmann et al., VLSI

(2016)

ITRS 2.0 ROADMAP

Lateral GAA in ITRS roadmap:

Confirmation of industrial relevance

Production forecast: 2019-2021

Assumed target dimensions:

Diameter of 6 nm

Vertical pitch of 18 nm

10

Source (2016):

http://www.itrs2.net/itrs-reports.html

http://www.itrs2.net/itrs-reports.html

SCOPE OF THIS WORK

Key features:

Scaled dimensions:

8-nm diameter wires

Stacking of nanowires

CMOS device integration

Restriction:

Stacking limited to 2 nanowires

to limit topography for

downstream processing

11

OUTLINE




release, ...


Summary

12

GAA PROCESS FLOW

13

Starting material: Si wafer

Ground plane formation

SiGe/Si epitaxy

SADP fin patterning

STI fill + fin reveal

Dummy gate patterning

Spacer formation

Embedded S/D epitaxy

ILD0 fill

Dummy gate removal

Nanowire release

Dual WF metal integration

Metal gate fill and CMP

LI1 + LI2 + V0 + BEOL

PMOS

pMetal

nMetal

W fill

Si

NWs

Si S/D

epi

NMOS

GAA PROCESS FLOW

14

NMOSPMOS

Si

Alignment to zero

markers (not shown)

B I/IP I/I



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




GAA PROCESS FLOW

15

Si



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




Si Si0.7Ge0.3

Typical layer

thicknesses: 10nm

GAA PROCESS FLOW

16



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




APF

fin core

Photo

resist

SiO2 HM

SiN HM

GAA PROCESS FLOW

17



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




APF

fin core

SiO2 HM

SiN HM

90 nm pitch

GAA PROCESS FLOW

18



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




45 nm pitch

SiN spacers

GAA PROCESS FLOW

19



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




NMOSPMOS

GAA PROCESS FLOW

20



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




GAA PROCESS FLOW

21



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




SiO2 fill after STI CMP

SiN HM

GAA PROCESS FLOW

22



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




SiGe/Si fins

SiGeSi

SiGeSi

GAA PROCESS FLOW

23



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




a-Si

GAA PROCESS FLOW

24



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




1.5 gate pitch

0.5 LG 1 LG

Nanowire

view

during RMG

processing

S/D epi view

GAA PROCESS FLOW

25



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




Nanowire

view

during RMG

processing

GAA PROCESS FLOW

26



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




S/D epi view

GAA PROCESS FLOW

27



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




SiN spacer

GAA PROCESS FLOW

28



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




SiN spacer

Recessed

SiGe/Si fins

GAA PROCESS FLOW

29



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




SiN spacer

Undoped

Si epi

GAA PROCESS FLOW

30



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




NMOSPMOS

B I/IP I/I

GAA PROCESS FLOW

31



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




S/D Si epi

w/ HDD I/I

GAA PROCESS FLOW

32



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




ILD0 oxide

Dummy gate

GAA PROCESS FLOW

33



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




Dummy gate removed

ILD0 oxide

GAA PROCESS FLOW

34



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




SiGe/Si fins

in gate trenches

GAA PROCESS FLOW

35



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




Lateral

SiGe etch

36



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




Si nanowires

STI

SiN spacer

ILD0

GAA PROCESS FLOW

37



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




ILD0

STI

TiN

TaN

HfO2

pMetal:GAA PROCESS FLOW

GAA PROCESS FLOW

38



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




PMOS NMOS

pMetal

GAA PROCESS FLOW

39



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




PMOS NMOS

pMetal

HfO2

GAA PROCESS FLOW

40



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




PMOS NMOS

pMetal (with nMetal on top)

nMetalW fill

41



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




TiN

TiAl

HfO2

nMetal:GAA PROCESS FLOW

42



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




Nanowires Embedded

S/D epi

Simulated epi volume

is suboptimal

GAA PROCESS FLOW

GAA PROCESS FLOW

43



SiGe/Si epitaxy

SADP fin patterning



Spacer formation


ILD0 fill

Dummy gate removal

Nanowire release




PMOS

pMetal

nMetal

W fill

Si

NWs

Si S/D

epi

NMOS

OUTLINE




release, ...


Summary

44

SHALLOW TRENCH ISOLATION (STI) FOR SILICON GAA

45

SiGe/Si epi: Fin etch: STI:

Si

Restriction on STI densification

SiGe

Si

SiGe

TEM:

~1 nm sharp

SiGe/Si

interfaces

Risk: High thermal budget can lead to

smoothening of the SiGe/Si transitions

SiG

e

STISi

Nitride SiGe

10 nm

SIGE/SI INTERMIXING: DIFFUSION MODEL*

46

-15 -10 -5 0 5 10 150.0

0.1

0.2

0.3

Ge

fra

ctio

n

Depth (nm)

750 °C900 °C

1050 °C

500 600 700 800 900 1000

10-25

10-23

10-21

10-19

10-17

10-15

<~ 1 nm SiGe-Si

interface broadening

for 30-min anneal

50%

35%

Ge% = 20%

Ge d

iffu

sio

n c

onsta

nt (c

m2/s

)

Temperature (°C)

STI densification

temperature for

Si FinFET

Low degree of intermixing for 750 °C for Ge% =

27%

Selected for STI densification

Temperature and

Ge% dependence:

SiGe/Si profile simulations

for 30-min anneal:

Ge% = 27%

* D. B. Aubertine and P. C. McIntyre,

J. Appl. Phys. 97, 013531 (2005)

SIGE/SI INTERMIXING: EXPERIMENT

47

30 min, 900 °C, N2

Annealed

0 20 40 60 80 100 12010

1

102

103

104

105

106

As grown

750 °C

1050 °C

70G

e in

ten

sity (

co

un

ts/s

)

Depth (nm)

900°CSiGe

HAADF-STEM:

As-grown

SiGe

SiGe

SiGe

Ge% = 27%

SIMS data:

Ge% = 27%

Trends from diffusion model

confirmed by experimental

data

Thermal budget

restriction

Image contrast Z2

Si0.73Ge0.27

Is this representative for fins ? See next slides

0 20 40 60 80 100 1200.0

0.1

0.2

0.3

Ge

co

nce

ntr

atio

n (

arb

. u

nits)

Depth (nm)

SIGE/SI INTERMIXING: EXPERIMENT

48

30 min, 900 °C, N2

Annealed

SiGe

HAADF-STEM:

As-grown

SiGe

SiGe

SiGe

Ge% = 27%

STEM vs. SIMS:

Ge% = 27%

Line: SIMS

Dots: STEM

STEM

intensity

(dots)

Good SIMS-STEM

correspondence

STEM suitable for SiGe/Si intermixing

analysis

Applicable to nanostructures, see next

slide

Depth

SIGE/SI INTERMIXING IN FINS

49

SiGe/Si intermixing by STI thermal

budget comparable for narrow fins

and blanket layers (blue vs. green)

STEM methodology applied to narrow fins:

010

20

30

40

50

2x10

4

3x10

4

4x10

4

STEM intensity

(arb. units)

Depth

(nm

)

Depth

-6 -4 -2 0 2 4 60.0

0.1

0.2

0.3

ST

EM

inte

nsity

(arb

. u

nits)

Depth (nm)

Black: Post epi - Blanket

Green: Post STI - Blanket

Blue: Post STI - Fin

STI

thermal

budget

Post-STI STEM

10 nmSTI dens. at 750 °C Sharp SiGe/Si

NANOWIRE RELEASE

50

(111)

Si

Si

SiGe

HCl vapor etch in epi reactor*:

Slow Fast

Application to SADP-defined fins:

Si0.7Ge0.340 nm

Si Si

8-nm Si nanowires

WF

metal

W gate

HCl +rounding

+ RMG

NANOWIRE SIZE TUNING

51

• Starting material: Si wafer

• Well implantations

• SiGe/Si epitaxy

• SADP fin patterning

• STI fill and recess

• Dummy gate

• Spacer

• Embedded S/D epitaxy

• ILD0 (incl. poly removal)

• Dummy oxide removal

• Si nanowire release

• HK + WF metal deposition

• Metal gate fill and CMP

• LI1 + LI2 + V0 + BEOL

Challenge:

Size and

shape control

for

top and bottom

nanowires

with

nanometer

accuracy

Oxidation (top/side)

Oxidation (top/side)

Fin width and profile

Si layer thicknesses

Oxide etch / clean

Clean / oxidation

SiGe/Si selectivity

Process flow: Influence on nanowire size:

NANOWIRE SIZE TUNING

52

GAA module

optimization Epi tuning

Fin profile

optimization

Minimization of

SiGe/Si intermixing

SiGe/Si etch

improvement

Si nanowire corner

rounding optimization

GAA module

set-up

GAA DEVICE STRUCTURE

53

NMOS, LG = 70 nm

WF

metal 8 nm

8 nm

HfO2

W gate

Si

Stacked Si nanowires

Narrow size distribution

Conformal HK/MG fill

45 nm

20 n

m

TEM ALONG NANOWIRES

54

Thick TEM specimen

Along nanowires:

W fill

W gate covers the nanowires:

W fill

WF

metal

WF metalHfO2

Si

Si

10 nm LG = 70 nm

Metal gate shields the nanowires

TEM ALONG NANOWIRES

55

Thick TEM specimen

Along nanowires:

LG = 70 nm

W fill

W gate covers the nanowires:

W fill

WF

metal

WF metalHfO2

Si

Si

10 nm

TEM sample thinning to make W gate transparent See next slide

TEM ALONG NANOWIRES

56

Thick TEM specimen

Along nanowires:

LG = 70 nm

W fill

Si nanowires visible:

Si

Si

Ultrathin specimen

Well-defined NWs over full gate lengthWF metal

Si NWs

HfO2

Ultrathin W

HfO2

10 nm

9.4 8.7 nm

8.9 nm 9.6 9.4

8.4

TEM ALONG NANOWIRES

57

Top Si NW

SiN spacer

HfO2

Bottom

Si NW

Facet attributed to anisotropy of

vapor HCl etch process

Si

S/D

Si0.7Ge0.3

HCl

etch

W fill Top

Si NW WF

metal

RMG

Top Si

LG = 30 nm

20 nm

WF metal

Bottom Si

Well-defined GAA device structure for LG = 30 nm

KEY DIFFERENCES COMPARED TO FINFET

58

1. SiGe/Si epitaxy 2. Low-T STI module

3. Embedded Si S/D epitaxy 4. Si nanowire release in RMG

SiGe/Si stack

with ~1 nm

sharp transitions

Si Si0.7Ge0.3

S/D epi

Gate

Temperature

reduction of

1050 °C to 750

°C to minimize

SiGe/Si

intermixing

SiGe/Si layer

stack confined

below dummy

gate

SiGe sacrificial

layer removal by

HCl vapor etch

process +

HK/MG dep.

STI

SiGe

Si

STI

SiGeSi

ID-VGS CHARACTERISTICS

59

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.510

-12

10-10

10-8

10-6

10-4

10-2

Dra

in c

urr

ent (A

)

VGS

(V)

NMOSPMOS

LG = 28 nm

VDD =

0.9 V

VDD =

50 mV

VDD =

50

mV

Excellent short-

channel characteristics

GP doping

condition: >1E19

cm-3

N- and PMOS on separate

wafers

0.01 0.1 10

50

100

150

200

250

300

350

400

SS

(m

V/d

ec)

Gate length, LG (m)

-1.0 -0.5 0.0 0.510

-13

10-11

10-9

10-7

10-5

10-3

I S (

A)

VGS

(V)

SUBTHRESHOLD SLOPE

60

0.01 0.1 10

50

100

150

200

250

300

350

400

SS

(m

V/d

ec)

Gate length, LG (m)

-0.5 0.0 0.5 1.010

-12

10-10

10-8

10-6

10-4

I S (

A)

VGS

(V)

VDD = 0.9V

LG = 24nm

GAA High GP

Hig

h

GP

Low

GAA

Low

GP

WFIN

5

nm

10

nm

NMOS

FF

High

GPGAA

Low

GP

VDD = 0.9V

LG = 24nm

GAA High GP

Low

PMOS

PMOS: NMOS:

Subthreshold slope reduction by high GP

doping

DIBL AND ION – VT,SAT

61

-0.2 0.0 0.2 0.40

200

400

600

800

1000

I ON (

A/

m)

VT,SAT

(V)

20 25 30 35 400

50

100

150

200

250

300

350

400

DIB

L (

mV

/V)

Gate length, LG (nm)

NMOS

VDD = 0.9V

LG=24-30nm

GAA, High GP

FF, WFIN =

5nm

FF,

WFIN=10nmVDD = 50mV, 0.9V

PMOS

GAA

High GP

NMOS

FF NMOS

GAA

High GP

10n

m

5nm

WFIN

Excellent DIBL for GAA ION – VT,SAT at similar

trend line as FinFET

NMOS:PMOS and NMOS:

* Normalized by

channel perimeter

OUTLINE




release, ...


Summary

62

DUAL WORK FUNCTION METAL GATES

63

NMOS PMOS

20 nm

nMetalpMetal

Previous slides:

NMOS and PMOS devices on

separate wafers

Next slides:

NMOS and PMOS devices on the

same wafer

Dual work function metal gates

for threshold voltage tuning

S

i

S

i

DUAL WORK FUNCTION METAL INTEGRATION

64

PR

TiN

TaN

TiN

HfO2

SiO2

Si

pFET

HfO2

SiO2

Si

nFET

TaN

TiN

HfO2

SiO2

Si

pFET

HfO2

SiO2

Si

nFET

Dry strip + APM

TiN removed

(stop in TaN)

pMetal + TaN

barrier + sacrificial

TiN dep. + litho

Dry removal of

pMetal from

nFET

W-Fill

(W)

TiN 2

TiAl 4

TiN 2

TaN 2

7 n

mTiN 3

HfO2

1.

8

SiO2

Si

pFET

W

2 TiN

8 n

m

4 TiAl

2 TiN

1.

8HfO2

SiO2

Si

nFET

PR

TiN

TaN

TiN

HfO2

SiO2

Si

pFET

TiN

TaN

TiN

HfO2

SiO2

Si

nFET

TiN

TiAl

TiN

TaN

TiN

HfO2

SiO2

Si

pFET

TiN

TiAl

TiN

HfO2

SiO2

Si

nFET

nMetal

deposition by

ALD

Photo

resist

SF6

O2+ APM

PMOS-first patterning scheme developed for FinFET:

DUAL WORK FUNCTION METAL INTEGRATION

65

PR

TiN

TaN

TiN

HfO2

SiO2

Si

pFET

HfO2

SiO2

Si

nFET

TaN

TiN

HfO2

SiO2

Si

pFET

HfO2

SiO2

Si

nFET

Dry strip + APM

TiN removed

(stop in TaN)

pMetal + TaN

barrier + sacrificial

TiN dep. + litho

Dry removal of

pMetal from

nFET

W-Fill

(W)

TiN 2

TiAl 4

TiN 2

TaN 2

7 n

mTiN 3

HfO2

1.

8

SiO2

Si

pFET

W

2 TiN

8 n

m

4 TiAl

2 TiN

1.

8HfO2

SiO2

Si

nFET

PR

TiN

TaN

TiN

HfO2

SiO2

Si

pFET

TiN

TaN

TiN

HfO2

SiO2

Si

nFET

TiN

TiAl

TiN

TaN

TiN

HfO2

SiO2

Si

pFET

TiN

TiAl

TiN

HfO2

SiO2

Si

nFET

nMetal

deposition by

ALD

Photo

resist

SF6

O2+ APM

PMOS-first patterning scheme developed for FinFET:

Is this patterning

scheme compatible

with 3D GAA

structures ?

FABRICATED DEVICES

66

Post-WFM-etch

Top-view SEM:

PMOS NMOS

PWFM

TEM cut

LG = 30nm

LG = 30 nm

PMOS NMOS

PWFM NWFMN/P

boundary

NMO

S

PMO

S

HfO2HfO2

TiAlTiNTa

N

PWFM

removed from

NMOS 20 nm

Conformal WFM

deposition

Removal of pMetal

from NMOS

Well-defined N/P

boundary

NMOS VTH SHIFT BY DWFM INTEGRATION

0.0 0.2 0.4 0.6 0.8 1.00

200

400

600

800

1000

So

urc

e c

urr

en

t, I

S (

A/

m)

Gate-source voltage, VGS

(V)

LG = 28 nm, VDD = 0.9 V

NMOS w/

nMetal

Control:

NMOS w/ pMetal

200-mV shift

HfO2

TiAl

nMetal

on NMOS:

Control*:

pMetal

on NMOS

TiNTaN

* TEM for illustrative purposes (pMetal on PMOS)

HfO2

67

MATCHING VTH BY DWFM INTEGRATION

68

-1.0 -0.5 0.0 0.5 1.010

-11

10-9

10-7

10-5

Dra

in/s

ou

rce c

urr

ent, I

D,S

(A

)


(V)

ID,LIN

6x2 NWs

LG = 30 nm

VDD =

50 mV, 0.9 V

|VT,SAT| =

~0.35ID,LIN

ID,SAT

IS,SAT

PMOS NMOSN- and PMOS devices on

the same wafer

MATCHING VTH BY DWFM INTEGRATION

69

-1.0 -0.5 0.0 0.5 1.010

-11

10-9

10-7

10-5

Dra

in/s

ou

rce c

urr

ent, I

D,S

(A

)


(V)

ID,LIN

6x2 NWs

LG = 30 nm

VDD =

50 mV, 0.9 V

|VT,SAT| =

~0.35ID,LIN

ID,SAT

IS,SAT

PMOS NMOSMinority carriers

generated in nanowires:

S

D

BGIDL in ID and IS

Signature of nanowire

conduction

THRESHOLD VOLTAGE VS. GATE LENGTH

70

0.0

0.2

0.4

0.6

Lin

ea

r th

resh

old

vo

ltag

e, V

T,L

IN (

V)

0 50 100 150 200 250

-0.6

-0.4

-0.2

Gate length, LG (nm)

Similar VTH as

uni-gate control

devices

Validation of

dual

work function

metal integration

scheme

NMOS

PMOS

Uni-gate (control)

Dual-gate (CMOS)

Uni-gate (control)

Dual-gate (CMOS)

OUTLINE




release, ...


Summary

71

SUMMARY: SCOPE

72

GAA:

Natural evolution of

FinFETs:

Improved electrostatics

SUMMARY: SCOPE

73

GAA:


FinFETs:


Industry-relevant:

Illustrated by ITRS 2.0

roadmap

SUMMARY: SCOPE

74

GAA:


FinFETs:


Industry-relevant:

Illustrated by ITRS 2.0

roadmap

GAA device variants:

Trade-offs:

- Drive current

- Electrostatics

- Parasitics

- Layout

flexibility

SUMMARY: SI GAA DEVICE DEMONSTRATION

GAA Si NWFETs with excellent short-

channel characteristics demonstrated:

1. Stacked NWs

2. Scaled dimensions

3. RMG processing

4. Bulk Si substrates

Major differences with bulk FinFET flow:

STI densification at 750 °C Sharp SiGe/Si transitions

Low-complexity GP doping scheme prior to SiGe/Si epitaxy bottom

parasitic channel suppression

75

8 nm

8 nm

HfO2

Si

Si

SUMMARY: SI GAA CMOS DEMONSTRATION

767676

LG = 30 nm

PMOS NMOS

pmetal nmetal

N/P

boundary

NMOSPMOS

HfO2HfO2

TiAlTiN TaN

Vertically stacked Si nanowire transistors

with dual work function metal gates

demonstrated

-1.0 -0.5 0.0 0.5 1.010

-11

10-9

10-7

10-5

Dra

in/s

ou

rce

cu

rre

nt,

ID

,S (

A)


(V)

ID,LIN

6x2 NWs

LG = 30 nm

VDD =

50 mV, 0.9 V

|VT,SAT| =

~0.35 ID,LIN

ID,SAT

IS,SAT

ACKNOWLEDGEMENTS

The GAA team of Imec’s LOGIC DEVICES program

Imec’s (sub-)10nm CMOS partners including, Samsung,

TSMC, GlobalFoundries, Intel, SK-Hynix, Micron,

Qualcomm, Sony, Altera, and Huawei

The European Commission and Regional authorities

for their support of European collaborative projects

Coventor for process simulation software support

77

GATE-ALL-AROUND MOSFETS BASED ON …...GATE-ALL-AROUND MOSFETS BASED ON VERTICALLY STACKED...

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Transcript of GATE-ALL-AROUND MOSFETS BASED ON …...GATE-ALL-AROUND MOSFETS BASED ON VERTICALLY STACKED...