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GAN POWER TRANSISTORS

NEW CONTENDER FOR THE POWER TRANSISTOR THRONE: HOW GAN IS THREATENING THE MOSFET’S CROWN

WHITE PAPER VERSION 1.0

2

PANASONIC GAN POWER TRANSISTORS VERSION 1.0

industry.panasonic.eu

THE CHARACTERISTICS OF GAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

OVERVIEW AND ADVANTAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

GATE DRIVING PRINCIPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PANASONIC‘S HD-GIT STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

RELIABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

END OF LIFE TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SOLVING THE CURRENT COLLAPSE PROBLEM . . . . . . . . . . . . . . . . . . . . . . . . 8

MECHANICAL STRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

TESTING TRAPPING AND CURRENT COLLAPSE . . . . . . . . . . . . . . . . . . . . . . 9

ROBUSTNESS IN APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

APPLICATIONS OF GIT TRANSISTORSSTRESS . . . . . . . . . . . . . . . . . . . . . . . 11

PANASONIC GATE DRIVER IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ADVANTAGES IN APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

TABLE OF CONTENTS

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INTRODUCTION

For more than 35 years, power MOSFETs have dominated the field of power converter design in the low to medium power range. This has been supported by continuous innova-tion in the components structure and related semiconductor technology. Fast switching characteristics and low losses, as well as ease of use in various circuit topologies also con-tributed to their success. At the dawn of a new millennium, however, silicon power MOSFETs are reaching their theoret-ical performance limits, which means that further progress in power supplies and power management systems will no longer be as easy to achieve with these switching elements. Current trends in power supply unit design are focusing on higher efficiencies and power densities, that go beyond the capabilities of the silicon MOSFET technology. Development engineers need new switching devices that are able to meet these requirements. And so begins the conception of gallium nitride transistors (GaN) .

THE CHARACTERISTICS OF GAN

The first GaN power transistors were introduced in the early 2000s, after being used over a decade as a standard fixture in high-frequency technology. The favourable combination of chemical-physical characteristics offered by GaN – such as ten times the dielectric strength of silicon, high electron mobility and carrier density, very fast carrier recombinations, and last but not least a high maximum junction tempera-ture of over 400°C – open up additional prospects for this material.

Applied to power transistors, these characteristics enable the manufacturing of high-switching frequency capable tran-sistors. These in turn improve the power density of power conversion systems, thanks to lower conduction losses, and thanks to a reduction of the typical system size and weight – for example by reducing the size of passive components under fast switching conditions. Gallium Nitride transistors are therefore becoming a realistic and attractive alternative to silicon transistors and start conquering the field of power electronics.

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OVERVIEW AND ADVANTAGES

Panasonic Hybrid Drain-Gate Injection Transistors (HD-GITs) are normally-off GaN-on-silicon transistors. They are based on the HEMT principle, using the highly mobile 2D electron gas forming at an AlGaN-GaN heterojunction as conduction layer. The active part of the transistor is completed on the top side with (ohmic) drain & source contacts, a recessed p-GaN gate (ohmic contact) and a p-GaN “gate like” structure con-nected to the drain. For cost reasons, the transistor is grown on top of 6 inches silicon wafers by MOCVD process. In order to reduce the tensile stress caused by the mismatched crys-tal lattices of Si and GaN, to limit the vertical drain-substrate leakage currents and to prevent deep breakdown paths in the conductive Si substrate, a lattice buffer layer (Figure 1) is inserted between the silicon bulk and the active top side of the transistor.

This buffer plays a central role in the determination of key reliability characteristics of the transistors (Figure 2), as we’ll develop further below. The transistor is turned on resp. off like a field effect transistor, by applying a gate-source volt-age above resp. below a threshold voltage. In off state, the p-GaN gate depletes the electron gas underneath by lifting the potential well of the AlGaN-GaN junction above the Fermi level. In on-state, the gate behaves essentially like a diode. Unlike in MOS transistors however, a small (around 10mA) current is injected from the gate into the conducting layers by electrons tunneling through the AlGaN barrier. Due to the low velocity of holes in the GaN material, the current conduction at the AlGaN-GaN interface is only due to the electron gas, and so the transistors are to be understood essentially as unipolar devices on this regard.

Since the HD-GiT gate can be accessed directly, the gate circuit can be designed to control and adjust the transistor’s du/dt and di/dt – a major advantage as compared with the cascade.

Figure 1 Figure 2

GaN epitaxial

StrainRelaxation

Si (111) substrate

AlNAlGaN

GaN / AlNSuper-lattice Buffer

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The lateral structure of the GiT is also advantageous for fast switching, since its parasitic capacitances are typically lower than those of vertical structures, such as for example sili-con-based super-junction MOSFETs (see Figure 3).

The Figure-of-Merit (RDS(on) ∙ QG) of a 600V/70nOhm GiT is therefore ~350mΩ ∙ nC, in other words around one tenth the value of modern silicon components.

GATE DRIVING PRINCIPLE

The GiT transistor is controlled as mix of a field effect transis-tor and (bi)polar transistor. As with FETs, a positive threshold voltage needs to be applied between the source and gate to open a conductive channel. At the same time, a small on-time current needs to flow into the gate to increase the conduc-tivity of the conductive layer and to keep the switch-on re-sistance as low as possible in the useful operating area. The transistor is switched off by removing the voltage from the gate; the gate current stops, the channel closes, the transis-tor is blocking again. Unlike with IGBTs however, the charge recombinations at switch off do not result in measurable de-lays or power losses due to tail currents (see Figure 4).

Figure 3

Figure 4

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X-GaN™ GiT transistors allow current to flow in the reverse direction once the source, gate, and drain potential are set in a way that current is fed in at the gate. Unlike with MOSFETs the reverse current does not flow through a parasitic body here, instead is it conducted through the channel. Even though they are reminiscent of a diode, the thresholds in the third quadrant of the static IV curve are not dictated by junc-tion’s behaviour, but are simply the threshold voltage of the transistor plus any negative bias voltage that is applied to the gate. In the same way as a MOSFET, the GiT can be switched on in the reverse direction in order to further reduce the loss-es by operating under 0V-offset condition. The GiT recovers extremely quickly from reverse conduction. The recovery en-ergy practically just corresponds to the energy required to charge the output capacitance. The conduction and recovery performances of the GiT in the reverse mode are the same as those of an SiC Schottky diode (see Figure 5).

PANASONIC‘S HD-GIT STRUCTURE

Developers of gallium nitrite components have to deal with the phenomenon of current collapse. When the transistor is under high voltage stress, conduction electrons can become trapped in defects in the crystal, at interfaces between lay-ers etc., which can leads to a rapid increase of the RDS(on) (on-resistance), leading to a rapid increase in losses and the destruction of the components. This effect can be especially critical for hard switched topologies.

So far Panasonic has been the only provider of GaN compo-nents to publicly announce the complete elimination of the problem of current collapse. The figure 6 shows Panasonic’s unique approach for solving the issue. An additional p-doped structure, similar to the gate, is grown near the drain and electrically connected to it. That structure injects holes into the GaN components, that recombine with the trapped electrons.

The HD-GiT uses a recessed gate so that the thickness of the AIGaN layer is increased in order to avoid depletion of the charge carriers under the p-doped area close to the drain. The HD-GiT was proven to have the same excellent switch-ing characteristics as the conventional GiT structure. Failure mechanisms in GaN transistors in general have been close-ly investigated in the past decade and discussed in many papers; a detailed overview can be found for example in. Let’s now review the most important aspects of Panasonic’s X-GaN transistors’ reliability.

GiT reverse recovery behaviour

Cha

nnel

cur

rent

(A)

Vds=300V

Qrr=38nC

15A

GaN-GiT in reverse conduction mode

Qrr=58.5nC Si-FRD

50ns/div

15

10

5

0

Figure 5 Figure 6

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RELIABILITY

In order to guarantee the reliability of the HD-GiT transistors in mass production, Panasonic not only tests against the usu-al JEDEC standards for Si components, but also developed its own additional GaN-specific tests to guarantee the long-term stability of the transistors, for example with regard to current collapse. Accelerated life tests have showed a worst case FiT rate of ~10 FIT can already be achieved. Electron trapping and current collapse.

Electron trapping and current collapse

In the absence of specific technical counter-measures, GaN GiT transistors suffer from electron trapping issues. Generally speaking, these effects are related to the build-up of negative-charged regions in the transistors. This is caused by the trapping of electrons in defects of the crystal and/or at the surface of layers, leading to non-optimal repartition of the electric field in the transistor and disturbing the flow of charge carriers in the 2D gas.

Two trapping effects seem to dominate in GiTs, leading po-tentially to different destruction mechanisms. Specifically it is understood that the traps contributing most to the build-up of the negative regions are i) deep traps in the buffer layer in the drain to substrate region, appearing under high Vds stress and ii) traps located at the AlGaN surface, capturing hot electrons crossing the AlGaN barriers under hard switch-ing conditions in the semi-on state (Figure 7).

First consequence: when a drain-source voltage is applied above a certain threshold – dependent on the device char-acteristics, a bit above 500V for the transistors we are writing about here – the “current collapses”, i.e. from the application point of view the Rds(on) of the transistor increases switch-ing cycle after switching cycle, until it reaches a saturation value. This effect, also known as dynamic Rds(on) typically leads to the rapid destruction of the transistor by thermal breakdown (Figure 7).

Second consequence: the hot electrons captured at the surface of the AlGaN layer in the “semi-on” state under hard switching conditions are suspected to trigger a positive de-structive feedback loop that will see the electric field at the drain side increase due to the trapped charges, causing more trapping at the AlGaN surface, causing a further increase of the electric field etc. until the device breaks down (Figure 8).

0

2

4

300 400 500 600

Drain-Source [V]

On-R

esist

ance

[a.u.

] CONVENTIONALSTRUCTURE NEW STRUCTURE

Figure 7 Figure 8

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SOLVING THE CURRENT COLLAPSE PROBLEM

The first step taken by Panasonic to eliminate the current collapse involved fine tuning the super-lattice buffer and the GaN epitaxial growth to relieve the stress. This approach had a physical limit, a bit beyond 500V in Panasonic’s investiga-tions. This was not good enough given the target of quali-fying 600V transistors, nor was it good enough for actual applications.

The second step was to develop the Hybrid Drain concept (compare page 6). The drain terminal of HD-GIT is connected to an additional gate-like p-GaN structure. In off-state the hybrid drain is effectively in injecting holes under the drain, which appears to counter the current collapse effect in two ways .

First, the hole injection of the p-drain in off-state compen-sates the hole generation in the buffer layer and prevents the region under the gate to become too negatively charged thus ensuring a more uniform repartition of the electric field between gate and drain. Second, the holes emitted by the p-drain recombine with the hot electrons captured in semi-on state as shown by the observation of electro-lumines-cence at the surface of the AlGaN at gate and drain edge. The Figure 8 shows the EL area moving from gate to drain with increased Vgs (and consequently, increased drain current) in GiT transistors .

This indicates a displacement of the peak electric field to the drain side caused by hot electrons trapping at the AlGaN sur-face. It does not happen in HD-GiTs, showing the success-ful suppression of the trapping effect by the hybrid p-drain. As a consequence of introducing the hybrid drain, dynamic Rds(on) cannot be detected anymore in HD-GiTs, at least up to 850V (Figure 4), [1], [2]. The HD-GiT is a major improve-ment in this regard as compared with the conventional GiT, and the resulting transistors are suitable for qualification as 600V devices. All commercialized Panasonic transistors in the X-GaN line up today are based on the HD-GIT technology.

END OF LIFE TEST

The end of life mechanism in the GiT transistors seems to be well modeled by a so-called percolation degradation model, where the accumulation of defects over time along e.g. the path of leakage currents ultimately creates a conductive path that will cause a time dependent breakdown. The life time of HD-GiT transistors is directly related to the p-drain leakage current, by comparing physical models with the Weibull plots of transistors failures under High Temperature Reverse Bias (HTRB) conditions. According to this understanding the thick-ness of the lattice buffer in Panasonic’s X-GaN transistors has been adjusted to limit the p-drain to substrate leakage, aiming at achieve a failure rate over time less than 0.1% for 10 years operation (at Vds=480V and Tj=100°C).

Accordingly the HTRB test is the most critical to assess the lifetime of the X-GaN transistors. It was therefore performed on 10,000 transistors, taken from 20 different lots, far be-yond JEDEC requirements. Data corresponding to 1 billion devices and hours equivalent of operation were accumulat-ed. No failures were observed during the test, proving that the said 10 FiT target set by Panasonic as minimum accept-able level to start the mass production had been achieved.

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TESTING TRAPPING AND CURRENT COLLAPSE

There are no test items in existing standards testing the re-liability of power transistors in regard with electron trapping mechanisms, nor the life time stability of the transistors from that point of view. Based on the understanding of the key trapping mechanisms on the one hand and the understand-ing that these mechanisms worsen with temperature and aging on the other hand (more tensile stress inducing more defects), Panasonic developed a High Temperature Operating Life Time test focusing on such potential quality issues.

The test circuit described in (Figure 10) switches the tran-sistors under worst case hard switching condition, with Vds=600V, and is used in two different ways for the qualifi-cation. In a first test, the Rds(on) of the transistors is stressed with 5,000 pulses, before and after the other aging-related tests (described in Figure 10). In a second test, the same cir-cuit is kept pulsing under high temperature (Ta = 125°C) and the Rds(on) is monitored. No measurable dynamic Rds(on) effects were detected with the first test items, and no signif-icant degradation was measured after over 3,600h testing. Panasonic X-GaN transistors can therefore be considered current collapse free within their operating range and over the life time.

MECHANICAL STRESS

As shortly noted at the beginning of the article, different lat-tice constants and different thermal expansion coefficients create mechanical stress in the chip. One can therefore sus-pect that the interfaces between the buffer and surrounding layers will be sensitive to temperature cycling and aging ef-fects. The X-GaN “super lattice” buffer.

Figure 1 ensures a progressive release of the mechanical stresses. Moreover, Panasonic manufacturing know-how warrantees an excellent uniformity of the deposited layers and crack free wafers after processing. The robustness of the transistors against mechanical stress effects is tested and validated by standard JEDEC temperature cycling and high temperature storage tests.

Figure 10

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ROBUSTNESS IN APPLICATION

Besides extensive testing of the critical aspects affecting the devices’ intrinsic reliability and life time, Panasonic X-GaN transistors also provide robustness by design, contributing to the safe design of application circuits. The first, obvious aspect, consists in the X-GaNs being normally off transis-tors, and appeals no further comments here. There is more however …

Diode gate, doesn’t break

As discussed at the beginning, the gate of the HD-GiT tran-sistors in on state behaves like a diode. This means that there is no breakdown destruction to fear in case of voltage spike on the gate. Gate noise will be clamped by the diode and “absorbed” as transitory peak current. Of course there is a limit to the energy that can be absorbed in this way for thermal reasons. However the data sheet of our 70mOhm transistor for example warrantees comfortable 1.5A resp. 32nC pike values (5 times the maximum continu-ous gate current resp. 6 times the typical gate charge of the transistor) .The safety of the gate circuit is therefore insured by design. This is a significant advantage as compared with other de-vices implementing different gate contact concepts, that im-pose the gate signal to be kept within a very narrow voltage range in on-state, and that are very sensitive to overvoltage breakdown. The benefit comes at a very small cost in the HD-GiT: the small gate injection current drawn by the gate under normal turn-on condition will typically causes gate losses around 10mW, which is neglectable from the point of view of the efficiency of the system.

Extra margin on the breakdown voltage

Unlike MOSFETs, GiT’s lateral structures have no junctions that will avalanche and clamp voltage spikes above the rat-ed breakdown. The GaN material’s wide bandgap property however allows the design of small dies with high break-down voltage. Therefore, to warrantee a fail-safe operation of the transistors for example in the event of line surges, Panasonic X-GaN devices have been designed with a with a big margin on the drain-source breakdown limit. Indeed the static field-dependent breakdown voltage of the currently available transistors qualified for 600V operation is in the range of 900V to 1kV (Figure 11). As a side effect, it allows the X-GaN transistors to be qualified with a Vds spike volt-age rating of 750V for one microsecond. The vertical field dependent breakdown is also in the same 1kV range; the lattice buffer design (again) is playing here a major role in setting this value.

Package

Packaging is one of the most important factors for the reli-ability of power device. X-GaN ensures its quality by adopt-ing a mature molded packaging technology proven with conventional SJMOS. The assembly profile is optimized to reduce the epitaxial mechanical stress. The resin with high insulation resistance, 2.7mm minimum creepage distances to clear industrial safety standards and 0.5mm copper heat pad for good transient heat dissipation are strong features of the 8x8 DFN packages of the X-GaN transistors. Parasitic in-ductance, stray-L by wire, affects GaN’s high-speed switch-ing performance. X-GaN packaging adopts therefore novel techniques to minimize stray-L, as low as 0.7nH for source and 2.9uH for gate. In addition, a Kelvin contact is provided for the source pin. Therefore, the design has no problem even at high frequency of above 10MHz. The transistors are tested against ESD according to JEDEC standards.

500 600Static

700 750Transient

800 900 1000

2

4

6

8

10

Vds [V]

Id [A

]

X-GaN

BreakdownVds > 900V

Avala

nche

Brea

kdow

n

Avala

nche

Proo

f

Si

Figure 11

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APPLICATIONS OF GIT TRANSISTORSSTRESS

In addition to selecting the right topology and gate control scheme, the choice of the gate driver circuit is especially important. Fortunately, a simple and common push-pull gate triggering circuit with separate switch-on and switch-off re-sistors can be used. Figure 12 shows a typical gate circuit for GiTs that can be realised using available high-performance MOSFET gate drivers.

The designer can easily control the switching behaviour of the transistor, as shown on Figure 13 (example of dv/dt control at turn on).

As well as providing the necessary dynamic power during the switching transition, the gate driver must also reliably keep the transistor turned on. The gate input characteristic of the GaN GiT corresponds to a diode. The constant gate current flow through this internal gate diode Dgs during the on-time is controlled by Rig during the on interval (Figure 5).

Finally, keeping the transistor reliably switched off requires attention, because the threshold voltage of GiTs is signifi-cantly lower than the typical level in MOSFETs. Even though the small Crss/Ciss ratio of the X-GaN transistors protects against Miller capacitance coupling effects, a negative volt-age can be optionally applied to the gate during the off time to increase the safety margin.

Figure 12 Figure 13

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PANASONIC GATE DRIVER IC

Panasonic brought out its own X-GaN™ gate driver at the end of 2016 for developers who want to quickly deploy a solution using GiTs. The X-GaN driver IC is optimized for high switching frequencies up to 2 MHz and provides an easy way to unlock the full performance of the transistors. Besides op-timized gate control terminals, additional integrated func-tions are provided – such as a charge pump for (optionally) generating negative gate voltages, or safety features against under-voltage and gate oscillations. (Figure 14).

Figure 14

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ADVANTAGES IN APPLICATIONS

Panasonic’s GiT transistors are aimed at power converters in the ~100W to ~5-6kW range, where MOSFETs with 600V to 650V are typically used today. Depending on the require-ments of the application, developers can target maximum ef-ficiency, maximum power density, or a compromise between the two. Thanks to their “0 reverse recovery” behaviour, GaN transistors make some topologies practically usable, such as for example totem-pole PFCs, which require fewer parts as conventional designs and exhibit state-of-the-art efficiency performance. Increased switching frequency enables pas-sive components to be miniaturized – in particular magnetic components – whereas the power density of circuits such as resonant DC-DC converters can be increased. Last but not least, GaN bring significant efficiency improvements under partial load operation in resonant circuits of this type.

Figure 15

Panasonic has used and demonstrated these capabilities in a highly compact and efficient AC-DC demo unit (Figure 15).

Applications like power supplies for IT, telecoms servers and AC adapters should benefit most from these in the short term. The automotive industry has also demonstrated significant interest in being able to use such components in on-board chargers or DCDCs in the medium term.

After the start of the mass production starts at the end of 2016, Panasonic will further extend its offer of GaN-on-Silicon tran-sistors. After the successful introduction of the 600V versions with on- resistances of 70mOhm and 190mOhm, the line-up is now to be extended with new variants between 40mOhm and 350mOhm. The 600V switches in series production will also guarantee a Vds pulse rating of up to 750V.

WHITE PAPER VERSION 1.0

APRIL 2018

Panasonic Industry Europe GmbHRobert-Koch-Strasse 100 · 85521 Ottobrunn · Germany

Internet: industry.panasonic.eu

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