Future Fab International Volume 45

In Association with: ISSUE 45 – April 2013 – www.future-fab.com

Accelerating the next technology revolution.

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FUTURE FAB International | Issue 45

Welcome …

Nikon. Evolution in Action. www.nikonprecision.com

Nikon continues to evolve the proven Streamlign platform to extend 193 nm

lithography. The NSR-S622D immersion and NSR-S320F dry ArF scanners satisfy

the industry’s most demanding requirements for imaging, overlay accuracy,

and ultra-high productivity, which are essential for cost-effective, leading-edge

multiple patterning applications.

Despite our collective disbelief here in the hallowed halls of Future Fab, it’s April 2013. According to the movies, it’s now 12 years since HAL went nuts in 2001: A Space Odyssey. And yet we still don’t have flying cars, and nuclear war has not been instigated by artifi-cial intelligence (a.k.a. Judgment Day in Terminator 2). So what do we have instead? Well, 450 mm wafers are coming into focus, and we’re proud to have partnered with the G450C. EUV lithography, on the other hand, is seemingly not. It continues to pushed out despite all the talk of it still being viable. What’s of more import to us here is that the end of CMOS is finally a visible blob on the horizon. Although the post-7 nm world is still very much a mystery, realistic ideas of what could succeed silicon and the workhorse CMOS structure are starting to take shape, a potential shakeup that is sometimes hard to fathom. What the planar transistor was to the vacuum tube, the transistor itself will be to whatever comes next. At inflection points such as these, whole industries disappear and are replaced by their new technology progeny. As a case in point, can you name more than one vacuum tube manufacturer? As a publisher, we are dealing with our own inflection points as we first evolved away from print and are now planning a second step into the mobile world. Stay tuned.

The Future Fab Team

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3www.future-fab.com |2 | FUTURE FAB International | Issue 45

CONTENTS | FUTURE FAB International | Issue 45

FUTURE VISIONS & CURRENT CONCERNS

10 Introduction Alain E. Kaloyeros – College of

Nanoscale Science and Engineering, University at Albany

11 Section Sponsor

Hitachi

12 450 mm Era: A New Opportunity for the Semiconductor Industry

John Lin, Paul Farrar – G450C

19 Thought Leadership Profile Total Facility Solutions

22 Industry Alignment on Cost and Time Savings in the 450 mm Transition

Jonathan Davis,1 Frank Robertson,2 Allen Ware3 – 1SEMI 2G450C 3M+W Group

28 Thought Leadership Profile M+W Group

30 How to Survive the Scaling and 450 mm Transition Challenge

Luc Van den hove – imec

NEW TECHNOLOGIES & DEVICE STRUCTURES

33 Introduction Lode Lauwers – imec

34 The Robust Plastic Future Is Available Today Mike Banach – Plastic Logic Ltd

38 M&NEMS: A Technological Platform for 10-Axis Sensor

P. Robert,1 P. Rey,1 A. Berthelot,1

G. Jourdan,1 Y. Deimerly,1 S. Louwers,2 J. Bon,2 F.X. Boillot,2 Joël Collet2 – 1CEA-Leti 2Tronics

LITHOGRAPHY LANDSCAPE

44 Introduction Yayi Wei – GLOBALFOUNDRIES

45 Section Sponsor

Nikon

46 Shifts for EUV Mask Users and Suppliers

Keith Standiford – GLOBALFOUNDRIES

BACK END OF LINE

53 Introduction Jon Candelaria – SRC

54 Interconnect History and Future Prospects: Part 1

Ahmet Ceyhan, Azad Naeemi – Georgia Institute of Technology

METROLOGY, INSPECTION & FAILURE ANALYSIS

60 Introduction Davide Lodi – Micron Semiconductors

61 The Enabling Role of Metrology in the 450 mm Transition Rand Cottle,1 David Nessim,2 Frank Robertson,1 Menachem Shoval3 – 1G450C 2Intel 3Metro450

66 Addressing Nanodefectivity Challenges Jenah Harris-Jones – SEMATECH

69 Quantifying Focus Spot-Related Yield Loss Garry Tuohy – GLOBALFOUNDRIES

WAFER FAB & PACKAGING INTEGRATION

74 Introduction Peter Ramm – Fraunhofer EMFT

Munich

75 Section Sponsor

EV Group

76 Through-Silicon Interposer Technology for Heterogeneous Integration

H.Y. Li, L. Ding, G. Katti, J.R. Cubillo, Surya Bhattacharya, G.Q. Lo – Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research)

82 3D Stacking: Act II Sitaram Arkalgud – Invensas Corp.

87 Advertisers Index

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EDITORIAL PANEL

Paolo A. GarginiChairman International Technology Roadmap for Semiconductors

Dr. Paolo Gargini is also responsible for worldwide research activities conducted outside Intel for the Technology and Manufacturing Group by consortia, institutes and universities. He received doctorates in electrical engineering and physics from the Universita di Bologna, Italy.

Paul A. Farrar, JrGeneral Manager, Global 450mm Consortium (G450C), CNSE Vice President for Manufacturing Innovation

Paul Farrar is General Manager of the Global 450mm Consortium (G450C) and oversees the coor-dination, administration and management of G450C’s strategic, operational and financial missions, including external collaborations with international partner companies, program staffing, and interactions with the G450C Management Council. In addition, he serves as CNSE Vice President for Manufacturing Innovation, where he is responsible for the expansion of CNSE’s intellectual know-how and state-of-the-art programs to convert long-term prospective innovations into busi-ness opportunities and economic development programs across New York. Farrar joined CNSE with more than 32 years of experience in the semiconductor industry. Farrar received a bachelor’s degree and a master’s degree in Materials Engineering from Rensselaer Polytechnic Institute.

Surya BhattacharyaDirector, Industry Development; IME

Dr. Surya Bhattacharya is director, Industry Development, for IME’s Through Si Interposer (TSI) program. He has over 18 years of experience ranging from 0.8 micron to 28 nm CMOS while work-ing in the U.S. semiconductor industry at both fabless companies and integrated device manu-facturers. Surya obtained his Bachelor of Technology degree in electrical eng. from the Indian Institute of Technology Madras, India in 1987, and his M.S. and Ph.D. in microelectronics from the University of Texas at Austin in 1993.

Biographies of Future Fab’s Panel MembersFor the full versions of the following biographies, please click here.

Welcome to our new Panel Member – Paul A. Farrar, Jr

Alain E. KaloyerosSenior Vice President, CEO and Professor, College of Nanoscale Science and Engineering; University at Albany

Alain E. Kaloyeros has authored/co-authored over 150 articles and contributed to eight books on nanoscience, holds 13 U.S. patents, and has won numerous academic awards. He received his Ph.D. in experimental condensed matter physics from the University of Illinois, Urbana-Champaign, in 1987.

Gilbert J. DeclerckExecutive Officer, imec; Member of the Board of Directors, imec International

Gilbert J. Declerck received his Ph.D. in electrical engineering from the University of Leuven in 1972. He has authored/co-authored over 200 papers and conference contributions. In 1993, he was elected fellow of the IEEE. Since July 1, 2009, Dr. Declerck has been executive officer imec and a member of the board of directors of imec International.

Didier LouisCorporate and International Communication Manager, CEA-Leti

Louis joined CEA-Leti (France) in 1985, where he received a Ph.D. in metallurgy/electrochemistry from the University of Grenoble. He has written more than 30 papers related to etching and strip-ping processing and has co-authored more than 60 scientific papers and eight patents.

Shishpal RawatChair, Accellera Systems Initiative Director, Business-Enabling Programs; Intel Corp.

Shishpal Rawat holds M.S. and Ph.D. degrees in computer science from Pennsylvania State University, University Park, and a B. Tech. degree in electrical engineering from the Indian Institute of Technology, Kanpur, India.

Jon CandelariaDirector, Interconnect and Packaging Sciences; SRC

Jon Candelaria has over 34 years’ experience in the electronics industry in a wide variety of engi-neering and managerial roles. He received his BSEE and MSEE from the University of New Mexico.

Yannick Le TiecTechnical Expert, CEA-Leti, MINATEC Campus

Yannick Le Tiec joined CEA-Leti in 1995 and received his Ph.D. in materials science and engineer-ing from the Polytechnic Institute, Grenoble, France, and his M.S. in chemistry from the National School of Chemistry, Montpellier, France. He is a CEA-Leti assignee at IBM, Albany (NY), develop-ing the advanced 22 nm CMOS node and the FDSOI technology.

Alain C. DieboldEmpire Innovation Professor of Nanoscale Science; Executive Director, Center for Nanoscale Metrology, CNSE, University at Albany

Alain’s research focuses on the impact of nanoscale dimensions on the physical properties of materials. He also works in the area of nanoelectronics metrology. Alain is an AVS Fellow and a senior member of IEEE.

Rohan AkolkarSenior Process Engineer, Components Research; Intel Corporation

Dr. Akolkar received the Norman Hackerman Prize of the Electrochemical Society in 2004, and numerous Intel Logic Technology Development awards. He has authored more than 40 technical papers, invited talks, and U.S. patents in the area of electrodeposition.

Christo BojkovSenior Package Development Engineer, TriQuint Semiconductor

Dr. Christo Bojkov has published over 30 publications and holds 15 patents. Since receiving his doctorate in chemical engineering, he has worked and taught in academia for over 10 years in physical chemistry and surface science.

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EDITORIAL PANEL | FUTURE FAB International | Issue 45

Steve GreathouseGlobal Process Owner for Microelectronics, Plexus Corp.; Idaho

Steve Greathouse has published many articles on technical topics related to semiconductor pack-aging, failure analysis and lead-free packaging. He has a B.S. in electronic physics from Weber State University with advanced studies in material science and computer science.

Daniel J.C. HerrProfessor & Nanoscience Department Chair, JSNN; UNC – Greensboro

Dr. Herr is a pioneer in collaborative nanotechnology research. He is professor and chair of the Nanoscience Department at the new Joint School for Nanoscience and Nanoengineering in Greensboro, North Carolina. Until recently, Dr. Herr served as the director of Semiconductor Research Corporation’s Nanomanufacturing Sciences area. He received his B.A. with honors in chemistry from Wesleyan University in 1976 and his Ph.D. from the University of California at Santa Cruz in 1984.

William T. ChenSenior Technical Advisor, ASE (U.S.) Inc.

Bill Chen is the co-chair of the ITRS Assembly and Packaging International Technical Working Group. He was elected a Fellow of IEEE and a Fellow of ASME. He received his B.Sc. at University of London, MSc at Brown University and Ph.D. at Cornell University.

Liam MaddenCorporate VP, FPGA Development & Silicon Technology; Xilinx, Inc.

Liam Madden is responsible for foundry technology, computer aided design and advanced package design. He earned a BE from the University College Dublin and an MEng from Cornell University. Madden holds five patents in the area of technology and circuit design.

Alan WeberPresident, Alan Weber & Associates

Alan’s consulting company specializes in semiconductor advanced process control, e-diagnostics and other related manufacturing systems technologies. He has a bachelor’s and a master’s degree in electrical engineering from Rice University.

David G. SeilerChief, Semiconductor and Dimensional Metrology Division, NIST

David G. Seiler received his Ph.D. and M.S. degrees in physics from Purdue University and his B.S. in physics from Case Western University.

Mark McClearGlobal Director, Applications Engineering, Cree LED Components

Mark McClear is responsible for LED lighting applications development and Cree’s Application Engineering Technology centers worldwide. He holds a B.S. in electrical engineering from Michigan State University and an MBA from Babson College, and has 11 issued and published U.S. patents in electronics, LED and solid state lighting.

Giuseppe FazioAdvanced Process & Equipment Control Sr. Engineer; Micron Semiconductors Italy

With a laurea degree in applied physics from Milan University, Giuseppe has working experience in several sectors, from research to industry, and vast experience in industrial and scientific instru-mentation. He has authored/co-authored many articles, is an avid contributor at conferences and holds several patents in the semiconductor field.

Peter RabkinDirector of Device & Process Technology, SanDisk Corp.

Dr. Peter Rabkin focuses on development of novel 3D memory technologies and products. He holds a master’s degree in physics from Tartu University and a Ph.D. in physics of semiconductors from the St. Petersburg Institute of Physics and Technology.

Sitaram R. ArkalgudVice President of 3D Products, Invensas

Sitaram Arkalgud is vice president–3D products at Invensas, where he recently joined after serv-ing as director of SEMATECH’s Interconnect Division. He has more than 20 years of R&D and manufacturing experience with the chip industry. He has a Ph.D. and a master’s degree in materi-als engineering from Rensselaer Polytechnic Institute, and a B.S. in metallurgical engineering from Karnataka Regional Engineering College, Surathkal, India.

Daniel C. EdelsteinIBM Fellow; Manager, BEOL Technology Strategy, IBM T.J. Watson Research Center

Dr. Edelstein played a leadership role in IBM’s industry-first “Cu Chip” technology in 1997, in the introduction to manufacturing of Cu/Low-k insulation in 2004. He received his B.S., M.S., and Ph.D. degrees in applied physics from Cornell University.

Christian BoitHead, Semiconductor Devices at Berlin University of Technology, Germany

The Berlin University of Technology is an institution for research and development in the areas of device simulation, technology, characterization and reliability. Christian Boit received a diploma in physics and a Ph.D. in electrical engineering on power devices, then joined Siemens AG’s Research Laboratories for Semiconductor Electronics in Munich and has been a pioneer on photoemission.

Pushkar P. AptePresident, Pravishyati Inc.

Dr. Pushkar P. Apte’s strategy consulting firm focuses on the high-tech industry. He received his master’s and Ph.D. from Stanford University in materials science and electrical engineering, and his bachelor’s degree in ceramic engineering from the Institute of Technology, Varanasi, India.

Jiang YanProfessor, IMECAS

Dr. Jiang Yan has authored and co-authored over 40 papers, holds 17 U.S. patents and 10 China patents. He received his Ph.D. in electrical engineering from the University of Texas at Austin in 1999.

8 | FUTURE FAB International | Issue 45

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Peter RammHead of Device and 3D Integration Department, Fraunhofer EMFT; Munich

Peter Ramm received his physics and Dr. rer. nat. degrees from the University of Regensburg. He has authored or co-authored over 100 publications, including three book chapters and 23 patents.

Davide Lodi Baseline Defectivity & Metrology Engineering Manager; Micron Semiconductors Italy

After graduating in physics from the University of Milan, Davide Lodi started working in 1997 for STMicroelec-tronics as a process engineer. After becoming the manager of Wet Processes and Metrology Engineer-ing at the NVM R&D Agrate site, he moved to Numonyx, which was acquired by Micron in 2010.

Stephen J. Buffat Staff Research Scientist, Lockheed Martin NanoSystems

Stephen Buffat is responsible for the startup and operation of Lockheed Martin’s nanotechnology facil-ity and operation in Springfield, Mo. He has authored or co-authored numerous articles on photolithogra-phy, etch and 300 mm surface preparation process technologies.

Ehrenfried Zschech Division Director for Nanoanalysis & Testing, Fraunhofer Institute for Nondestructive Testing; Dresden, Germany

Ehrenfried Zschech received his diploma degree in solid-state physics and his Dr. rer. nat. degree from Dresden University of Technology. He has published three books and over 100 papers in scientific jour-nals on solid-state physics and materials science.

Steven E. SchulzPresident and CEO, Silicon Integration Initiative, Inc.

Since 2002, Steve Schulz has served as president and CEO of Si2, the leading worldwide consortium of semiconductor and software companies chartered to develop EDA standards. He has a B.S. in electri-cal engineering from the University of Maryland at College Park, and an MBA from the University of Texas at Dallas.

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EDITORIAL PANEL | FUTURE FAB International | Issue 45

Klaus-Dieter RinnenDirector/Chief Analyst, Dataquest

Klaus-Dieter Rinnen is director for Dataquest’s semiconductor and electronics manufacturing group. He received a diploma degree in physics with minors in physical chemistry and mechanical engineering in Germany, and a Ph.D. in applied physics from Stanford University.

John SchmitzSVP & General Manager, Intellectual Property and Licensing; NXP

John Schmitz holds a master’s degree in chemistry from Radboud University of Nijmegen, Netherlands, and a doctorate in physical chemistry from Radboud University Nijmegen. He has authored more than 45 papers in various scientific journals and has written books on IC technol-ogy and on thermodynamics.

Lode Lauwers Director Strategic Program Partnerships for Silicon Process & Device Technology, imec

Lode Lauwers has an M.S. in electronics engineering and a Ph.D. in applied sciences. He joined imec in 1985 as a researcher. Lode manages imec’s core partner research program on sub-32nm CMOS technologies.

Janice M. GoldaDirector, Lithography Capital Equipment Development; Intel Corp.

Janice Golda manages an organization responsible for creating strategies and working with Intel’s lithography, mask and metrology suppliers and subsuppliers to deliver equipment meeting Intel’s roadmap technology, capacity and cost requirements. She is a member of the Berkeley CXRO Advisory committee, is Chairman of the Board for the EUV LLC and holds one U.S. patent.

Luigi ColomboTI Fellow

Dr. Luigi Colombo is a TI Fellow working on the Nanoelectronic Research Initiative (NRI). He is author and co-author of over 130 publications, three book chapters, and holds over 60 U.S. patents. Dr. Colombo received his Ph.D. in materials science from the University of Rochester.

Warren SavageChief Executive Officer, IPextreme

Warren Savage has spent his entire career in Silicon Valley, working with leading companies, where he focused on building a global scalable semiconductor IP business. In 2004, he founded, and still leads IPextreme in the mission of unlocking and monetizing captive intellectual property held within semiconductor companies and making it available to customers all over the world. He holds a B.S. in computer engineering from Santa Clara University and an MBA from Pepperdine University.

Yayi WeiPrincipal Member of Technical Staff; GLOBALFOUNDRIES

Dr. Wei investigates advanced lithography processes and materials. He has over 16 years of lithog-raphy experience, including DUV, 193 nm, 157 nm, 193 nm immersion, EUV and E-beam lithography. Dr. Wei has numerous publications and holds several patents in the field of lithography.

FUTURE VISIONS & CURRENT CONCERNSClick here to return to Table of Contents


Hitachi High Technologies America (HTA) designs state-of-the-art dry plas-ma etch tools for world-leading semi-conductor and hard disk drive (HDD) manufacturers. Hitachi’s renowned etch technology, paired with unmatched service and support, provides custom-ers with etch solutions to meet their stringent development and production requirements. HTA delivers performance.

Hitachi etch technology is driving the latest trends in next-generation semi-conductor and HDD devices. As con-ventional flash memory reaches its end of life, Hitachi has new specialized etch tools for vertical NAND. For the latest MRAM, Hitachi has the EMCP etch tool specifically designed and developed to etch the non-volatile materials that sim-ply can’t be processed by conventional etch tools. Hitachi’s EMCP tool not only allows a development group to create

a process test device, it delivers unsur-passed reliability and stability in the manufacturing environment.

Hitachi’s newest etch tool, the HS-9050, is a bulk dry removal etch tool. The HS-9050 is designed to transi-tion away from wet chemical processes that experience surface tension and defect problems to the tight control of a dry etch process. It pairs Hitachi’s lat-est plasma source with the high-speed 9000-Series platform to provide a flex-ible tool delivering the performance of a dry etch tool to replace the traditional wet bulk removal processes.

Beyond Hitachi’s leading etch tech-nology, HTA provides award-winning service support and spare parts man-agement. Add Hitachi etch technology to your processes today and know you’ll be ready for tomorrow’s demanding etch requirements.

Hitachi High Technologies America (HTA) – Superior Etch, Superior Service

This Future Fab section is sponsored by Hitachi

Hitachi XT Next – A Better Way to Etch | www.hitachi-hta.com


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“It is the long history of humankind (and animal kind, too) those who learned to collaborate and improvise most effec-tively have prevailed.” - Charles Darwin

What has been true for the evolution of the animal kingdom has never been truer for the evolution of the nanoelec-tronics kingdom as well. As scaling of devices has been enabled by the devel-opment of new materials and fabrication techniques, increased cost-effectiveness of semiconductor manufacturing has been realized in part by the increase of wafer size. Each successive wafer size transition has involved increasing cost burdens, resulting in a progressively smaller pool of semiconductor companies large enough to undertake such a manu-facturing transformation. This has result-ed in an unprecedented opportunity for unique collaborations between manufac-turers to help propel the industry forward to 450 mm silicon wafer processing.

This issue of Future Fab features the two largest such collaborative models. One article discusses the Global 450 Consortium (G450C), the corporate-academic partnership established at the SUNY College of Nanoscale Science and Engineering (CNSE) by New York Governor Cuomo in November 2011. The G450C facility was ready for equipment

Alain E. KaloyerosSenior Vice President, CEO and Professor, College of Nanoscale Science and Engineering, University at Albany

in February 2013, with 280,000 ft2 floor space and a 60,000 ft2 cleanroom. Under the joint oversight of Intel, TSMC, Samsung, GLOBALFOUNDRIES and IBM, G450C will use the state-of-the-art capabilities established at CNSE for joint development activities and to support a comprehensive industry-wide 450 mm wafer ecosystem.

Similarly, imec’s Luc Van den Hove describes imec’s new 450 mm clean-room, which will be ready for tool instal-lations by the end of 2015. The author argues that imec’s open innovation initia-tive, which has succeeded by bringing together the complete ecosystem (the supply chain and the innovation chain), will be needed to successfully make the transition toward smaller transistors and bigger wafers.

Finally, in the third paper, Jonathan Davis of SEMI, Frank Robertson of G450C, and Allen Ware of the M+W Group tie these unique partnerships to industry-wide standardization trends and key learning and best practices derived from the last wafer size transition from 200 mm to 300 mm wafers. In particular, the authors point out that early adoption of stand-ards allows companies to collaborate in a pre-competitive environment, resulting in greater industry efficiency and a smoother technology transformation.

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FUTURE VISIONS & CURRENT CONCERNS FUTURE VISIONS & CURRENT CONCERNS

The Global 450 Consortium (G450C), announced by New York Governor Andrew M. Cuomo in September 2011 and headquartered at the SUNY College of Nanoscale Science and Engineering (CNSE) in Albany, is leading the industry transition from the 300 mm wafer to 450 mm wafer

production. This first-of-its-kind collabora-tion includes five leading international IC manufacturing companies partnering with CNSE to create the next generation of computer chip technology. The G450C pro-gram integrates key semiconductor IC mak-ers with important equipment and material

450 mm Era: A New Opportunity for the Semiconductor Industry

suppliers, along with the investment from New York State and the vision and leader-ship of Governor Cuomo.

Why 450 mm? Reduce manufacturing cost, stimulate another wave of innovation on equipment and manufacturing methods, and drive toward greener manufacturing.

Semiconductor manufacturing costs have increased rapidly as technology complexity has accelerated at sub-20 nm nodes (Figure 1). Process steps such as multiple patterning, EUV lithography, 3D transistors, channel engineering, atomic-layer deposition (ALD) and novel backend technologies have added costs. Evolving technology drives the need for periodic wafer size increases to maintain historical cost reduction trends.

Wafer size transitions have historically occurred on about a 10-year cycle. As pic-tured in Figure 2, the 300 mm node has

lasted longer as the leading-edge produc-tion node than previous generations. Thus, the transition to 450 mm wafers late in the decade is already later in relation to previ-ous transitions. The 450 mm wafer ramp is now expected to be in 2017–2018 for early adopters.

The 450 mm Benefits On average, a 30% cost reduction was

seen with the implementation of 300 mm wafers from the previous 200 mm cost basis. Some semiconductor manufacturers reported even greater cost benefits. The industry consensus is that the 450 mm wafer can provide similar cost reduction opportunities.

The cost and performance advan-tage from the manufacturing productiv-ity enabled by the 450 mm transition will allow the semiconductor industry to

John Lin, Paul Farrar G450C

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Figure 1. Node-to-node wafer cost increases significantly because of technology complexity. Figure 2. History of wafer capacity for each wafer size transition.



continue to migrate to advanced tech-nology nodes, and with significant cost improvements over technology nodes. This will be a key component of main-taining Moore’s Law. The semiconductor industry’s historic cost reductions have enabled the mobile and interconnected society we live in.

The 450 mm wafer transition provides a great opportunity to stimulate and imple-

ment another wave of innovations on equipment performance. Improvements in uniformity, productivity, process control, automation and manufacturing systems will be required to achieve these cost ben-efits. Figure 3 illustrates the productivi-ties that were achieved with the 300 mm wafer introduction.

Another benefit of the implementation of the 450 mm wafer will be to create new opportunities to achieve a more environ-mentally friendly semiconductor manufac-turing process. During the 300 mm transi-tion, the use of energy, water, chemicals and emissions per unit wafer area were sig-nificantly reduced (Figure 4). Besides sim-ply using smaller amounts of water, chemi-cals and energy in relation to the larger wafer area, the G450C has also set early targets and recommendations for the use of these items. This is being done early in the cycle compared with the 300 mm tran-

sition. The industry is targeting a 30–40% per area saving for 450 mm wafers.

The G450C ProgramTo speed up the 450 mm transition,

three major IC makers (Intel, Samsung and TSMC) reached an agreement in 2008 to collaborate on industry infrastructure development, and to share the industry

tool development cost. More importantly, the collaboration would lead to a syn-chronization of tool suppliers’ schedules, reducing the risk of high development costs, establishing standards, provid-ing test wafers, and shortening the tool development cycles. The three IC makers continued the collaboration to purchase silicon wafers in 2009, and to acquire metrology tools, stockers and initial proto-type tools.

In September 2011, Governor Cuomo announced that the G450C would be established at CNSE. The 450 mm tools will reside in the newly built NanoFab Xtension (NFX, Figure 5). The facility was ready for equipment in February 2013, with 280,000 ft2 floor space and 60,000 ft2 cleanroom. G450C will use the state-of-the-art capabilities established at CNSE for joint development activities and to support a comprehensive industry ecosystem.

450 mm Era: A New Opportunity for the Semiconductor Industry FUTURE VISIONS & CURRENT CONCERNS

Production Indices 300 mm vs. 200 mm

Cycle Time 0.8X

Defect Density 0.4X

People Productivity 2.5X

Equipment Productivity 1.8X

Full Automation Rate Semi � Full Auto

450 mm

Expect moreinnovations toenable furtherimprovements

Figure 3. Many innovations enabled 300 mm transition with significant productivity and engineering improvements.

Figure 5. The 450 mm fab in the NanoFab Xtension (NFX) at CNSE.

300 mm vs. 200 mm (per cm2 silicon processed)

Norm

aliz

ed P

erfo

rman

ce

100

Volatile OrganicCompounds

One member company 2008 data

Electricity

Ultra-Pure Water

Hazardous Air Pollutants

Perfluorocarbons

80

60

40

20

0

45%

60%58%

53%

52%

Figure 4. The 300 mm transition showed considerable improvement from a green perspective. Figure 6. An example of equipment performance metrics (EPM).


Five semiconductor member com-panies—Intel, Samsung, TSMC, IBM and GLOBALFOUNDRIES—are working in part-nership with CNSE. The G450C program is a public-private partnership that will develop equipment prototypes and high-volume manufacturing (HVM) tools, and establish a coordinated test, metrology and wafer program to enable a cost-effec-tive industry transition to 450 mm wafers. In summary, this will synchronize industry efforts by involving the key stakeholders in setting a clear development roadmap and implementation timeline.

The G450C program has established a platform of key objectives. Initially, in the 2012–2014 timeframe, the team is focused on supporting supplier tool development with test wafer capability. Key metrics have been established for defect density, uniformity, and system reliability and pro-ductivity. The program will demonstrate

prietary components in the facility and equipment. The G450C team is working with SEMI and its members on these pre-competitive supplier-identified projects.

Tool and Wafer ChallengesThe G450C team is driving hard on

tool and process performance, and has published equipment performance met-rics (EPM)—tool specification targets for equipment with design-in capability as agreed upon with suppliers—as well as guidance on ESH, facilities requirements and standards compliance. Figure 6 shows the EPM for a representative etch applica-tion. The complete EPM for the 450 mm toolset to be demonstrated during the program using standard demonstration test methods (DTMs) is available on the G450C website (www.g450c.org).

The selection of 450 mm tools has been accomplished. Equipment will be moved

these capabilities using 14 nm (nominal/ITRS half-pitch) unit processes. In the 2015–2016 timeframe, the focus will be on improving tool performance to sup-port customers’ expectations for pilot operations. It is expected that the 450 mm toolset will be continuously improved to enable high-volume manufacturing in the 2017–2018 timeline.

The G450C program staff comprises engineers from CNSE and from each mem-ber company. The expertise of the engi-neering staff will allow for effective col-laboration with the equipment companies’ engineering teams to manage a successful tool demonstration and qualification at the 14 and 10 nm nodes. This unique col-location of equipment and semiconductor companies’ skills will pave the way to a successful industry transition to 450 mm.

Another aspect to the program is to enable early standardization of nonpro-

in and installed between 2013 and 2014, according to the defined schedules. There are about 60 tools that will be tested for ~100 applications to meet the 14~10 nm specs. These tools allow G450C to inves-tigate a full spectrum of processes and measurement needs to ensure successful test wafer demonstration. This site will be the largest 450 mm test bed in the world. The tool ready timeline for each type of tool is shown in Figure 7.

Lithography capability is one of the most strategic elements to ensure success in the 450 mm transition. G450C recog-nizes this critical factor, and is mobiliz-ing resources to accelerate lithography tool development and delivery to G450C. The tool will likely be delivered to G450C in 2015 and HVM tools will be ready in 2017–2018. Automation is also a key for successful 450 mm process and produc-tion. G450C will implement automation

Figure 7. The G450C 450 mm tool demonstration plan. Figure 8. The 450 mm development roadmap.

450 mm Era: A New Opportunity for the Semiconductor Industry FUTURE VISIONS & CURRENT CONCERNS


Future Visions & Current Concerns


Thought Leadership Profile

The look on your face as you read the title above is probably somewhere between intrigue and bemusement. Don’t worry; this is normal. You’ve probably not been on the receiving end of this order since you were a child. It is, however, one of those phrases that crosses all bounda-ries of society, language and culture, and is one of the first environmental safety and health edicts we are taught and that we in turn teach to our children.

It is pretty self-explanatory that the essence of the message is to forewarn the inexperienced of an everyday hazard that can cause numerous undesirable results, ranging from mere cuts to fully removed digits or worse. This statement is neither law nor threat; instead, it is the simple transfer of learned experience to a new generation through communication. Simple in execution and, yet, should you not have heard this message in your formative years and instead experienced the consequences of tripping while carrying scissors at speed, your perspective might well differ.

The concept of an injury-free workplace is of course several orders of magnitude

more complex than the mere cessation of rushed scissor conveyance. But when taken in its base form, it comprises a promise of similar clarity: “I am committed to an inju-ry-free workplace where everybody goes home safe each and every day.”

This is indeed the culture established at Total Facility Solutions (TFS). Its Incident and Injury Free® (IIF) initiative takes a proactive approach to safety and is a key factor in reducing and eliminating unsafe behaviors and conditions in the workplace. An IIF program is a mindset embraced throughout the company, in which all employees recognize their responsibilities to themselves, fellow workers and their families to do their work safely.

IIF is a culture that believes:• All injuries are preventable.• Every individual is responsible to work

toward the elimination of all injuries.• Injuries are not accepted as part of

doing business.• Free and open safety communications

are essential.• It’s about caring for one another and

demonstrating you care on a daily basis.

Never Run With Scissors! Core Values for an Injury-Free Workplace

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hardware and software connecting tools in the fab and trace the entire wafer process to enable advanced control on equipment and processes.

The G450C team also continued the previous effort to drive the wafer quality. Silicon manufacturers have been able to produce wafers meeting M74 mechanical handling wafer spec in 2011. They are com-mitted to meet the M76 monitoring wafer spec by 2013 and meet the M1 prime wafer spec in 2014.

To lower development costs, G450C offers a wafer loan program to the 450 mm community. This allows tool suppli-ers to obtain high-quality wafers for tool development, with substantial discounts in wafer cost. G450C will also offer metrol-ogy assistance and process capability to provide measurement and materials need-ed for tool development. The program goal is to provide cost-sharing opportuni-ties to assist tool suppliers.

G450C is representative of all industry constituencies—the Management Council includes executives from all chipmaker member companies, CNSE and suppliers through its associate members and SEMI. G450C is also coordinating with EEMI450 entities in Europe, Metro450 in Israel, and the SEMI Equipment Supplier Group in Japan to avoid duplicated effort and address issues through global collaboration.

Roadmap and Future EffortsG450C has coordinated industry collabo-

ration through member companies repre-senting IC manufacturers, equipment suppli-ers and their suppliers, a facility group, and material suppliers. This serves to align the timeline for tool installation and demonstra-tion between 2012 and 2014, with the major-ity of suppliers providing early production tools for IC makers’ pilot lines in 2015.

The wafer development is on sched-ule, with the M1 wafer to be ready in 2014. Illustrated in Figure 8, the readiness of high-volume manufacturing is driven by lithography development, with the sched-ule on track for 2017–2018.

About the Authors

John Lin John Lin, an assignee of TSMC, was

appointed vice president and general man-ager of operation of G450C in March 2012. Prior to joining G450C, he was director of TSMC’s Manufacturing Technology Center, and has held various manager positions in semiconductor technology development and manufacturing. Lin holds 59 U.S. pat-ents and is author/co-author of 25 papers. He received his Ph.D. in optoelectronics from the University of Oxford. He won the award of Outstanding Contribution Engineer from the president of Taiwan in 2008

Paul FarrarPaul Farrar was appointed general man-

ager of G450C and CNSE vice president for manufacturing innovation in September 2012. Prior to his appointment, he was vice president for strategic alliances for IBM Microelectronics. During his 34 years at IBM, Farrar held various executive posi-tions in semiconductor process develop-ment, manufacturing, and product line management. He has a master’s degree in materials engineering from Rensselaer Polytechnic Institute (RPI).


450 mm Era: A New Opportunity for the Semiconductor Industry

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• It’s about taking action when you see potentially unsafe behaviors or condi-tions.

• It’s about an attitude of choosing to fol-low the rules and procedures (vs. having to follow them).

The foundations of the above are sim-ple, but profound. It’s a pledge to each other and to the company to speak up, to get involved, and to not take the easy route and remain silent. It sounds easy, but ask yourself this: How many times have you not intervened when you’ve seen someone in your workplace or in any part of your life who is about to make a minor error? TFS encourages an open policy

when it comes to safety by encouraging its own and others to take responsibility for their actions while having the cour-age to speak up when unsafe acts arise. Employees must believe that an incident and injury free worksite is attainable, and must be willing to accept the responsibility needed to reach the stated goals.

A truly injury-free workplace is attain-able only through a comprehensive shift in corporate culture, having everyone—from part-time contractors to the highest levels of management—all taking responsibility for the end goal: the removal of risk. But how do you achieve that? Though risk is inherent in many workplaces in numerous forms, its avoidance starts with communi-

cation. But it also requires the removal of fear. An employee’s fear of disparagement for speaking out is often the foundation for communication breakdowns that sow the seeds for accidents both small and large. At TFS, employees are encouraged to speak up on behalf of themselves and those around them without fear of reper-cussion and with solid backing from the management team. In fact, we celebrate those who identify hazards and report them or fix them as they arise.

It sounds simple, but encouraging com-munication while enabling employees to speak out is not the easiest task, especially in the large, diverse companies that make up an industry like the semiconductor busi-ness. However, the benefits outweigh the costs in this instance, and not just in terms of employee safety but also in real-world economics. In worst-case scenarios, acci-dents can cost lives; in less serious cases, long-term injury. And, although it might seem obtuse in the extreme to measure health against fiscal impacts, the fact is that there are economic penalties for all accidents: Time lost, compensation, etc.

With proper communication, teamwork and the correct safety measures in place, we as a company can make sure we are doing the best thing for our employees and our bottom line. So why isn’t everyone implementing these practices across the board, you may ask? You know it’s funny; we’ve been asking ourselves the same question. We never run with scissors—nei-ther should you.

Total Facility Solutions’ vision is to be the preferred, single-source provider of process-critical infrastructure for customers in the semiconductor, life science, renewable energy, and sci-ence and research industries.

Joe CestariPresident

Mike Anderson Executive Vice President/ Chief Operating Officer

Chris Walton Vice President, East Region

Robert Hill Vice President, West Region

Joe MinerVice President, Electrical

Total Facility Solutions 1001 Klein Road Suite 400Plano, Texas 75074Phone [email protected]

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The virtues of collaboration in the extraordinarily complex and capital-inten-sive business of microelectronic technol-ogy development have been long recog-nized and are only becoming more impor-tant as transition to manufacturing on 450 mm wafers accelerates.

Commercial wafer fabs are dependent on intricate synchronization and inter-operability of hardware, software and other technology that is provided from numerous companies around the world. Both chipmakers and their suppliers ben-efit from coordinated planning activity. Consequently, the industry has developed many ways to achieve alignment and efficiency, including roadmaps, consortia-facilitated activity and standards develop-ment, to name just a few.

Formation of the Global 450mm Consortium (G450C), announced by Governor Andrew Cuomo in September 2011 and based at the College of Nanoscale Science and Engineering (CNSE) in Albany, N.Y. (Figure 1), provided a clearer sense of customer commitment to 450 mm development. It also repre-sented significant opportunity to increase levels of collaboration as the semiconduc-tor industry implements the capability to manufacture its products on larger wafers.

By agreeing early in the transition on elements of chipmaking operations ranging from interoperable physical interfaces and components to streamlined methods for installation, the industry can save time and money. Another example of collaborative dialog is seen with the Facilities 450mm Consortium (F450C), a consortium formed in collaboration with G450C to focus on facilities and fab installation issues.

Standardization contributes to the effi-ciency of the industry in ways that provide significant benefits to all participants. A 2007 National Institute of Standards and Technology (NIST) study estimated $9.6 billion in benefits between 1996 and 2011

Industry Alignment on Cost and Time Savings in the 450 mm Transition

from standard test methods and software standards.

One of the most highly respected and effective platforms for semiconductor man-ufacturing technology collaboration occurs under the purview of SEMI Standards. This international consensus-based program was established in 1973, with clear proce-dures and attention to anti-trust, copyright and intellectual property sensitivities. To

foster openness, transparency and inclu-sion, SEMI Standards activities are open to all interested parties, including chip manufacturers, suppliers, trade organiza-tions and government agencies. Worldwide distribution of document drafts and ballots facilitates global consensus-building and helps achieve a common alignment toward complex technology development.

Standardization is strongly motivated by the need to establish consistent defini-tions and specifications that can be relied upon to function over time. However, standards are not static. They adapt and are revised as new learning occurs.

Over the past 40 years, all aspects of an automated fab have been addressed through a structure that includes thou-sands of industry volunteers, 23 global technical committees and 200 task forces. This formidable infrastructure has resulted in the current availability of more than 800 SEMI Standards and Safety Guidelines that are globally accessible through SEMIViews, a comprehensive online repository and document management tool.

Learning From the 300 mm Experience

At the last wafer size transition, a num-ber of standards for physical interfaces and carriers were defined before proto-types were available, or in some cases before component concepts were firmed up. Despite good intentions to provide design frameworks, the lack of data on functionality, reliability and interoperabil-ity led to repeated modifications of the standards and an extended period before they were finalized.

Industry adoption of new standards depends on a critical mass of customer support and adequate implementation

Jonathan Davis,1 Frank Robertson,2 Allen Ware3 1SEMI 2G450C 3M+W Group

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Figure 1. The G450C is based at the College of Nanoscale Science and Engineering in Albany, N.Y.

Published SEMI 450 mm Standards & Auxiliary information

Assembly & Packaging

• SEMI G88-0211 – Specification for Tape Frame for 450 mm Wafer

• SEMI G92-0412 – Specification for Tape Frame Cassette for 450 mm Wafer

Physical Interfaces & Carriers (PIC)

• SEMI E154-0612 – Mechanical Interface Specification for 450 mm Load Port

• SEMI E156-0710 – Mechanical Specification for 450 mm AMHS Stocker to Transport Interface

• SEMI E158-0912 – Mechanical Specification for Fab Wafer Carrier Used to Transport and Store 450 mm Wafers (450 FOUP) and Kinematic Coupling

• SEMI E159-0912 – Mechanical Specification for Multi Application Carrier (MAC) Used to Transport and Ship 450 mm Wafers

• SEMI E162-0912 – Mechanical Interface Specification for 450 mm Front-Opening Shipping Box Load Port

• SEMI AUX023-1211 – Overview Guide to SEMI Standard for 450 Wafers

Silicon Wafers

• SEMI M1-0812 – Specification for Polished Single Crystal Silicon Wafers

• SEMI M49-0912 – Guide for Specifying Geometry Measurement Systems for Silicon Wafers for the 130 nm to 22 nm Technology Generations

• SEMI M52-0912 – Guide for Specifying Scanning Surface Inspection Systems for Silicon Wafers for the 130 nm to 11 nm Technology Generations

• SEMI M62-0912 – Specifications for Silicon Epitaxial Wafers

• SEMI M74-1108 – Specification for 450 mm Diameter Mechanical Handling Polished Wafers

• SEMI M76-0710 – Specification for Developmental 450 mm Diameter Polished Single Crystal Silicon Wafers

• SEMI M80-0812 – Mechanical Specification for Front-Opening Shipping Box Used to Transport and Ship 450 mm Wafers

Figure 2. Industry adoption of new standards depends on a critical mass of customer support and adequate implementation guidance.



guidance (Figure 2). SEMI F107 for an Adaptor Plate was defined at 300 mm with the intent to enable pre-facilitating and rapid installation of fab equipment; it was not widely specified by customers, and suppliers did not generally ship the adaptor plates ahead of the tools to pre-install. The transition to 450 mm presents an opportu-nity to improve the implementation of tem-plates for time and cost savings.

A major emphasis on environmental objectives and compliance with safety and ergonomics standards occurred during the 300 mm wafer transition. It resulted in increased attention to these elements during the design and certification of new tools. It is critical that these focus areas continue to be emphasized going forward. Compliance with SEMI EHS Guidelines, including S2 (EHS Guidelines for Semiconductor Manufacturing Equipment) and S8 (EHS Guidelines for Ergonomics Engineering) will again be a required part of demonstrations at G450C.

Even where international standards already exist, there is potential to improve compliance and implementation, and learn-ing from pilot projects on new concepts

may lead to new standards. Where stand-ards are not yet established, consortial working groups help focus industry priories.

Collaboration on 450 mm Standards

Guided by customer requirements, SEMI Standards task forces are working on key issues such as the technical parameters for 450 mm silicon wafers, physical interfaces, carriers, assembly and packaging. To date, SEMI has 10 task forces working on 450 mm, and has published 15 450 mm stand-ards with 16 more in the pipeline.

The Specification for Polished Single Crystal Silicon Wafers (SEMI M1-0812) was revised and published in August 2012. The new edition includes a significant addition of a 450 mm polished single-crystal sili-con wafer specification and the guide for specifying 450 mm wafer for 32, 22 and 16 nm technology generations. Standardized parameters include edge profile, warp, con-ductivity, dopant and surface conditions.

Industry alignment on the dimensions for wafer thickness and carrier slot pitch was an early success for 450 mm. The agreement on 925 vs. 825 μm thickness,

which was extrapolated from the recent diameter increase thickness trend, repre-sented a compromise between customer drive for the thinnest and lowest-cost wafer possible and supplier concerns on robustness in handling. The 2 mm increase in wafer spacing to 12 mm balanced mar-gin for gravitational sag and process-induced warpage with carrier volume and productivity. In both cases, significant test data was brought to bear on the industry’s deliberations, and standards were set in a timely manner.

To ensure viable factory integration solutions up front, leading proponents of 450 mm worked with suppliers during early co-development of component pro-

totypes and international standards to run many millions of cycles of individual and interoperating components (wafers, carri-ers, load ports, wafer handling robotics), feeding data requested by SEMI’s volun-teers into the engineering assessment for standards. The overall result was a reduc-tion in the time to finalize the standards of about 60% compared with the equivalent duration for 300 mm.

Based on this proven effectiveness, the G450C program will use SEMI-standard wafers and carriers and verify compliance with a broad set of SEMI standards for physical interfaces and fac-tory connectivity in 450 mm equipment demonstrations.

Industry Alignment on Cost and Time Savings in the 450 mm Transition FUTURE VISIONS & CURRENT CONCERNS

Figure 3. The time it took to finalize 450 mm standards was only 60% what it took for 300 mm standards.

SEMI

Equipment Suppliers

Sub-Component

Suppliers

F450C

Facili�es Systems, Component,

Service Suppliers

Device Makers

Facili�es Council

Standardiza�on WG

Op�mized Sizing Effec�ve Base Build/fit-up

Reference Designs for Non-Differen�a�ng Components

Standard Connec�onsStreamlined Installa�on

EHS Improvements

Test BedGuidelines

Standards

Prototypes

• Iden�fy Focus Areas/Concepts• Define Pilot Work• Demo Feasibility of Approaches• Drive Timely Adop�on

Figure 4. A number of groups working on 450 mm have identified key issues and are aligning on approaches to address them.


Further Standardization Opportunities

A number of groups working on 450 mm have identified key issues and are aligning on approaches to address them (Figure 4). Some equipment companies have provided insight on components for potential standardization while the F450C proposed a number of projects for con-sideration. G450C’s Facilities Council and Standardization Working Group prioritized a short list from these opportunities for immediate action, and plans are being defined for rapid initiation.

Facility Considerations Bringing 450 mm to reality is not only

a daunting task from a technical and manufacturing standpoint, but as we con-sider the facility infrastructure it becomes apparent that merely scaling the new facil-ity is not a practical option. The size of the 450 mm facility superstructure and related

• Supplier requests for customer conver-gence: uniform safety sign-off; consist-ency of procurement documentation; reduced range of fab layout/equipment configurations.

• Materials conservation imperatives related to technology trends in time-frame of 450 mm (e.g., helium capture); pump idle mode.

Multiple parties are engaged in discus-sion of further standardization opportuni-ties among global organizations. There is agreement between G450C and groups in Europe and Israel on harmonizing contami-nation requirements at both the tool and facility levels. SEMI regional working groups have also proposed further development of standards for predictive carrier logistics, secure recipe management and a recess for longer-stroke load port robot to enable higher wafer transport plane in 450 mm tool platforms. There is also industry-wide support for further detailing industry EHS best practices to help with sustainability.

ConclusionProgress on the transition to 450 mm

wafers is being made with a variety of col-laborative engagements among consortia, standards bodies and industry representa-tives from the IC makers, and equipment and materials companies. Consortia activ-ity will drive industry agreement on a focused set of early concepts that can be designed in to save time and money, and reduce risk, in developing and deploying 450 mm capability.

The SEMI Standards program allows companies to collaborate in a pre-com-petitive environment to codify specifica-tions, definitions and guidelines that result in greater industry efficiency. Together, the industry will be learning from the past

infrastructure consumption projections will simply exceed affordability realities or resource availability constraints.

These roadblocks can be addressed only through standardized solutions developed in collaboration with facility experts across the entire supply chain (Figure 5). M+W, as a leading design/builder of technical facili-ties, in consultation with G450C, has begun to coordinate with premier semiconduc-tor facility companies around the globe to bring their collective expertise to bear on the most pressing facility issues. These col-lective companies form F450C.

F450C Charter Based on discussions to date, suppliers’

and IC makers’ priorities for pre-competi-tive cooperation include:• Pilot projects: “hoist” survey; wet station

utilities’ actual use to minimize over-engineering; etcher consolidated points of use; and adaptor plate installation.

and looking to the future as the prospects of manufacturing semiconductors on 450 mm wafers gains momentum.

About the Authors

Jonathan DavisJonathan Davis is global vice president

of advocacy and a member of the Global Executive Team at SEMI. Davis has served at SEMI for more than 20 years in various management positions, including president of the Semiconductor Business Unit; presi-dent of SEMI North America; and executive vice president of global expositions, com-munications, marketing and EHS.

Frank RobertsonFrank Robertson is vice president and

general manager, industry interface and program strategy at the Global 450mm Consortium (G450C). He began work on the 450 mm transition in 2005 while managing external programs for Intel, assuming his current position as an assignee at the found-ing of G450C in 2012. Prior to joining Intel in 2000, Robertson had been chief operating officer of International SEMATECH and gen-eral manager of I300I.

Allen WareAllen Ware is vice president, program

executive for the 450 mm consortium for M+W U.S. Inc. He joined M+W Group in September 2011, having previously worked at Intel as director, facilities materials & services. He is retired from the U.S. Army, where he served in a variety of Corps of Engineers assignments.


Industry Alignment on Cost and Time Savings in the 450 mm Transition

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E-MAILthis articleFigure 5. Bringing 450 mm to reality will require not just a mere scaling of facilities.

FUTURE VISIONS & CURRENT CONCERNS





With the research activities started within the Global 450mm Consortium (G450C) in 2011 and its recently founded Facilities 450mm Consortium (F450C) sub-group, significant progress is being made to define the unique challenges and obstacles we must overcome to make 450 mm manufacturing a reality, sustainable and cost-effective. The plan is to develop potential solutions to these challenges by the end of the calendar year.

As the process of research and inves-tigation gets into full swing, the enormity

of the scale of a 450 mm fab is beginning to come into focus, and with it interesting juxtapositions in relation to the 300 mm transfer back in the early 2000s. The ele-phant in the room is the scale of these new facilities: Another 2.5x jump in surface area means equivalent leaps in the resources needed to process wafers, which in turn will have significant impact on facility site selection and facility design.

The preference is to place a fab where there are already other fabs in existence so that the infrastructure to transport prod-

ucts, materials and services is already in place, as are basic utilities such as power, natural gas and water supply. However, the scale of the expected utility demand at 450 mm ups the stakes somewhat. For instance, a large 300 mm facility cur-rently uses about 4 million gallons of water per day, whereas a 450 mm fab (with the same wafer output) will use almost double that, putting immense strain on a location’s infrastructure should there be other fabs in the region. This will weigh on future site selections immensely, and could see regions that had previously not been appealing now hold sway.

One outcome of this phenomenon is that the reduction, reclaim and reuse of materials will no longer be driven only by the desire to be a good corporate citizen, but will also be driven by cost control and to ensure availability of required resources such as power, water, specialty gases and chemicals.

Today, state-of-the-art semiconductor fabs are already fairly efficient with respect to water recycling/reuse and with energy-efficient mechanical systems. However, with the resources needed to keep a 450 mm facility running, we’ll need to take this to a new level and will need to develop solutions for other materials (some spe-cialty gases and chemicals, for example) as the worldwide supply for them becomes constrained.

M+W Group is recognized as the lead-ing global engineering, construction and project management company in the fields of Advanced Technology Facilities, Life Science & Chemicals, Energy & Environmental Technologies, and High-Tech Infrastructure.

Headquartered in Stuttgart, Germany, M+W Group has a global workforce of more than 7,000 employees, and is the worldwide leader in the design and con-struction of 300 mm semiconductor wafer fabrication facilities, including the first fab to operate at 28 nm geometries. Recently selected by the University at Albany’s College of Nanoscale Science and Engineering (CNSE) as an associate member for facilities and infrastructure for the Global 450mm Consortium (G450C), M+W will spearhead development of new facility and infrastructure technologies and manage building and facility suppliers selected to participate in the program.

Allen WareVice President Program Executive for F450C

Don YeamanDirector of Technology

M+W U.S. Inc. – A Company of the M+W Group 125 Monroe StreetWatervliet, NY 12189Phone 518.266.3400www.mwgroup.net

Business Contact

Aimée RobichaudCorporate Communications Manager

Phone [email protected]

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and Considerations

Today’s Common Tools With No Commonality



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For the past five years, mobile commu-nication and mobile computing have been the main drivers for the IC industry and for the need to scale down transistors. This trend will continue. High-value connectiv-ity will be in the background of everyday lives, connecting people to people and people to their environments.

Tremendous OpportunitiesMore new opportunities are on the

horizon. Chips will be integrated to enable new diagnostic devices for improved, faster and point-of-care diagnostics. These tremendous opportunities to develop a personal health management system, together with the ever-continuing demand for increased connectivity, will drive the IC industry in the coming years.

Moore’s Law has made today’s applica-tions possible through a continuous cost reduction of transistors, enabling more system complexity, functionality and performance. Scaling will continue to be important for this purpose, but we are fac-ing times in which scaling will no longer automatically be translated into cost reduction. Unprecedented opportunities and challenges will shape the IC landscape in the coming years.

The complexity of scalingDevice scaling from the 45 nm technol-

ogy node to the sub-10 nm node has to deal with many different device architec-tures and material systems. FinFETs and nanowire-based tunnel FETs are being developed in R&D centers, with metal gates, high-k materials, high-mobility channels and carbon nanotubes. With this myriad of scaling routes, scaling is becom-ing more and more complex. Furthermore,

How to Survive the Scaling and 450 mm Transition Challenge

to achieve performance gain at the system level, 3D technology is needed to stack memory on top of logic, analog on top of digital, etc.

Scaling also requires dedicated lithog-raphy solutions. With the delay of EUV lithography, there is a risk that the road-map is slowing down. Since no EUV is available today, techniques like double and triple patterning must be used. However, this leads to a tremendous rise in cost. Key for the coming years will be to get EUV ready because this is the only way to get the cost down for aggressively scaled pitches such as the 14 nm node.

A Cost-Effective 450 mm Wafer Transition

EUV lithography will be key to enable cost-effective scaling. But transitioning toward a larger wafer size can also con-tribute to staying on the cost curve related to Moore’s Law. Going from 300 mm to 450 mm wafer sizes could reduce costs by

30% because of the production efficiencies it would bring. However, a cost reduction with the 450 mm transition is not a given. Major innovations will be needed.

First of all, we must consider the wafer-based processes like deposition, etch and cleaning. For 450 mm, new bodies have to be developed, wafer handling has to be innovated, and the process has to be optimized. In this case, we can achieve an efficiency benefit of a factor of 2.25.

The situation is very different, however, for die-based processes such as implanta-tion, inspection and lithography. Here, in terms of cost reduction, you don’t gain anything by going to a larger wafer size. Again, innovations are needed for body development, wafer handling and process optimization. The throughput will stay the same while using a more expensive tool.

For lithography, for example, there are many challenges when transitioning to 450 mm. A bigger wafer stage is need-ed—some 3–4x heavier than for 300 mm wafers. This implies that when using the same stage speed, the acceleration forces will be much higher. As a consequence, the acceleration must be reduced to achieve the same overlay specs. To main-tain the same throughput, major innova-tions will be needed.

Luc Van den hove Imec

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Figure 1. Lab-on-a-chip prototype device for improved, faster and point-of-care diagnostics. Figure 2. A 450 mm wafer.

Figure 3. The imec campus with a 200 mm, 300 mm and soon a 450 mm R&D facility.


NEW TECHNOLOGIES & DEVICE STRUCTURESClick here to return to Table of Contents

The two papers in this section talk about widely differing applications: flexible displays and 10-axis M&NEMS sensors. The common ground, though, is that both are based on new technolo-gies that have been refined and opti-mized in R&D labs for a long time, and that are now transferred for actual fabri-cation. This, of course, presents a totally new set of challenges, including finding the commercially attractive and viable applications to ensure a solid uptake.

The first paper, by Mike Banach (Plastic Logic), is about plastic elec-tronics and their application in flexible displays. Once a pure R&D subject, flex-ible displays are now on the technology roadmaps of the major display makers. And market research indicates an enor-mous potential. The technology has suc-cessfully taken the step from the lab to

Lode LauwersVice President Sales Core CMOS and Strategic Accounts, Imec

the fab. According to Banach, the next challenge will be for innovative product designers and brand owners to make the best use of the unique form factors ena-bled by these displays.

The second paper is by Philippe Robert and colleagues from CEA-Leti and Tronics. To overcome some of the limitations of existing MEMS technol-ogy, CEA-Leti has developed a new technology combining micro- and nano-electromechanical systems (M&NEMS) technologies. The basic idea is to com-bine on the same device a thick MEMS layer for the inertial mass with a thin and narrow NEMS part as suspended silicon nanowire strain gauge. The platform has been transferred to the fab (Tronics) for the design and fabrication of a motion sensor chipset that fully leverages the M&NEMS strengths.

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An Open-Innovation CampusIndeed, major innovations will be

needed in the domain of device scaling, lithography and 450 mm tool and process development. Obviously, the required R&D budget to tackle these challenges will increase—at a higher rate than the avail-able R&D budget. We will see a significant consolidation in the IC industry, at the supplier side as well as on the IC manu-facturing side. With fewer players in the game, it will be important to organize R&D in the most efficient way. Collaboration in an open-innovation mode is definitely the best way to address both the increasing R&D costs and the enormous technological challenges.

This is where imec wants to make a contribution. With its large expertise in setting up open-innovation programs around the most critical issues in scaling, imec is ready to take on this challenge too. The open innovation initiative has suc-ceeded by bringing together the entire ecosystem—the entire supply chain, and the entire innovation chain. The same kind of initiative will be needed to successfully make the transition toward smaller transis-tors and bigger wafers.

The first phase of transitioning to big-ger wafer sizes mainly deals with equip-ment development and early tool testing. In this stage, the equipment suppliers will have to take the lead, and in this context the Global 450 Consortium (G450C) is very important. Meanwhile, imec will also set up a 450 mm R&D facility and do some initial 450 mm tool testing in its cleanroom extension next to its 300 mm R&D facility, which was built three years ago and is fully compatible with 450 mm wafers.

By the end of 2015, imec’s new 450 mm cleanroom will be ready for tool installa-tion. In this full 450 mm process R&D facil-

ity, imec and its R&D partners will focus on materials, process and device develop-ment, which has always been the strength of imec. In this environment, we will con-tinue to develop a strong value proposi-tion to both the supplier community and the IC manufacturers. Also, we will be developing a platform where fabless and fablite companies can test out new tech-nology options for the sub-10 nm node.

We are convinced that the only way to tackle the enormous challenges lying ahead of us is through very extensive col-laboration. In this way, we will reach the innovation level that we need to make these phenomenal transitions.

About the Author

Luc Van den hoveLuc Van den hove received his Ph.D. in

electrical engineering from the University of Leuven in Belgium. He joined imec in 1984, and in 1988 became manager of imec’s micro-patterning group. In January 2007, he was appointed as imec’s execu-tive vice president and chief operating officer (COO), and in 2009, he became CEO. He has authored or co-authored more than 100 publications and confer-ence contributions.


How to Survive the Scaling and 450 mm Transition Challenge

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NEW TECHNOLOGIES & DEVICE STRUCTURES NEW TECHNOLOGIES & DEVICE STRUCTURES

Today’s world is heavily reliant on elec-tronic devices. No longer reserved for the techie or the deskbound office worker, electronic devices have become so prolific, compact and mobile that business execu-tives are regularly to be met with three devices or more simultaneously on the go, and no self-respecting teenager would dare be sighted without the latest in smartphone technology.

However, the rising number of electron-ic devices has also led to increased reports of device breakage. A common factor is screen damage, be it a tablet, smartphone or a dedicated e-reader. This is due to the fact that, although the devices themselves have evolved dramatically over the past 20 years, the basic display technology has remained rigid with several layers of glass.

Recent advances in the area of organic electronics, however, represent the advent of an alternative display technology: plastic flexible displays that are already commercially available for product inte-gration. This new generation has displays that are slimmer, lighter and much more durable than their glass counterparts, with extremely low battery consumption. Since they can be fabricated in any shape and conformed to any surface, they are not only well suited to replace glass displays

in many current electronic devices, but will also enable truly unique product form fac-tors in a whole range of new devices.

Flexible components and devices ena-bled by printed or plastic electronics have already caught the imagination of science fiction writers and product designers. Initially, though, the technology did not appear to be capable of passing the pro-totype stage. This was primarily due to the challenges of carrying out precision engi-neering on plastic. Though flexibility might be an attractive product feature, handling thin plastic films through a multiple-stage fabrication process represents a huge manufacturing challenge.

Several industries, such as graphic arts, employ roll-to-roll processes in which these handling issues can be overcome by applying tension to the film. Many plastic electronics firms are successfully using roll-to-roll processes to make working devices. However, a glass-based display in a standard e-reader device has more than 150 pixels per square inch and its fabrica-tion demands structuring to dimensions several times thinner than a standard sheet of paper. This type of precision alignment is currently too demanding for most roll-to-roll processes, so a new sheet-fed strat-egy needed to be developed.

The Robust Plastic Future Is Available Today

It is difficult to develop a consistent display-making process on a thin plastic sheet because it simply does not have the same dimensional stability as a sheet of glass. Additional obstacles become appar-ent even after a viable sheet-fed process is developed, temperature being one exam-ple. Traditional display and silicon chip fabrication processes include several bake steps at temperatures well over 300°C. Standard engineering plastics are designed to melt at temperatures below 200°C to make it viable to cast or mold them in their molten state.

Even with these known obstacles, every major display maker continues to include flexible displays on its technology roadmap. This further justifies the market potential of this class of devices, but also means that there are several tactics being explored to overcome the considerable manufacturing challenges.

Plastic Logic’s specific journey to developing a manufacturing process for flexible displays has run in parallel with and to a certain extent also been a driv-ing force behind the development of the plastic electronics industry. The founda-tion of this industry was motivated by the vision that a new class of plastic materials can perform the same semicon-ductor functions as silicon. In fact, the replacement of active silicon components with plastic results in several advantages for the fabrication of flexible displays. It enables a much lower temperature profile during fabrication, which in turn permits the use of standard polyester films. Another benefit is the improved dimensional stability at lower processing temperatures. Finally, using the plastic electronics approach has allowed not only the removal of glass, but also sev-

eral other brittle ceramic layers normally used in display fabrication.

As yet, Plastic Logic is the only compa-ny worldwide with a process and volume manufacturing facility capable of reliably producing flexible plastic displays at yields comparable to those of the LCD industry. Nevertheless, market research companies recognize that this is indeed a market des-tined for considerable growth. According to Transparency Market Research, the market for displays enabled by organic or plastic electronics will be worth $16.74 bil-lion in 2018.[1]

Furthermore, two international stand-ards organizations, IPC and IEC, have recently initiated specific committees to define standards for the printed electron-ics industry. The first meeting for the IEC TC119 Printed Electronics Standards Committee was held in Seoul, Korea, in May, and was attended by delegates from the 10 countries most advanced in this industry. Though it will take some time for actual standards to emerge, the interna-tional acceptance that they are required offers further proof that ubiquitous plastic electronics is on its way.

Standards will encourage coopera-tion between technology firms, enabling a faster transition from lab to fab. But this transition is already complete for flexible plastic displays. Both color and mono-chrome flexible electrophoretic display components can be reliably manufactured in a wide variety of shapes and sizes. The next challenge is finding innovative prod-uct designers and brand owners to make the best use of the unique form factors enabled by these displays. Their extreme durability makes them attractive for tra-ditional e-readers in challenging environ-ments such as schools or factories.

Mike Banach Plastic Logic Ltd

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Also, a great wealth of applications for this breakthrough technology exists, some of which are already known. More still have yet to be discovered. For example, Gartner sees a potential for flexible displays to be used for advertising wrapped around columns in shops or in window displays, which communicate with potential cus-tomers, displaying personalized adverts on their smartphones as they pass by.[2]

Since this flexible plastic display tech-nology is ultra-light and super thin, gener-ally it can be said that as the display size increases it will be the weight that becomes the most attractive feature, with peripheral devices for smartphones emerging that will have the look and feel of a sheet of paper. Conversely, as the display size decreases, it will be the formability of the display that will be the biggest asset. Imagine a single display with the information density of your smartphone and the durability of your watch that is easily configured to wrap around your wrist, the handlebars of your bike, or your shopping cart.

Electrophoretic displays are both reflec-tive and multi-stable. Products made from these displays will be daylight readable and have exceptionally long battery life. These attributes coupled with form fac-tors enabled by flexible displays are ideal for portable devices. Plastic Logic recently added color to its displays based on elec-trophoretic deposition (EPD), and has showcased how animation effects can be designed into the display control systems.

Both of these innovations will further enhance the way a user can interact with the current generation of flexible display-based devices. The next generation of flex-ible displays will unlock a whole new prod-uct class where vibrant colors and multi-media content are required. Several display technologies are being developed for use

with flexible backplanes, including elec-trowetting, electrofluidic, liquid crystal and of course organic LED (OLED). Each one of these technologies is capable of achiev-ing the color performance and update rates required to show multimedia content. Several companies have already fabricated prototypes devices, and in the coming years this will lead to real products.

Flexible displays are only the start of a wave of products enabled by plastic electronics. This can best be illustrated by taking a closer look at the technology that enables a flexible display: A flexible plastic display component consists of a front-plane, which is the display medium, and a backplane that is fabricated using plastic electronics. In a display, the backplane operates as an output device, with its high-density array of switches supplying the correct voltage levels to every pixel. However, the very same backplane can also be used as an input device, and there is considerable interest in flexible sensor technologies. For example, a digital X-ray sensor that could conform to the body immediately becomes a much more effec-tive imaging device. The backplane itself is actually comprised of millions of individual transistors. In the future, smart packaging will include a series of these transistors configured to complete complex logic operations to offer end users additional security or brand promotion opportunities for products.

Plastic electronics also has great poten-tial for the area of smartcards. These pock-et-sized cards are as ubiquitous as coins and banknotes. What was once introduced as a method of payment for payphones is now used for fares on public transit, expensive purchases online, or to gain access to high-security buildings. These plastic cards can take on any number of

functions and become ever more sophisti-cated in their functionality as they do.

The fact that they are made of plastic rules out the option of integrating small displays made of glass. However, as the demands on the functionality of smart-cards rise, the need for display integra-tion is ever more apparent. A further key benefit of the plastic display technology is the fact that it is easier to integrate com-ponents. Right now, the smartcard indus-try is being held back because the circuit, display and sensor components neces-sary for these devices need to be sourced separately and then somehow attached together on a single rugged, plastic card in a robust and cost-effective way. Plastic electronics technology enables the circuit-ry, which runs the sensor and the display, as well as connecting them together, to be prefabricated on the card, making integra-tions much simpler and cost-effective.

Plastic electronics is a young tech-nology, which at its core represents the transition from traditional rigid manufac-turing paradigms to more customizable techniques. Eventually, it will dovetail with the emerging 3D-printing revolution to allow consumers the ultimate flexibility in designing new products.

The rallying call for the silicon indus-try was Moore’s Law, which motivated an entire industry to compress ever increasing processing power into an ever decreasing area and package. The success of the plastic electronics industry will be defined differently: Processing circuitry will be processed over ever expanding areas to make every surface you contact “smart-er.” Compared with the silicon industry, plastic electronics has come a long way in a very short time. The interest in flexible display technology is extremely diverse and ranges from e-readers to watches to

displays on kettles. It is paramount that business development professionals in other market sectors for flexible electron-ics take note that perhaps the most valua-ble applications will emerge in areas where you least expect them.

References1. Transparency Market Research,

“Organic Electronics Market Global Market Analysis and Forecast, 2012-2018.”

2. Gartner Inc., “Emerging Technology Analysis: Printed Electronics Creates New Set of Applications” (2011), p. 7.

About the Author

Mike Banach Mike Banach is director of research at

Plastic Logic, and brings 15 years of expe-rience in plastic electronics to the team. He joined the company in 2003 after completing his doctorate in physics at the University of Cambridge.


The Robust Plastic Future Is Available Today NEW TECHNOLOGIES & DEVICE STRUCTURES

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NEW TECHNOLOGIES & DEVICE STRUCTURES NEW TECHNOLOGIES & DEVICE STRUCTURES

MEMS technology has enabled millim-eter-scale sensors requiring milliwatt-level power, resulting in the widespread prolif-eration of sensors in practically all sectors, including industry, consumer, medical, automotive and more. Further reductions in size (and therefore cost) of these MEMS sensors is likely to result in lower perfor-mance because simple physics shows that reducing various device parameters (e.g. mass and capacitance) will decrease signal-to-noise ratio (SNR).

To overcome the limitations of exist-ing MEMS technology, CEA-Leti has developed a new design and detection

mode combining micro- and nano-elec-tromechanical systems (M&NEMS) tech-nologies. The basic idea is to combine on the same device a thick MEMS layer for its inertial mass with a thin and narrow NEMS part as suspended silicon nanowire strain gauge.

9-Axis M&NEMS SensorThis new approach was presented for

the first time by Robert et al. for accel-erometers.[1] This approach combines a MEMS part, which is sensitive to inertial forces, and a NEMS part for detection, which consists in a suspended silicon

M&NEMS: A Technological Platform for 10-Axis Sensor

gauge of the nanometer-scale section (Figure 1). The two parts can then be opti-mized independently.

The advantages are that most of the inertial force is picked up by the gauges, there is a strain concentration due to the highly reduced section of the gauge, and there is an amplification due to a lever arm effect. All these elements lead to particu-larly high sensitivity.

Compared with existing capacitive transducers used in MEMS, M&NEMS piezoresistive nanowire transducers have important advantages. One is the MEMS sensor miniaturization by a factor of at least 2, made possible by nanowire trans-ducers occupying much less area than capacitive transducers.

Also, the performance trend of piezore-sistive sensors is favorable because their cross-sectional area is reduced. A reduc-tion from 2.5x2.5 μm2 to 0.25x0.25 μm2, for example, amplifies the output signal by two orders of magnitude because the strain is concentrated over a smaller area. Taking into account the magnification of the nano-scale gauge, and the design lever effect, this concept leads to a total stress magnification of few thousand compared with conventional piezoresistive sensors.

A “universal” MEMS concept and plat-form allows very simple three-axis detec-tion, with no need for complex technology with top and/or bottom electrodes for out-of-plane detection. In-plane and out-of-plane detections are all obtained on the

P. Robert,1 P. Rey,1 A. Berthelot,1 G. Jourdan,1 Y. Deimerly,1 S. Louwers,2 J. Bon,2 F.X. Boillot,2 Joël Collet21CEA-Leti 2Tronics

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Figure 1. M&NEMS in-plane accelerometer Figure 2. Three-axis accelerometer

Figure 3. Three-axis magnetometer

Figure 4. M&NEMS gyroscope and focus on the nano-gauge



same silicon layer and with the same nano-gauge structure (and electronics).

A three-axis accelerometer (Figure 2),[1] three-axis magnetometer (Figure 3)[2] and three-axis gyroscope (Figure 4),[3] all based on this M&NEMS platform, have already been demonstrated. It allows straight, nine-axis inertial sensor fusion, all integrated at the chip level.

This is a strongly differentiated approach. With more than 15 patents, this new concept and technology can offer a dynamic and strong IP differentiation that grows every year

Beyond the high-level integration offered by the M&NEMS concept, this sen-sor platform paves the way to a process standardization and process mutualization. Hence, high gain in efficiency and cost can be expected in terms of development, cycle time and risk by capitalizing on mod-eling, technology progress, characteriza-tion, reliability, electronics and more.

M&NEMS Pressure Sensor—Toward the10-Axis Platform

An innovative pressure sensor is now in development to expand the sensor offer-ings of this platform. We recently demon-strated an ultra-compact and high-perfor-mance absolute pressure sensor based on the M&NEMS approach.

The concept is illustrated in Figure 5. The pressure applied to the membrane induces a bending and therefore a vertical displacement at its center. This displace-ment induces an out-of-plane rotation of the lever arm around a pivot. From this rotation, a compressive/tensile stress aris-es in the piezoresistive nano-gauges.

Compared with state-of-the-art pie-zoresistive pressure sensors, this configu-ration offers several interesting character-istics:• The nano-gauges are physically sepa-

rated from the membrane and sus-pended in the reference pressure cav-

ity. Therefore, they are protected from external harsh environments and com-patible with high temperatures (no leak-age current).

• Mechanical transduction through the lever effect allows an easy implementa-tion of self-test electrode that can be used for calibration and/or for atmos-pheric pressure compensation.

• The stress induced on the nano-gauges is a unidirectional compressive/tensile stress leading to an efficient and linear transduction.

• A counterweight can be added to sup-press acceleration sensitivity.

• Multi-sensor platforms can be eas-ily implemented. Inertial sensors using an identical transduction scheme and the same process flow (except for the magnetic material) have already been reported.

• Additionally, the lever arm allows inde-pendent optimization of the membrane with respect to the piezoresistive detec-tion.

A 20 bar pressure sensor has been designed (Figure 6). The piezoresis-

tive gauges have been optimized for high dynamic range, and the rest of the device for small footprint. Following those guidelines, we obtained a design with a mechanical footprint of only 0.04 mm2 (200x200 μm), as shown in Figure 6. The total footprint goes up to 0.4 mm2 when wafer-level packaging and electrical con-tact pads are included.

Industrial TransferThe M&NEMS platform is currently

being transferred to Tronics. Within a two-years timeframe, the team develops 6-DOF, 9-DOF and higher DOF devices, where all sensing elements are using the same technology. The first-generation product is a 6-DOF monolithic MEMS achieving a die size below 4 mm2, fol-lowed by a 9-DOF of <5 mm2. This high level of integration and commonality sim-plifies the associated control and readout electronic circuits both in terms of design and operation efficiency.

The initiative involves Tier 1 pilot cus-tomer and well-established industrial part-ners to ensure its fit with market needs and its rapid convergence to actual prod-ucts. In addition, leading ASIC suppliers are contributing their expertise to design a motion sensor chipset that fully leverages the M&NEMS strengths.

To comply with the volumes required by consumer applications, Tronics plans to support the technology all the way to high-volume 8 in. production maturity.

References1. P. Robert et al., “M&NEMS: A New

Approach for Ultra-Low Cost 3D Inertial Sensor,” IEEE Sensor Conference, 2009.

2. D. Ettelt et al., “A Novel Microfabricated High Precision Vector Magnetometer,” IEEE Sensors, p. 2010-2013, 2011.

M&NEMS: A Technological Platform for 10-Axis Sensor NEW TECHNOLOGIES & DEVICE STRUCTURES

Figure 6. Colorized SEM image of the fabricated transducerFigure 5. Schematic cross-section view of the pressure sensor


François-Xavier BoillotFrançois-Xavier Boillot holds an M.Sc.

in micro- and nano-technologies from Polytechnic National Institute of Grenoble, France. He joined Tronics in 2008 as a project engineer, and designed several custom MEMS. He was also design leader for the ultra-miniature three-axis accel-eometer platform TRIO200. Now Tronics’ lead designer for consumer MEMS, Boillot is responsible for the 6-DOF and 9-DOF design on M&NEMS technology.

Joël ColletJoël Collet holds an M.Sc. in micro-

electronics from ISEN, Lille, France, and a Ph.D. in microelectronic materials from Lille University. After a few years as a project manager at ISEN, working on process sim-ulation for Philips BiCMOS process optimi-zation, he joined Tronics in 2000. As a key process engineer, he has been involved in several of Tronics’ process developments (wafer-level vacuum packaging, DRIE over cavity dry process flow, TSVs, etc.), and is inventor or co-inventor of more than five patented IPs. Collet is now in charge of M&NEMS nanowire process transfer and industrialization at Tronics.


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focus on designing advanced micro and nano sensors and developing transduction methods at the nanoscale.

Yannick DeimerlyYannick Deimerly received his B.S from

the National Polytechnical Institute of Grenoble in 2007. In 2010, he received his master’s degree from a joint program of the University of Turin, EPFL and INPG. He is currently pursuing his Ph.D. in the field of microsystem inertial sensors at CEA-Leti.

Stephan LouwersStephan Louwers holds an M.Sc. from

Eindhoven Technical University, and a Ph.D. in chemical technology from the Eidgenoessische Technische Hochschule Zürich. He has more than 20 years’ expe-rience in advanced silicon processing, and has worked for a several companies, including STMicroelectronics, Intel, Atmel and Philips Semiconductors. After join-ing Tronics in 2011, Louwers was involved in the M&NEMS technology transfer pro-ject, and is now head of the business unit Contract Manufacturing.

Julien BonJulien Bon holds an M.Sc. in micro-

electronics from Polytechnic National Institute of Grenoble, France. He joined Tronics in 2001, after a first experience with smart cards test development at STMicroelectronics. In the first years as a test and product engineer, he worked on a variety of sensors, then became head of engineering and product industrializa-tion and led various MEMS development efforts. Bon is now managing the Multi-Sensor Technologies Business Unit, and is in charge of project management related to M&NEMS technology transfer.

3. A. Walther et al., “3-Axis Gyroscope With Si Nanogage Piezo-Resistive Detection,” MEMS 2012 Conference, 2012.

About the Authors

Philippe RobertAfter various positions in industry,

Philippe Robert, Ph.D., is manager of the MEMS Sensors Group at CEA-Leti. He has authored or co-authored about 40 journal papers and conference contributions, and holds more than 40 patents dealing with MEMS and NEMS. He was member of the IEEE-MEMS Technical Committee in 2007 and 2008. He is European co-chair of the ITRS MEMS Technology Working Group.

Patrice ReyPatrice Rey received his engineer diplo-

ma from the Ecole Nationale Supérieure de Physique de Grenoble in 1986 and his Ph.D. in 1990 from INPG. He joined the MEMS department at CEA-Leti in 1990, and has been in charge of several MEMS pro-jects. He participated in the development of micro pressure sensors, force sensors, accelerometers, RF switches, and ultra-sonic transducers. He is the author or co-author of 15 patents in the microsystems field.

Guillaume JourdanGuillaume Jourdan, alumnus of the

physics department of the Ecole Normale Supérieure de Cachan, he received an M.S. from the University of Paris XI in 2004, and a Ph.D. from the University Joseph Fourier in 2007. He was involved in Casimir force measurement and nanomechanics issues from 2004 to 2007. Since 2008, he has been working at CEA-Leti on the field of MEMS and NEMS. His research activities

M&NEMS: A Technological Platform for 10-Axis Sensor

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Nikon Corporation has been one of the world’s leading optical companies for more than 90 years. Nikon devel-oped the world’s first production-worthy step-and-repeat photolithography tool in 1980. Since then, more than half of all ICs printed have been manufactured on Nikon steppers and scanners.

With a long-established precedent of leading the industry through inno-vation and the continuous evolution of our proven lithography solutions, Nikon provides photolithography sys-tems spanning the range of resolutions required by today’s IC manufacturers. From high-throughput i-line steppers to advanced ArF immersion scanners for the most demanding multiple-pattern-ing applications, Nikon delivers superior performance with the lowest cost of ownership, and the most comprehen-sive customer support of any manufac-turer.

In 2009, Nikon released the NSR-S620D immersion scanner with the newly developed Streamlign platform to meet the stringent requirements for 32 nm double patterning and provide extendibility to next-generation appli-cations. This was followed in 2011 by

the NSR-S320F, a Streamlign platform-based system designed to deliver excep-tional performance and productivity for the most critical dry ArF applications.

In 2012, the Streamlign platform was further evolved with the introduction of the NSR-S621D immersion scanner, which satisfies the challenging overlay and throughput requirements for 20 nm technology and beyond. Recently, Nikon launched the NSR-S622D, the latest evo-lution of the established Streamlign plat-form. The S622D is the most advanced scanner for high-volume immersion lithography, and provides the necessary imaging, overlay accuracy, and ultra-high productivity that are essential for cost-effective, leading-edge multiple-patterning applications.

Next-generation lithography tech-niques continue to evolve, but IC mak-ers need solutions today that will keep them on their aggressive technology roadmaps. To meet this challenge, Nikon continues to advance the proven Streamlign platform to extend 193 nm technology. With a history of innovation and evolutionary lithography solutions, Nikon will be there to ensure you main-tain your production timelines.

Proven Solutions Through Evolution

This Future Fab section is sponsored by Nikon

Nikon. Evolution in Action. | www.nikonprecision.com


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LITHOGRAPHY LANDSCAPEClick here to return to Table of Contents

Masks used in advanced photolithog-raphy are made by an electron-beam lithography process in the mask shop. The mask creation flow includes design release, optical proximity correction (OPC) implementation, data tapeout and transfer to mask shop (so-called GDS-out data), pattern generator (PG) data format conversion, and e-beam expo-sure.

During the data conversion to PG format, minor data manipulation might occur to correct simple mask process errors. For example, these manipula-tions could include shifting all edges by a fixed value (a global bias) to overcome CD targeting errors and adding spatial correction maps to address global CD uniformity signatures (loading effects or center-to-edge CD trends).

At 32 nm half-pitch node and beyond, source-mask optimization (SMO) is a common practice, and patterns in mask must have very high fidelity to the GDS-out design. Deviations introduced in the mask man-

Yayi Wei Principal Member of Technical Staff, GLOBALFOUNDRIES USA

ufacturing process must be corrected in a detailed manner, including mask linearity and electron backscattering effect. Mask linearity error, caused by short range e-beam proximity effects (<3 μm), becomes significant in the overall lithography error budget. In par-ticular, an EUV mask blank has a mul-tilayer structure with a tantalum-based absorber layer. Electron backscattering effect is much more pronounced than on conventional photomask substrates. This heavy backscattering effect leads to patterning distortion, which can-not be corrected by the traditional approach through in-tool correction algorithms installed on the current e-beam system. Consequently, an addi-tional data preparation, called mask process correction (MPC), is required prior to exposure.

Where should this correction be per-formed in the mask data flow? In this section, a researcher from a leading semiconductor manufacturing company shares his vision on this topic and sug-gests pattern modifications, similar to OPC, should be applied by the maskmak-er. Additionally, more mask specifica-tions have been proposed to ensure the mask quality.

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LITHOGRAPHY LANDSCAPE LITHOGRAPHY LANDSCAPE

Given the resolution limitations of tra-ditional optical lithography at 193 nm, the continued shrink of technology nodes in the semiconductor industry has forced the adoption of multiple patterning or pitch multiplication strategies that increase the chip production costs. The introduction of extreme ultraviolet (EUV) lithography is expected to alleviate these limitations and reduce the number of masking layers with a corresponding reduction of wafer pro-duction cost.

The EUV mask structure generates many new challenges for the mask pat-terning processes. Here we discuss the additional mask process corrections (MPCs) that will be required to compen-sate for increased electron-beam scatter-ing during the patterning of the EUV mask blank. These corrections will also require enhanced specifications for mask perfor-mance. We will show one new such speci-fication based on chip reliability concerns. These issues will drive the adoption of new paradigms for the interface between mask user and supplier.

Mask Manufacturing and MPCMasks are typically patterned using 50

keV e-beam tools. The e-beam impacting the substrate at the top center of Figure

1a generates backscatter and second-ary electrons within the blank substrate. Many of these electrons reach the surface, and contribute to the resist exposure of nearby figures. These dose errors vary with the surrounding pattern density and distribution, and can add more than 40% to the incident dose. These “e-beam prox-imity errors” in dose lead to very large CD variations.

For conventional mask substrates, these effects can reasonably be characterized by a Gaussian distribution with about a 9–10 μm sigma. The maskmaking tool can cor-rect these errors by building a density map for the input pattern and modifying the doses for each figure on the mask during the mask printing process.

EUV mask blanks show a significantly increased electron backscatter[1,2] com-pared with traditional optical masks, as shown in Figure 1b. This stronger back-scatter behavior introduces CD errors that the conventional proximity effect correc-tion implemented on the mask patterning tool cannot correct adequately because the scattering range is too small. The range over which one pattern influences another also goes well beyond the range considered by optical proximity correction (OPC) algorithms. To correct these errors,

Shifts for EUV Mask Users and Suppliers

new mask process correction (MPC) soft-ware is required.

Some work on MPC software has already been reported.[5,6] Logically, MPC should be inserted into the existing mask data flow after OPC has been done and before the final conversion to the e-beam patterning tool format. We have previously argued that MPC should be performed by the mask supplier.[7] This places the responsibility for the calibration and maintenance of the correction models in the same organization as the processes being corrected, and avoids extending the required feedback loops over the bounda-ries (both organizational and geographic) between the mask user and supplier. In many cases, however, this represents a significant paradigm shift, since mask sup-pliers are often not allowed to modify the mask data supplied by the mask user to any significant degree.

Maskmakers also routinely use features of the mask patterning tools to correct for

process errors that depend on mask posi-tion or etch density and vary over a range of millimeters. Although the interaction of these corrections with MPC is not yet fully understood, it is possible that these routine corrections might require modifi-cations to MPC as well. This would further argue for performing MPC within the mask shop to expedite mask delivery.

The Need for Additional Mask Specs

Mask users typically specify the target size for certain critical dimensions (CDs), and demand a specified uniformity over the mask area. In addition, they typically characterize “mask CD linearity” by meas-uring an isolated line, an isolated space, and a dense grating with equal lines and spaces while varying the target feature size. The linearity is the CD variation as the feature size is varied over a range.

For EUV masks, we worried that den-sity variations in the circuit design might

Keith Standiford GLOBALFOUNDRIES

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Figure 1. (a) Electron scattering on an EUV mask at 50 keV simulated by CASINO.[3] The area shown is about 30 μm deep. The resist layer on top is not visible. (b) Absorbed energy in the resist layer vs. dis-tance from the exposure point simulated by PENELOPE[4] for conventional mask materials, and an EUV mask blank shows a large increase in backscattered electron dose for EUV masks out to the intermedi-ate range of a few microns. (c) The resulting rapid increase in mask CD error from the increased electron backscattering on EUV masks compared with OMOG material.



cause CD errors that were significant for device performance and were not adequately captured by these methodolo-gies. Identifying such cases is important for calibrating and evaluating MPC models and corrections. If these activities are per-formed in the mask shop, these cases must form the basis of the mask specification between user and supplier. We found one such case by examining wafer fabrication requirements for time-dependent dielectric breakdown (TDDB) of the metal layers at the back end of line (BEOL).

An Introduction to BEOL TDDBTDDB is deterioration over time of the

electrical properties of a dielectric exposed to excess electric field strength. For BEOL metal and via layers, it can result in seri-ous long-term reliability issues for circuits at the 45 nm node and beyond. Workers

such as Vilmay[8] have investigated the topography impacts (such as trapezoidal trenches and line-edge roughness) on reli-ability within a single metal layer. Others such as Liu[9] have extended this work to include the interactions between via and metal layers, including misalignment. The critical issue for all these cases is the mini-mum spacing between circuit elements (at least for reasonable errors).

For lithography, we need to control the CD uniformity (CDU) and line-edge rough-ness (LER) of the metal and via layers, and the overlay between the two as shown in Figure 2. We must ensure that these varia-tions do not reduce the minimum designed conductor spacing below the minimum required value for device reliability. The designed conductor spacing is set by the design rules and process characteristics, such as the trapezoidal conductor shapes.

A wafer lithography error budget might then be constructed that must satisfy the following equation.

Min_Space is the minimum designed conductor spacing, Min_Ins is the mini-mum allowed spacing for TDDB reliability (including process characteristics), and “n” is chosen to achieve the required device reliability. This budget must also include the impact of mask errors. Establishing such a budget is a complicated multi-disciplinary task and is well beyond the scope of this discussion. What we must note is that mask

linearity errors will be systematic based on the surrounding structure and not random. Linearity errors thus must be treated as

mean errors and cannot be lumped in with the CDU and LER sigma terms.

Critical Mask Structures for TDDB Performance

The search for critical mask struc-tures involves understanding of the wafer requirements, the technology design rules and the actions of OPC and design for manufacturing (DFM) software. This goes

Shifts for EUV Mask Users and Suppliers LITHOGRAPHY LANDSCAPE

Figure 2. Contributors to critical minimum TDDB spacing. In the top down view on the left of a single layer, line-edge roughness and CD errors for the drawn space influence the minimum spacing M1-M1 (Metal 1 to Metal 1). In a cross-section view on the right, the trapezoidal shapes and the layer misalign-ments are also significant contributors to the minimum spacing V1-M1 (Via 1 to Metal 1). The right-hand case is generally more difficult, since it includes the overlay between layers.

Figure 3. Mask CD error for the minimum drawn space through pitch. Data is shown at wafer scale. MEEF is not considered.


well beyond the scope of this paper, but will be discussed in a later publication.

By inspection of Figure 2 and Equation 1, we can argue that (for a given voltage) only the minimum allowed space between metal lines can have a TDDB issue. If the space is larger, then conductors have more separation and the TDDB constraints are more easily met. Note that since the metal is drawn, the critical space between them is the “drawn space.” We will refer to the feature this way as a space, even though it may vary in tone on the mask or wafer based on resists and processes.

Next we checked if the minimum space was allowed to occur through a wide range of pattern densities, where it would be influenced by proximity effects. We found at least one set of leading-edge finFET technology design rules that allowed metal lines of varying size to be drawn with the minimum space. We therefore decided to

examine the performance of the minimum metal space through pitch on EUV masks for the targeted technology node.

Minimum Space Through PitchWe measured the minimum space

through pitch as shown in Figure 3. Note that the data is presented at wafer scale, so the actual mask errors are 4x larger.

The chart also shows significant struc-ture through pitch. Since the two ends of the chart correspond to the dense grid and isolated drawn space values that are usually measured by maskmakers, this new linearity measurement is significant.

Mask Linearity Requirements for TDDB Performance

Lastly, we need to examine the linearity performance required for TDDB reliability and compare to experimental results to see if MPC is really required.


As mentioned previously, a detailed error budget derivation is outside the scope of this paper. Instead, we turn to an example given by Chen[10] to give us some guidance on how sensitive reli-ability might be to linearity errors. Chen gave a set of lithographic assumptions and a minimum insulator requirement for TDDB, and derived a potential chip failure rate as a function of overlay vari-ation. Although he did not publish the exact metal space values, we used the structure of Equation 1 and the given assumptions and discovered that a space of 28 nm gives results that are within half an order of magnitude of his published data. To estimate the linearity sensitivity, we evaluated the same function assum-ing that the metal spaces were printed 1 nm smaller on the wafer. The results are shown in Figure 4. The 1 nm CD error on the wafer results in nearly an order of magnitude increase in the expected fail-ure rate. We therefore expect that the linearity control target for the minimum space through pitch should be well under 1 nm at the wafer.

ConclusionsMask process corrections will be

needed on EUV masks because of the enhanced electron backscattering from the mask substrates. We believe that these MPCs should be implemented in the mask shop.

We found that the need for MPC will also drive a requirement for new mask specifications. We propose a new linearity requirement based on the minimum space through pitch in order to ensure TDDB reli-ability.

Introduction of data correction meth-ods like MPC into the mask shop and the creation of new types of mask specifica-

tions both represent paradigm shifts in the relationship between mask user and mask supplier.

AcknowledgementsThis paper is an abridged version of a

paper submitted to the SPIE Photomask Technology Symposium for 2013. Special thanks to Christian Buergel of AMTC for discussions and data, and Yuansheng Ma, Jongwook Kye and Tom Wallow of GLOBALFOUNDRIES for many valuable insights.

References1. H. Tanabe, T. Abe, Y. Inazuki and

N. Hayashi, “Short-Range Electron Backscattering From EUV masks,” Proc. SPIE 7748, 774823 (2010).

2. J. Choi, et al., “Degradation of Pattern Quality Due to Strong Electron Scattering in EUV Mask,” Proc. SPIE 7823, 78230D-1 (2010).

3. D. Drouin, et al., “CASINO V2.42—A Fast and Easy-to-Use Modeling Tool for Scanning Electron Microscopy and Microanalysis Users,” Scanning, Vol. 29, 92–101 (2007).

4. Fracesc Salvat, et al., “PENELOPE, a Code System for Monte Carlo Simulation of Electron and Photon Transport,” www.oecd-nea.org/global-search/download.php?doc=4418.

5. P. Schiavone, et al., “A Novel Mask Proximity Correction Software Combining Accuracy and Reduced Writing Time for the Manufacturing of Advanced Photomasks,” Proc. SPIE 8441, 84411F (2012).

6. T. Kamikubo, et al., “Mask Process Correction (MPC) Modeling and Its Application to EUV Mask for Electron Beam Mask Writer, EBM-7000,” Proc. SPIE 7823, 782331 (2010).

LITHOGRAPHY LANDSCAPE

Figure 4. Chip failure rate prediction based on Equation 1 with assumptions from Chen.[10] The overlay mean is assumed to be zero. A 1 nm CD error in the minimum space size on the wafer results in nearly an order of magnitude rise in the expected failure rate. LER terms are assumed to be already contained in the size control values.

BACK END OF LINEClick here to return to Table of Contents

The paper in this Back End of Line section addresses one of the most critical challenges our industry has ever faced. This is not an overstatement, but it is only recently that the severity of this challenge has been fully recognized.

Simply stated, the way we have designed and built computers will now fundamentally have to change. This includes applications from portable devices up to data centers and for almost every computing system platform in between.

The continued performance improve-ment of these systems that we’ve become accustomed to will come to an end unless fundamental new directions are taken. This continuing performance improvement is now being severely lim-ited by the energy budget within which each system must operate.

To address this critical challenge and limit the disruption of developing such a wide range of new products, new and

Jon CandelariaDirector, Interconnect and Packaging Sciences, SRC

substantial efforts are required, simulta-neously spanning basic materials research up through novel circuit and systems design.

While new transistor designs and novel circuit architectures have recently been developed to extend the capabilities of these systems, it is the physical and elec-trical limitations of scaled interconnects that have not yet received the attention required. This is despite the fact that for most of these systems, well over half of the energy being consumed is within these interconnects.

This paper describes the challenges at the interconnect materials and process-ing level and how they fit within the hier-archy of issues. It then briefly describes one of the possible solution paths being explored—the use of carbon-based mate-rials to replace copper in future circuits. As structurally simple as these materials appear, their characteristics at the dimen-sions required are not yet well-under-stood. How to apply and control them effectively is also not yet understood, so much work remains to be done.

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7. Christian Büergel, Keith Standiford and Gek S. Chua, “Choosing the Data Flow Paradigm for EUV Mask Process Corrections,” Proc. SPIE 8522, Photomask Technology 2012, 85220Y (Dec. 6, 2012).

8. M. Vilmay, D. Roy, C. Monget, F. Volpi and J.M. Chaix, “Copper Line Topology Impact on the SiOCH Low-k Reliability in Sub-45 nm Technology Node. From the Time-Dependent Dielectric Breakdown to the Product Lifetime,” Reliability Physics Symposium, 2009 IEEE International, 606-612 (2009).

9. W. Liu, et al., “Study of TDDB Reliability in Misaligned Via Chain Structures,” IRPS Paper 3A.4.1, Anaheim, Calif., 2012.

10. J.Y. Chen, “Transform Designs to Chips, an End User Point of View on Mask Making,” Proc. SPIE 8522, Photomask Technology 2012, 852202 (2012).

About the Author

Keith StandifordKeith Standiford is a principal mem-

ber of the technical staff in the Emerging Lithography and Tools Group, part of the Strategic Lithography Technology Department at GLOBALFOUNDRIES. He has more than 25 years of experience in e-beam lithography and metrology. Standiford previously worked at KLA-Tencor, and consulted for numerous organi-zations on next-generation lithography sys-tems. He began his career with the integra-tion of the first MEBES system at Etec.

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BACK END OF LINE BACK END OF LINE

A combination of innovative material and device-structure solutions overcame significant limitations to classical transistor scaling and performance improvement in terms of speed and energy dissipation at sub-100 nm technology nodes. This even-tually led to the revolutionary departure from the planar CMOS by using the verti-cal dimension to manufacture 3D transis-tors in the 22 nm technology node.[1]

Besides smaller and faster transistors, the semiconductor industry requires fast and dense interconnects to manufacture high-performance microchips. Interconnect performance, however, degrades with dimensional scaling. Interconnects impose major limits on IC performance because of the delay they add to critical paths, the energy they dissipate, the noise and jitter they induce, and their degrading reliability caused by vulnerability to electromigration and time-dependent dielectric breakdown (TDDB).

Historically, the delay of short local and intermediate-level interconnects has been much smaller than the delay of switches, and have scaled with technology. The delay of short interconnects has been determined by the output resistance of transistors and interconnect capacitance. The length of long global interconnects,

however, did not scale with technology scaling because they ran across the chip. The delay of repeated global intercon-nects remained constant, resulting in an increasing delay trend compared with gate delays. Therefore, global interconnects were thought to be the more serious inter-connect problem.

Considering that the intrinsic latency of an RC-limited interconnect is proportional to L2/HT, the interconnect delay can be reduced by: 1) reducing metal resistivity, , using new materials; 2) scaling insulator

permittivity, ; 3) reducing interconnect length, L, using novel architectures; and 4) reverse scaling interconnect height, H, and insulator thickness, T.

A variety of solutions have material-ized in the past decade to mitigate the global interconnect problem. Some of these include switching to the Cu/low-k technology to introduce a lower prod-uct, transitioning to many-core architec-tures and 3D integration to reduce the maximum global interconnect length, and reverse scaling. Another potential solution to the global interconnect scaling problem is changing the physical means of inter-connection by introducing on-chip optical interconnects.[2] Although some of these solutions have in turn introduced other

Interconnect Issues: History and Future Prospects, Part I

problems, such as router power dissipation in many-core architectures, it is undeniable that the nature of the global interconnect problem has changed as a result of these advances.

Besides, there is radical change in local-level interconnect behavior at sub-20 nm technology nodes. In addition to the reduction in cross-sectional interconnect dimensions due to dimensional scaling, the effective cross-sectional dimensions of copper interconnects are further reduced because of an increasing fraction of the trench being occupied by the barrier/liner/Cu seed tri-layer thickness. At such small dimensions, the resistivity of copper inter-connects significantly increases as a con-sequence of increased electron scatterings at the sidewalls and grain boundaries, and line edge roughness (LER).

Consequently, the resistance per unit length associated with copper intercon-nects increases rapidly such that the resistances of even the local-level inter-connects become significant. The delay of

local interconnects can no longer be deter-mined by just the output resistance of transistors and interconnect capacitance. It is known that both the local/intermediate and global interconnects are significant in the overall circuit delay.[3] Potential solu-tions, including the use of atomic-layer deposition (ALD) instead of sputter depo-sition for better control, and the use of self-forming barrier layers, might reduce the liner thickness and improve reliability, but the resistivity increase that is inherent to copper will eventually require a materi-al-based solution for mitigating the latency issues at the local/intermediate levels.

To compensate for the increasing inter-connect RC delay trend, one approach is to increase the aspect ratio to reduce the resistance per unit length, as plotted in the upper left of Figure 2 for minimum width interconnects at the 7 nm technology node in the year 2020. However, increasing the aspect ratio also increases the capacitance per unit length as plotted in upper right of the figure. As a consequence, there can be

Ahmet Ceyhan, Azad NaeemiGeorgia Institute of Technology

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Figure 1. RC delay (left) and EDP (right) of 10-gate-pitch long Cu/low-k interconnect with various size effect parameters compared with ITRS projections[4] and predictive technology models for finFETs at sub-20 nm technology nodes.[5]



an optimal aspect ratio for a given inter-connect length as shown in Figure 2. For short signal interconnects that are only 10-gate-pitch long, the aspect ratio that offers the smallest delay is as low as 1.5, whereas for 150-gate-pitch long intercon-nects, it can be around 2. Increasing the aspect ratio also results in higher intercon-nect power dissipation, which will be dis-cussed later.

Furthermore, as the interconnect dimensions scale and the density of interconnects increases, the aggregate interconnect length—and hence the total interconnect capacitance on a microchip—increases. As a consequence, interconnect dynamic power dissipation becomes a larger fraction of the total power dissipa-tion on a microchip at each technology generation.

An interconnect power analysis study performed on a microprocessor designed for power efficiency, consisting of 77 mil-lion transistors, fabricated in the 130 nm technology in 2004, revealed that inter-connects account for 50% of the total dynamic power dissipation.[6] This study also revealed that local- and global-level interconnects are equally important in terms of power dissipation, each account-ing for 25% of the total dynamic power of the chip.

To reduce the power dissipation in interconnects, progressively lower-k mate-rials have been introduced in many tech-nology generations.[1] However, low-k materials are more vulnerable to TDDB because of a high density of defect sites in the dielectric, damage or contamination of the dielectric from processes such as

CMP, copper diffusion into the dielectric through the barrier layer, and patterning problems such as LER or via misalign-ment.[7] Patterning problems become more pronounced as multiple-lithography techniques become a common method to extend the use of 193 nm lithography tools until EUV lithography is ready. This con-flicting requirement between power dis-sipation and reliability makes the intercon-nect problem even more complicated.

Such conflicting requirements extend to the system level as well. For instance, from the circuit design and reliability per-spective, the interconnect metrics such as resistance, capacitance, resistance to electromigration and TDDB are not equally important for all wires. The resistance of the majority of local signal interconnects in CMOS chips are dominated by drivers; hence the circuit delay is largely deter-mined by the product of the driver resist-ance and the interconnect capacitance. On the other hand, power and ground inter-connects must be low-resistance, and their current density must be kept under control to increase their electromigration-limited lifetime.

Signal wires conduct bidirectional cur-rents and are less vulnerable to electro-migration. The fact that signal and power interconnects need to be routed in the same metal levels means that they must be co-designed together based on con-flicting requirements. For instance, the typical aspect ratio of short local inter-connects is generally higher than 2, even though the lowest delay is achieved by a considerably smaller aspect ratio, as shown in Figure 2.

To provide the possibility to route fine-pitch interconnects for high density at some metal levels, and wider and thicker interconnects for improved delay at oth-ers, the number of metal layers has gradu-ally increased over the years.[1] It has been shown that the number of metal levels will have to be increased significantly if size effects are not mitigated and scaling the barrier thickness continues to be a chal-lenge.[8]

We have established above that the Cu/low-k interconnect technology faces various challenges and we need innovative solutions right now. Many of the solutions that are mentioned in this paper mitigate

Interconnect Issues: History and Future Prospects, Part I BACK END OF LINE

1 2 3 4 50

500

1000

Aspect Ratio

r (

/μm

)

1 2 3 4 50.1

0.2

0.3

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c (f

F/μ

m)

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50

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rc (

fs/μ

m2 )

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ay (

ps)

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ay (

ps)

Figure 2. Per unit length resistance (r) and capacitance (c), rc product, and total line delay assuming a 10-gate-pitch long interconnect (solid line) and a 150-gate-pitch long (dashed line) interconnect, respec-tively, are plotted vs. aspect ratio at the 7 nm technology node for the year 2020.

Figure 3. Comparison of the RC product per unit length squared and EDP per unit length cubed associated with copper interconnects, SWNT bundles, SWNT interconnects considering various number and diameter of tubes in a single layer, and mono- and multi-layer GNR interconnects with perfect and rough (20% edge scattering probability, p=0.2) edges.


the interconnect problem at the global level. The only known solutions that would work for the local level are material-based, and there are rising opportunities for carbon-based emerging interconnect tech-nologies as dimensional scaling continues.

Carbon nanotubes (CNTs) have long been considered a promising alterna-tive for future nanoscale interconnects because of their long mean free path (MFP), high current carrying capability and high thermal conductivity. As the RC delay associated with Cu/low-k interconnect technology degrades, various CNT-based interconnect designs hold potential as nanoscale interconnects. Graphene nanor-ibbons (GNRs) can be considered unrolled CNTs. High-quality graphene sheets can have MFPs close to those in CNTs. GNRs can also conduct current in the same order of magnitude as CNTs.

One major issue about the conductiv-ity of GNRs is their rough edges. The MFP associated with diffusive scatterings at the edges of a GNR is a function of the edge roughness. For chemically obtained GNRs with relatively smooth edges, an electron backscattering probability of 0.2 has been measured.[9] For patterned GNRs, this probability is typically around 1. Even when a moderate value of 20% of electrons are assumed to scatter backwards at the edges, the resistance per unit length asso-ciated with GNR interconnects increases significantly. This increase becomes more pronounced at smaller GNR widths because electrons interact with the edges more frequently.

The intrinsic properties of various carbon-based interconnects are compared with that of Cu/low-k in Figure 3. Many carbon-based designs offer comparable or better performance than Cu/low-k in terms of both RC delay and energy-delay prod-

uct (EDP) beyond the year 2020. Despite major technological progress in fabricating such interconnects, there are many major challenges that must be overcome before they can become commercially viable options.

References1. M. Bohr, “The New Era of Scaling in an

SoC World,” ISSCC, 2009.2. D. Miller, “Rationale and Challenges

for Optical Interconnects to Electronic Chips,” Proc. IEEE, Vol. 88, No. 6, 2000, p. 728.

3. N.S. Nagaraj et al., “Impact of Interconnect Technology Scaling on SoC Design Methodologies,” IEEE IITC, 2005.

4. International Technology Roadmap for Semiconductors (ITRS), 2012, www.itrs.net.

5. Predictive Technology Models, Nanoscale Integration and Modeling Group, Arizona State University, ptm.asu.edu.

6. N. Magen et al., “Interconnect Power Dissipation in a Microprocessor,” Proc. Intl. Workshop on System Level Interconnect Prediction, 2004.

7. J.P. Gambino et al., “Reliability Challenges for Advanced Copper Interconnects: Electromigration and Time-Dependent Dielectric Breakdown (TDDB),” IEEE IPFA, 2009.

8. A. Ceyhan and A. Naeemi, “Multilevel Interconnect Networks for the End of the Roadmap: Conventional Cu/Low-k and Emerging Carbon Based Interconnects,” IEEE IITC, 2011.

9. X. Wang et al., “Room-Temperature All-Semiconducting Sub-10-nm Graphene Nanoribbon Field-Effect Transistors,” Phys. Rev. Lett., Vol. 100, No. 20, p. 206 803-1, May 2008.

Interconnect Issues: History and Future Prospects, Part I

About the Authors

Ahmet CeyhanAhmet Ceyhan was born in Ankara,

Turkey. He received an M.S. degree in electrical and computer engineering from Rutgers University in 2009. He is current-ly working toward a Ph.D. at the Georgia Institute of Technology.

Azad NaeemiAzad Naeemi received M.S. and Ph.D.

degrees in electrical and computer engi-neering from the Georgia Institute of Technology in 2001 and 2003, respec-tively. He has been an assistant professor with Georgia Tech since 2008. Click here to return to Table of Contents

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This issue’s MIFA section deals with two main topics: A general overview of technical requirements for a future viable metrology (either for 450 mm or to cope with challenges imposed by a 1X nm tech-nology node) is paired with a specific case study of a typical, day-to-day defec-tivity problem.

I always appreciate papers dealing with next-generation node require-ments because they give a perspective to our daily activities and help us figure out what is stewing for us in the future. Cottle et al., in their activity at G450C, scrutinize reasons why today metrology is not fully suitable to guarantee 450 mm development (essentially, throughput and capability, i.e. P/T issues), and pro-pose possible scenarios to improve it to enable 450 mm and/or 1X nm node pro-cess development and manufacturability.

For her part, Harris-Jones brings to our attention the SEMATECH Nanodefect

Center view on challenges that need to be addressed to enable scaling below 20 nm. Her approach is somewhat new and more interdisciplinary, focusing on the non-process-related defect genera-tion mechanisms, claiming a real break-through in defect reduction will come when components behavior (valves, vacuum systems, etc.) undergo a deep analysis and a thorough R&D activity to improve their behavior (I am willing to bet, though, something similar nagged at back of our brains the moment some new tool qualification did not go smoothly).

Last, but equally important (I am told our salaries are paid out of such trivial activities), Tuohy suggests a methodol-ogy to quantify chuck spot-related yield loss, and a way to evaluate benefits weighted against costs of wafer backside cleaning strategies, based on stage dis-tortion mapping capabilities in scanners.

Enjoy reading!

Davide LodiBaseline Defectivity & Metrology Engineering Manager, Micron Semiconductors Italy

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Development of next-generation IC wafer metrology must simultaneously address two major challenges. The first—independent of wafer size and dictated by Moore’s Law—is providing measurement and detection capabilities for continuously decreasing critical dimensions (Figure 1). Detection and measurement of smaller dimensions on increasing topographical complexity drives the need for higher reso-lution and lower signal-to-noise (S/N) ratio.

The second major challenge is dictated by the economics of larger wafer size. Returning the investment in a 450 mm fab is associated with a die output rate proportional to the increase in wafer area (nominally 2.25x higher). To avoid either increasing the number of metrology tools (for a given die output rate) or reducing metrology-based measurements, 450 mm metrology tools must achieve wafer-per-hour throughput times (TPTs) equal or better than their 300 mm wafer prede-cessors. Bigger and heavier stages must move faster and accelerate/decelerate very quickly from one measurement point to another without detriment to measure-ment (stability, accuracy, etc.) or cleanli-ness. It also means faster acquisition and

real-time analysis of huge amounts of data from a larger surface or number of die.

Metrology Must LeadUnit process development can’t pro-

gress without reliable metrology. The first step in establishing an early test wafer (ETW) pilot line is to acquire and characterize metrology capabilities for bare wafer particle inspection, film thick-ness and stress, defect inspection and review, CD, overlay, wafer geometry, and nanotopography. Having these capabili-ties in place as early as possible enables rapid learning at the leading edge of technology progression. Enabling metrol-ogy is consequently a major focus for the Albany, N.Y.-based Global 450mm Consortium (G450C), and many of the first tools in the G450C demo line are metrology tools.

Challenges of Early MetrologyThe most commonly used metric for

determining if a metrology tool is meet-ing performance requirements is to gauge it in terms of the ratio of tool measure-ment precision to process tolerance (P/T). Historically, P/T 0.1 is the goal; i.e., metrol-

The Enabling Role of Metrology in the 450 mm TransitionRand Cottle,1 David Nessim,2 Frank Robertson,1 Menachem Shoval3 1G450C 2Intel 3Metro450

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ogy uncertainty is consuming no more than 10% of the process tolerance for variation. As dimensions continue to shrink to 14 nm and below, it’s getting increasingly difficult to achieve a P/T of 0.1. In the case of 1X nm node technology combined with 450 mm wafers, process tolerances are to a large extent uncertain at this point.

Early metrology tools are typically best-in-class 300 mm tools scaled up to handle 450 mm wafers. While actively in development, 450 mm calibration/quali-fication wafers are not yet available for most early development needs. 300 mm wafers are being used for initial testing. Potential differences between 300 and 450 mm wafers and film stacks add to the

measurement uncertainty. An early prior-ity for the G450C metrology team will be getting reference standards fabricated on 450 mm wafers.

The initial G450C capability will con-sist of a distributed toolset with some process and metrology tools at supplier or other sites. Reference artifacts are required to correlate tools from around the globe. Traceability from organizations like the National Institute of Standards and Technology (NIST) would also be highly desirable to make sure we’re not just on the same page, but on the right page.

450 mm metrology tools, being the first to arrive, are the first to face and solve wafer handling issues to pave the way

450 mm Technology and 1x nm Technology to Meet in 2018

110 nm90 nm

65 nm45 nm

32 nm22 nm

14 nm450 mm

300 mm

200 mm

1990 2001 2018

150 mm

Figure 1. Providing measurement and detection capabilities for continuously decreasing CDs is key to next-gen wafer metrology.

The Enabling Role of Metrology in the 450 mm Transition METROLOGY, INSPECTION & FAILURE ANALYSIS

for subsequent tools (Figure 2). Scaled-up versions of mature 300 mm platforms must be debugged as carriers, person-guided vehicles (PGVs), load ports, equip-ment front-end modules (EFEMs) and end effectors are integrated with them. G450C and suppliers are working diligently to resolve issues and optimize tools during development as essential early steps in the complex journey to production-worthy 450 mm metrology.

Israeli Metro450 ConsortiumGiven the challenge of 450 mm develop-

ment, some key observations can be made:1. Achieving acceptable metrology TPT is

pivotal to enable 450 mm high-volume

manufacturing (HVM) economies of scale. This is a key goal of the Metro450 consortium.

2. Early 450 mm enabling programs are focused on establishing and debugging initial 450 mm metrology handling capa-bilities to enable process development and proof of capability, but are for now less concerned with metrology high-volume IC manufacturability.

3. No single design element solves the complex equation for 450 mm metrol-ogy tool production-worthiness. Rather, it is the combination of and synergy between several key mechanical and operational aspects that pave the way to the required performance.

Figure 2. 450 mm metrology tools are the first to face and hopefully solve wafer handling problems.


4. A concerted, collaborative effort between stakeholders will drive the innovation and breakthrough solutions to support 450 mm HVM with produc-tion-worthy metrology platforms.

5. Waiting on the sidelines for the 450 mm bandwagon to go by is not an option for metrology OEMs wishing to maintain/enhance their market position.

Stepping up to these challenges, four Israeli metrology equipment manufactur-ers are collaborating with four local uni-versities and a major global IC manufac-turer. Backed by the Israeli Office of Chief Scientist (OCS), they have established the Israel 450 mm Metrology Consortium

(Metro450) and defined the following five themes as the key focus of its 3+ year program:1. Metro450 and G450C will work together

to enhance 14 nm and beyond metrol-ogy tool performance specs.

2. CNSE/G450C capabilities will be used to produce prototype “standard calibration wafers.”

3. G450C metrology module performance data (availability, defects, maintainabil-ity, costs) will be shared with Metro450 as input to annual work plan validation and optimization.

4. G450C wafer damage information will be shared with Metro450, and Metro450 will share diagnostics and RCA with

The Enabling Role of Metrology in the 450 mm Transition METROLOGY, INSPECTION & FAILURE ANALYSIS

Figure 3. Metro450 and G450C have established a collaboration scheme centered on several key activities.

G450C, including use of metrology to predict/prevent.

Additional collaborations on 450 mm metrology-centric projects exist among G450C, Metro450 and organizations partici-pating in European 450 mm programs. An example is global harmonization of on-wafer and ambient micro-contamination objectives and means to measure not only particles but molecular contamination in 450 mm tools, carriers and fabrication facilities.

ConclusionsThere is a huge opportunity to accel-

erate 450 mm development with timely availability of measurement capability meeting medium-term equipment demon-stration performance objectives. This early enablement must be complemented with longer-term focus on manufacturability and evolving technology needs. G450C, Metro450 and other global organizations will collaborate to achieve these goals in as cost-effective manner as possible as the industry transitions to 450 mm wafers.

About the Authors

Rand CottleRand Cottle is a College of Nanoscale

Science and Engineering (CNSE) assignee to the Global 450mm Consortium (G450C) as manager of metrology. He received his Ph.D. in materials science and engineering in 2000 from the University of Texas at Austin, and has 12 years of R&D experience in the semiconductor industry in the fields of metrology, integrations and lithography.

David NessimDavid Nessim is a senior program man-

ager with Intel’s Technology Manufacturing

Engineering group (TME-EMEA). For the past 18 years, he has held engineering, operations, construction, manufactur-ing and program management positions across Intel fabs in Israel, the United States and Ireland. He is currently engaged with various industrial, government and aca-demic programs focused on emerging technologies. He represents Intel in the Israel 450mm Metro Consortium since it was established in early 2012.

Frank RobertsonFrank Robertson is vice president and

general manager, industry interface and program strategy at the Global 450mm Consortium (G450C). He began work on the 450 mm transition in 2005 while man-aging external programs for Intel, assum-ing his current position as an assignee at the founding of G450C in 2012. Prior to joining Intel in 2000, Robertson had been chief operating officer of International SEMATECH and general manager of I300I after spending 20 years in fabs, develop-ment work and program management.

Menachem ShovalMenachem Shoval has an electronic

engineering degree specializing in industrial control systems. After 10 years at various organizations in Israel, he joined Intel to start the first fab in Israel in 1984, and spent the past 28 years in various engineering, technological and managerial positions with the company. With the initiation of the Metro450 Consortium in Israel, Shoval left Intel to take leadership of the consortium’s board.


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METROLOGY, INSPECTION & FAILURE ANALYSIS METROLOGY, INSPECTION & FAILURE ANALYSIS

As the environment in the semicon-ductor industry scales to nodes below 20 nm, strict requirements are being put on equipment and material suppliers to address defectivity challenges. Next-generation lithography techniques, new materials and processes for sub-20 nm node manufacturing, and the progression toward 450 mm wafer integration are among the candidates that are affected by these requirements.

The infrastructure needed to provide solutions to these roadblocks is faced with huge investment gaps in exponen-tially increasing R&D costs, which in turn put enormous amounts of pressure on the component-level supply chain. The supply chain must continuously adapt to these changing technology requirements and cope with slow implementation by the OEMs, which results in only a gradual recovery of expensive engineering costs.

As defect reduction requirements become more stringent, interdiscipli-nary knowledge is needed to understand defect generation processes. Using this knowledge, mitigation strategies can be devised and implemented to meet tech-nology roadmap constraints. Cycles of learning to understand and characterize

small defects generally take longer, result-ing in more costly efforts and increased development times for component and material suppliers, which ultimately affects yield ramping. Further, these delays have detrimental impacts to the IDMs by raising the costs of the manufac-tured chip and by reducing the manufac-turers’ competitive advantage if delivera-bles are not met in a timely fashion.

To address the growing defectivity challenges in the semiconductor industry, SEMATECH has created the Nanodefect Center (NDC) as a means to collaborate with different sectors of the industry, work proactively to address defectiv-ity before it becomes a showstopper, and drive forward industry solutions. Through collaboration, the NDC is able to identify key defectivity problems in the industry supply chain, perform R&D in shared facilities to cut down on costs, and facilitate discussions that are essen-tial for lateral and vertical integration. The NDC together with SEMATECH’s member companies will work proactively by creat-ing roadmaps and developing defectivity performance metrics for critical equip-ment components. The result is a shorter cycle of learning, and the solutions to

Addressing Nanodefectivity Challenges

component-level defect challenges can then be marketed to and implemented by fabs faster than the conventional way of working.

Problem ParticlesSEMATECH has accelerated the iden-

tification of key areas where particle per-formance significantly affects the yield learning in both current and future manu-facturing. Identification of the problem areas was achieved by conducting multiple workshops with more than 70 companies that included major IDMs, foundries, OEMs, and component and material suppliers.

The major areas highlighted as prob-lematic were centered on application-spe-cific valves and seals, defects introduced by vacuum systems, inadequate gas and liquid filtration, molecular contamination, cleaning and packaging of components, and electrostatic chucking issues. These workshops also revealed unsatisfactory progress in fundamental research focus-ing on defect generation and transport in conjunction with the severe lack of infra-structure to evaluate particle performance of components.

In response to this critical feed-back, the NDC held its first workshop in November 2012, titled “Current and Future Defectivity Issues From Components in the Semiconductor Industry,” which focused on defectivity concerns and gaps facing vacuum valve and seal suppliers.

SEMATECH has taken a fast-track approach to assist the supply chain by providing unique infrastructure with test stands and exclusive failure analysis capa-bilities, as well as standardized and inde-pendent testing, supplier benchmarking and roadmap development through the new NDC. This is all possible thanks to

more than a decade of expertise and infra-structure development at SEMATECH that was designed to meet major challenges faced by the supply chain such as reliable particle detection, defect characterization and particle mitigation.

The NDC is in the early stages of addressing some of the key problems confronting supply chain enablement. Among these projects are concentra-tion on component design issues and defectivity performance in vacuum and plasma systems, source identification of molecular contamination and mitigation schemes, and filtration challenges in wet applications including DI water and resist materials. Because of the strategic vision at SEMATECH, several other companies have been in contact with the NDC to dis-cuss the potential of joint work in other key areas involving defect reduction and development activities.

Coming up at SEMICON West 2013, SEMATECH and the NDC are planning talks and workshops to continue the dis-cussion between IDMs, OEMs and the sup-ply chain. SEMATECH CEO Dan Armbrust will participate in a SEMI executive forum on the semiconductor industry’s R&D mod-els, which will be followed by a TechXPOT session on “Nanodefects: An Emerging Challenge,” which will include a talk on the NDC.

A workshop held jointly with SEMI and SEMATECH will investigate trends in sup-ply chain R&D and explore collaborative models that will enable cost-effective inno-vation, and it will be chaired by Michael Lercel, senior director of the NDC. To close out the week, a focused, open workshop hosted by the NDC will emphasize defec-tivity issues and infrastructure gaps in liq-uid systems and liquid filtration.

Jenah Harris-Jones SEMATECH

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The NDC is prepared to concentrate its efforts on the impending defectivity chal-lenges as a means to enable the semicon-ductor supply chain. Current and future industry requirements are putting increas-ing pressure on the semiconductor supply chain to innovate and provide new prod-ucts, meet increasingly stringent develop-ment schedules, and reduce the time-to-market for new device modes.

Defect reduction is intensifying for many applications, including the emer-gence of EUV lithography and the 450 mm wafer platform shift, which is generating tremendous challenges for the OEMs to control particle performance of each com-ponent. Not only are the component sup-pliers held accountable to address these OEM performance specifications, but they must also continuously make improve-ments to their components to keep pace with the changing process latitudes of the end users. It is the goal of the NDC to close these gaps and participate in the enablement of the supply chain.

About the Author

Jenah Harris-JonesJenah Harris-Jones is a project manager

in the Nanodefect Center at SEMATECH, where she focuses primarily on defect char-acterization. She was awarded her master of science in nanoscale science from the University at Albany, State University of New York, where she studied electron-solid interactions and spectral processing, devel-oped a novel technique to precisely meas-ure the probe shape and size in a scanning electron-beam system, and demonstrated the methodology for the extraction of the momentum-dependent loss function through electron energy loss spectros-

copy. Harris-Jones received her bachelor of science in physics from the University of Northern Iowa, where she worked on dilute magnetic semiconductors.


Addressing Nanodefectivity Challenges

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The constant pressure to maximize yield as wafer processing costs and con-straints on depth-of-focus increase has directed ever more attention toward back-side wafer cleanliness and its subsequent effect on focus spot generation. To per-form an adequate cost-benefit analysis for potential backside cleaning methods, we must determine the cost in terms of yield. We present a method for quantifying the yield impact of focus spots resulting from backside contamination.

The ChallengeUsing the stage distortion map data

from the scanners/steppers is a novel means of monitoring backside wafer clean-liness and has the added advantage of filtering out the least significant defects (nuisance, roughness). For the purpose of process control and monitoring, it is suf-ficient to track the number and height of focus spots.

Figure 1 shows a stack map of focus spots detected at a specific mask opera-tion for more than 33,000 wafers. The variation in spot height is illustrated by the size of the circles.

It is also possible to convert these data to an equivalent defect map and perform a contingency analysis. However, this does not address a focus spots ability to

impact multiple adjacent die. This leads to the obvious questions: Which focus spots are yield-relevant; and what is their yield impact?

Quantifying the Focus Spot LossThe method used to determine the area

of influence of a given focus spot is to calculate the vectors from the focus spot to the corners of its resident die and to construct the perpendicular bisector that intersects at the focus spot. Ordering the

Quantifying Focus Spot-Related Yield LossGarry Tuohy GLOBALFOUNDRIES Inc.

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Figure 1. A focus spot stack map from more than 33,000 wafers at a specific mask operation, with circle sizes representing the measured spot height.




vectors according to their length identi-fied the sequence of nearest-neighbor-die. Sorting through this sequence of die until a non-power-related failing die (n) is encountered identifies the maximum possible radius for the focus spot and the number of die affected (n-1). The length of the previous vector can be considered as a minimum possible radius for the focus spot (Figure 2).

There is a small risk of obtaining a “hit” to a die with an unrelated power fail-ure when none actually exists. This risk increases with larger die size, but is negli-gible for volume production yield levels.

To achieve optimal overlay, we employ an ovular search pattern linked to the die size to compensate for possible non-circularity of the defective regions. This does introduce a slight risk of erroneously including additional die and artificially increasing the loss estimate. This can be ignored for all but the most extreme out-lier wafers.

Assessing the size and yield impact of focus spots is less accurate for edge die because of the lack of neighboring die. Off-die-grid focus spots should be aggre-gated separately because of the limitations of this method.

Figure 3 shows an example of a severe case where multiple die were affected, along with a subsequent defect inspection, which revealed the same pattern.

Figure 2. Example of focus spot and vectors to nearest-neighbor-die

Figure 3. Example of wafer backside defectivity resulting in (a) 14 failing die and (b) the front side defect map from a subsequent defect inspection.

Quantifying Focus Spot-Related Yield Loss METROLOGY, INSPECTION & FAILURE ANALYSIS

Once these loss estimates exist on a wafer-mask level, it is straightforward to aggregate these data to produce charts or stacked wafer maps for reporting pur-poses, to analyze the impact of experi-ments, or to monitor the result of process changes in terms of yield.

Focus Spot Loss PredictionWe examined the possibility to predict

die loss from focus spot height. It was clear that higher focus spots are more likely to kill more die. However, the consid-erable overlap between the height distri-butions for each die loss value makes dis-

crete prediction problematic. Considering the proximity of the focus spot to neigh-boring die would doubtlessly improve the selectivity.

Investigating the relationship between the focus spot estimated impact radius and height does indicate the existence of a linear relationship for some FEOL mask operations with the tightest exposure win-dows (Figure 4). The vertical scatter is a function of the die size. Unfortunately, this relationship was not universally observed, making loss prediction as a function of height only of value to the early FEOL mask operations.

Figure 4. Estimated focus spot impact radius vs. measured focus spot height for an FEOL mask operation.


ConclusionThis article presented a method for

determining the yield impact of focus spots resulting from wafer backside defec-tivity, as measured by a scanner’s stage distortion mapping capability. This is not intended as a replacement for wafer backside inspection, but the existence of these data for every wafer-mask operation makes their use compelling, in particular, in relation to quantifying the effectiveness of wafer backside cleaning initiatives.

Attempts at predicting die loss from the measured height of the focus spot was determined to be only practical for the early FEOL mask operations.

AcknowledgementsI would like to acknowledge Christian

Hobert for identifying the existence of these data and initially suggesting their use.

References• C. Saravanan et al., “Investigating the

Impact of Backside Defect Inspection on Process Development and Yields,” Micro Magazine, April 2004.

• L. Cheema et al., ”Yield Enhancement From Wafer Backside Inspection,” Solid State Technology, September 2003, p. 57-60.

• A. Carlson and T. Le, 31st International Symposium on Microlithography, February 2006.

About the Author

Garry Tuohy Garry Tuohy received a B.Sc. in applied

physics from the University of Salford, Greater Manchester, UK, in 1994. He has worked in the semiconductor industry

since 1996, mostly in the UK and Germany. Since 2003, he has been working in yield engineering in Dresden, Germany, for AMD and now GLOBALFOUNDRIES, where he is a member of technical staff. His work primarily involves developing systems for kill ratio and defect loss analysis, and web-reporting.


Quantifying Focus Spot-Related Yield Loss

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Invent. Innovate. Implement. These words summarize EV Group’s mission—to be the first to explore new micro- and nano-fabrication technologies that enable our customers to successfully com-mercialize new product ideas. Nowhere is this realized more than in advanced packaging, where reducing cost and foot-print, lowering power consumption and increasing IC performance requires high-precision alignment and wafer bonding systems, as well as process and applica-tions expertise.

Mask Alignment SystemsSince introducing the world’s first

double-sided mask aligners with bottom side microscopes in 1985, EVG has set the industry standards in lithography and aligned wafer bonding. Accommodating wafers and substrates up to 300 mm, varying in size, shape and thickness, EVG’s automated mask aligners are ideally suit-ed for advanced packaging, where they are optimized for the highest throughput and unmatched alignment accuracy.

Wafer Bonding SystemsWafer-level packaging techniques use

permanent and temporary wafer bonding

as an enabling solution for stacking wafers and 3D integration of devices. EVG offers flexible wafer bonders with a unique, modular bond chamber design to support the widest portfolio of wafer bonding pro-cesses. EVG’s wafer bonders are scalable from R&D to high-volume manufacturing, ensuring the advancement of new pack-aging techniques.

Wafer-Level Alignment SystemsWafer stacking is a viable solution for

reducing die size for new IC packaging applications. EVG’s SmartView aligner offers a proprietary method for micron-level, face-to-face, wafer-level align-ment—achieving the industry’s highest alignment accuracy to enable multiple-wafer stacking for leading-edge applica-tions. SmartView technology, combined with EVG’s Gemini automated production wafer bonding systems, allows stacking of wafers through face-to-face alignment and subsequent permanent bonding to form electrical or optical interconnects between wafers.

For more information, visit www.evgroup.com/en/markets/3dic_advanced_packaging

Industry-Leading Wafer Processing Solutions for Advanced Packaging

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WAFER FAB & PACKAGING INTEGRATIONClick here to return to Table of Contents

The common ground of interposer and 3D integration technology—hand in hand to face production concerns?

First of all, I must admit that I don´t like the naming “2.5D” for interposer technology; for a physicist, 2.5D is an outrageous term. On the other hand, as a technologist, I surely see advantages of interposers against “real” 3D integration: less complex design flow and testing, better thermal management—and poten-tially lower cost.

But be aware: 2.5D fabrication is not uncomplicated and not cheap. Although now entering application in low-volume and/or niche products, there are still big concerns in the industry for high-volume production, particularly regarding sup-ply chain, cost readiness and reliability. Just as for 3D integration technology, the state-of-the-art interposer processes must deal with serious problems such as those related to thinning, handling and processing of thin silicon. Consequently, not only the IDMs but also foundries are looking to outsource these risky pro-cesses like handing over a hot potato… in some sense being analogous to fabless companies (as let’s say “3D-less”).

In Europe, there is a large-scale project e-BRAINS (www.e-brains.org) focused on optimizing 3D TSV technolo-

Peter RammHead of Device and 3D Integration Department, Fraunhofer EMFT Munich

gies for heterogeneous sensor integra-tion. There, Siemens, in cooperation with Fraunhofer EMFT Munich, is also developing a high-performance inter-poser technology, but for thick—and thus stable—interposers. The applied TSV technology is based on photo-assisted etching, and can reach TSV diameters as small as ~2 μm through silicon wafers with standard thickness, realizing stable interposers with a low pitch.

I am confident that 3D integration will not come significantly later to produc-tion than interposer technology; inter-poser and 3D technology will go hand in hand, being chosen each time depend-ing on the cost and the specifications for a distinctive product and market, according to Cristina Torregiani from Qualcomm.

In this issue there is a dedicated inter-poser paper from Surya Bhattacharya et al. from A*STAR’s Institute of Microelectronics, and an excellent article on 3D scaling from Sitaram Arkalgud, formerly director at SEMATECH and now vice president of Invensas. I’m proud to say that as a first appearance in his new position, Arkalgud has accepted my invitation to be keynote speaker at this year’s IMAPS DPC conference in Scottsdale, Ariz.

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WAFER FAB & PACKAGING INTEGRATION WAFER FAB & PACKAGING INTEGRATION

As 3D IC technology paves the way for future VLSI systems, it is also confronting bottlenecks such as tools for designing optimal 3D systems and thermal solutions for 3D ICs. Meanwhile, 2.5D through-silicon interposer (TSI) technology is also gaining momentum, both in the foundry and the outsourced semiconductor assembly and test (OSAT) universe.

A typical TSI is designed to host a set of guest dies interconnected to each other using the back end of line (BEOL) intercon-nects, while the through-silicon vias (TSVs) are leveraged to interface with the external I/O ports on the organic package and/or PCB. Backside RDL technology routing has a potential to track a likely good die (LGD) through testing. TSI technology not only provides easier fabrication capabilities, alle-viating 3D thermal bottlenecks, it also sup-ports the fabrication of high-performance heterogeneous integration.[1,2]

A classical processor and memory inte-gration is an ideal system candidate for TSI application where the guest dies can be heterogeneous (e.g., logic and memo-ry) and can potentially belong to disparate

technology nodes (e.g., 28 nm for logic[3] and 40 nm for memory, or 130 nm for BiCMOS chips).

This paper demonstrates the fabrica-tion and characterization of a large size TSI (2.67x4.3 cm2) in a 300 mm processing line, and targeted for heterogeneous integration.

Versatile 2.5D Heterogeneous Logic + Memory System Design

Figure 1 shows a versatile 2.5D hetero-geneous logic + memory system design.[4] Ideally, the system should house a logic block integrated with high-speed memories supporting high-speed optical interface with the external world. Initial test vehicle simulation shows that on-chip interconnects provide more than 30x more bandwidth per watt compared with organic carrier. Moreover, the TSI reticle is large (2.67 x 4.3 cm2), and appears to be an ideal candidate for heterogeneous integration of the digital system. The large area of the TSI reticle is also instrumental in reducing the power density (W/cm2) constraint typically evident in real 3D stacked ICs.

Through-Silicon Interposer Technology for Heterogeneous Integration

on-chip data exchange. Bandwidth is transferred off-chip with single-mode fiber (SMF) optics at 1,550 nm optical wave-length, and optical bandwidth of 0.5 nm can carry 25 Gbps of data. For an SMF wavelength grid operating at 1,500–1,600 nm, it provides 5 Tbps per fiber or 10 Tbps in duplex mode.

Fabrication of TSI InterposerA 300 mm Si-(100) substrate was used

for TSI fabrication. The TSV was etched by a Bosch process after TSV lithography. Alternate deposition and etching achieved a 12 μm TSV with 100 μm depth. A 1 μm O3 TEOS with 1 kÅ PECVD SiO2 (field area)

H.Y. Li, L. Ding, G. Katti, J.R. Cubillo, Surya Bhattacharya, G.Q. Lo Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research)

A future test vehicle, so-called “node” in the high-performance computing world, will be a complete system with an optical interface for the off-chip signaling. With such “nodes,” all on-chip data transfer is electrical with copper wires, while off-chip data transfer uses optical fiber intercon-nects to guarantee bandwidth and low-power operations. With such architecture, the main function of the TSVs is to provide power and ground (through a large array of TSV and BEOL power/grids) and a few IO for the upper organic interconnect level such as a motherboard.

Such nodes or systems on TSI can operate in the Tbps regime (8xTbps) for

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TSI Vehicle Enables the Next Step Logic/Memory/Op�cs Integra�on on TSI

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Figure 1. Schematic of a versatile 2.5D Heterogeneous Logic + Memory System Design.



was deposited after via patterning a TSV liner to isolate the TSV from the silicon substrate. Titanium and copper were sput-tered on the TSV wafer as a barrier metal and copper seed. Copper void-free TSV was achieved by electroplating, and cop-per overburden was removed by a copper CMP process after copper annealing.

Three single-damascene processes were applied to form frontside (FS) M1, via and M2 on top of the TSV. The cross-section of TSV and FS metal is shown in the Figure 2 inset. Good connections are observed between TSV with M1 and M1-via-M2.

ZoneBOND technology[5] was used for wafer temporary bonding and de-bonding. TSV wafer was back-grinded near TSV depth before TSV exposed by the back-grinder. The remaining silicon substrate was etched to expose the TSV from the wafer backside (BS). Low-temperature dielectric films were deposited and a CMP process was applied for the planarization of BS dielectric films and TSV. BS barrier metal and copper seed were sputtered on the BS dielectric and TSV. BS RDL was patterned on barrier metal and copper seed. BS elec-troplating was used for the formation of BS RDL, and C4 bumps were built on top of the

RDL. The final cross-section of interconnect is shown in Figure 2 after BS photoresist strip and barrier layer and copper seed etch back. Full connection between TSV, BS RDL and FS metals is shown in the Figure 2 inset.

TSI Electrical CharacterizationThe electrical performance of the TSI

was characterized by an Agilent B1500A semiconductor device analyzer. C-V and

I-V curves were characterized for TSV capacitance (CTSV) and leakage current after top M2 metallization and before TSV revealing, treating measurement chuck as ground contact. The probability plots of the characterized TSV capacitance and leakage current are shown in Figure 3.

CTSV characterization was performed at 10 kHz, 100 kHz and 1 MHz frequency to observe the CTSV variation in the low-

Through-Silicon Interposer Technology for Heterogeneous Integration WAFER FAB & PACKAGING INTEGRATION

Figure 2. The cross-section of TSI after the BS bump process. The cross-section of TSV chain is shown in the inset.

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and mid-frequency range. The results are shown in the inset of Figure 3a. The accu-mulation and depletion capacitance of single TSV is ~300 and 180 fF respectively for a 12 μm TSV with 100 μm depth, and is in sync with the estimated average oxide liner thickness of ~420 nm.

CTSV response with applied voltage at different frequencies matches with theo-retical description on the TSV capacitor.[6] The TSV processing yield is observed to be ~90%. Further, TSV leakage currents are characterized for the successful dies. The leakage between four TSVs with con-nection pad to silicon substrate (measured TSV good dies after C-V characterization) is less than 1 pA for a voltage range 0–100 V as shown in the inset of Figure 3b. The probability plot for the TSV leakage (Figure 3b) shows <1 pA leakage current and higher breakdown voltage >100 V for all TSVs, suggesting satisfactory isolation between the TSV and the silicon substrate.

TSV chain and BS RDL were character-ized by four-points measurement on the first wafer after BS RDL. Figure 4 shows the results. The FS M1-TSV-BS RDL chain and FS M2-via-M1-TSV-BS RDL chain were characterized, with the results shown in Figure 4a. I-V curves of via chains (R = 1RTSV + 1Rtop metal + 1Rbottom metal + Rcontact) were characterized, and are shown in the inset of Figure 4a. The yield of the FS M1-TSV-BS RDL chain and FS M2-via-M1-TSV-BS RDL chain are observed to be 90% and 85%, respectively, after the BS RDL process that is shown in Figure 4a. More process optimization is being investi-gated to improve the TSV yield further.

Four-points testing was applied to characterize the resistance of BS RDL (line/space 10/10 μm) and shown in Figure 4b. BS RDL performance shows a good I-V curve, as seen in the inset of Figure 4b.

The probability plot (Figure 4b) shows a 100% electrical yield of BS RDL.

TSV integrated with FS four metal lay-ers on 300 mm silicon substrate complet-ed FS process development and electrical characterization. The wafers are process-ing BS metallization. The results will be reported in the future.

SummaryIn this article, we demonstrated and

characterized the TSI (with FS two met-als and BS one metal) for heterogene-ous integration. The preliminary electrical yield of the FS M1-TSV-BS RDL chain and FS M2-via-M1-TSV-BS RDL chain are 90% and 85%, respectively, on the first wafer. Ongoing processing improvements are in place to take yields to the high 90s.

The TSI platform offered at the Institute of Microelectronics (IME) is targeted for both low-cost and high-performance appli-cations. In addition, IME offers multi-pro-ject wafer (MPW) services that allow our industry/research partners to prototype 2.5D ICs by using IME’s TSI fabrication and assembly/packaging capabilities.

AcknowledgmentsThe authors wish to thank Linda Liew

and Lau Guan Kian for the fabrication of the TSI, Tang Leijun for the cross-section of interposer, and the staffs of the IME fab who supported this work.

References 1 K.W. Lee et al., “Characterization

of Chip-Level Hetero-Integration Technology for High-Speed, Highly Parallel 3D-Stacked Image Processing System,” IEDM 2012, p. 785.

2 G. Katti et al., “3D Stacked ICs Using Cu TSVs and Die-to-Wafer Hybrid Collective Bonding,” IEDM 2009, p. 357.

3 K.F. Yang et al., “Yield and Reliability of 3D IC Technology for Advanced 28nm Node and Beyond,” VLSI 2011, p. 140.

4 J.R. Cubillo et al., “Interconnect Design and Analysis for Through Silicon Interposers,” 3DIC, 2011 IEEE, p. 2.

5 “EV Group Launches ZoneBOND Capable Equipment and Open Platform for Temporary Bonding Materials,” www.evgroup.com/en/about/news/2011_10_zonebond_equipment.

6 G. Katti, M. Stucchi, K. De Mayer and W. Dehaene, “Electrical Modeling and Characterization of Through Silicon Via (TSV) for 3D ICs,” IEEE Trans. Electron Devices, January 2010, Vol. 57, No. 1, p. 256.

About the Authors

H.Y. Li, L. Ding, G. Katti, J.R. CubilloH.Y. Li, L. Ding, Guruprasad Katti and Joseph Romen Cubillo are scientists at the Institute of Microelectronics.

Surya Bhattacharya Surya Bhattacharya is director of indus-try development (TSI) at the Institute of Microelectronics.

G.Q. Lo G.Q. Lo is deputy executive direc-tor of research at the Institute of Microelectronics.


Through-Silicon Interposer Technology for Heterogeneous Integration

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WAFER FAB & PACKAGING INTEGRATION WAFER FAB & PACKAGING INTEGRATION

3D chip stacking promises high per-formance, low power consumption and a small footprint. The technology has made considerable progress in the past few years, with the appearance of the first interposer in 2011[1] and the first 3D Hybrid Memory Cube (HMC) prototype in early 2013. Adding momentum is the announcement of a global specification for HMC by the HMC Consortium.[2]

As an example of the growth of 3D technology, Figure 1 shows a cross-section of an interposer fabricated at Invensas. Figure 2 is an X-ray tomograph of the interposer showing the microbumped top die attached to the interposer, which in turn is attached to a substrate with C4 bumps. With increased availability of first-generation 3D technology, the logical question that follows is: What comes next for 3D? Since product generations have historically been driven by performance enhancements and cost reductions, this article takes a look at how 3D stacking could follow that path.

A New LeverThe most powerful lever for perfor-

mance and cost reduction that the semi-conductor industry has used over the past few decades has been lithographic scal-ing. Inexorably shrinking linewidths have

enhanced transistor performance and reduced costs at each node. However, the introduction of new materials and EUV lithography has whittled away at cost reductions to the point where it is project-ed that sub-32 nm nodes will actually result in cost increases per generation. With this in mind, 3D has an opportunity to “scale” in order to establish itself as the new engine for performance increases and cost reduc-tion, while also reducing the industry’s reli-ance on traditional lithography.

Even as 3D prototypes and low-volume products enter the market, the industry is grappling with concerns of cost and sup-ply chain readiness for high-volume manu-facturing (HVM). The first “pipecleaner” products will address technology gaps for HVM and iron out inefficiencies in the supply chain. For subsequent generations, the International Technology Roadmap for Semiconductors (ITRS) has provided road-maps for 3D.[3] For these to be relevant to the industry’s needs, the roadmaps must be validated with silicon-based data and must provide pragmatic projections into the future.

“Scaling” knobs will need to be investi-gated to address performance and cost ben-efits. Three of these will be discussed next. Since 3D stacking involves a combination of both front-end-of-line (FEOL) and assembly

3D Stacking: Act II bumps, this number might soon prove to be inadequate because of ever-increasing bandwidth requirements.

Yield is also a concern, and it might be necessary to use multiple microbumps for the same connection, much the way multiple contacts were used in the early days of scaling contacts in the front-end technology. As microbumps scale, reliabil-ity becomes a concern. This is due to the fact that, as the volume of the microbump scales down, the volume of the interme-tallic compounds (IMCs) formed at the interface does not. The IMC formation is expected to have a significant impact on the reliability of the chip-chip interconnect.

Sitaram Arkalgud Invensas Corp.

processes, the benchmarks must take the overall system performance into considera-tion, and must balance benchmarks for the front end as well as for assembly.

Chip-Chip Interconnect ScalingWith the need for ever-increasing band-

width at low power consumption, it is nec-essary to increase the number of chip-chip interconnects while continuing to run them at low speeds to avoid the need for paral-lel terminators, clock recovery, etc. The number of microbumps connecting two die are driven heavily by space consid-erations. Although today’s chip sizes can accommodate several thousand micro-

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Si Interposer

3-4-3 Build-Up Substrate

Micro-Bumps

C4 Interconnects

Figure 1. A cross-section of an interposer shows a top die connected to the interposer with microbumps, and C4 bumps connecting the interposer to the substrate.



As shown in Figure 3, a scaling road-map is developing for microbumps.[4] Driven by bump pitch and size dimensions, reflow of copper pillar with solder is pro-viding a minimum pitch of ~60 μm. Further scaling to ~20 μm is possible with thermo-compression bonding of copper pillars with solder caps, although the formation of IMCs will limit migration to smaller dimensions. Direct bonding of copper to copper (Cu DB) is being considered for further scaling.

Cu DB is a simpler materials system, and is compatible with the back-end-of-line (BEOL) metallization of the chips being stacked and bonded. This compat-ibility should help to improve the overall reliability of the system along with ther-

mal conductivity and power/signal integ-rity. Another longer-term advantage is that copper bump dimensions can scale for several generations beyond today’s microns, given the industry’s experience in chip BEOL metallization.

The biggest drawback of Cu DB is the process cost, since a good bond requires high pressure and temperatures in excess of 350°C. Work is underway at several R&D organizations to reduce the pro-cess temperature to 250°C and below,[4] which will drive the process cost to more reasonable numbers. However, scaling the microbumps will result in smaller stand-offs between the chips, which will impact the underfill methodology and materials. Capillary underfill systems, used widely

today, will need to give way to vacuum/pressure underfill methods and could finally lead to pre-applied underfill as the standoff gap drops to 10 μm and below.

Device ScalingThe industry has adhered to Moore’s

Law and doubled transistor count approxi-mately every two years through litho-graphic scaling. With the rising cost of future shrinks, increasing transistor count by stacking layers could be a viable, cost-effective option for staying on the Moore’s Law curve. Two possible “knobs” are dis-cussed below.

Wafer/die thickness scaling: The indus-try is working with 100 μm thickness for interposers and 50–75 μm thicknesses for 3D stacking. Reducing wafer thickness (and consequently die thickness) would allow stacking additional layers within a

given package height. This would also help to reduce the aspect ratio of through-silicon vias (TSVs) and delay the move to CVD and ALD processes for dielectric liner, barrier and copper seed deposition in the front end. However, assembly would need to deal with the non-trivial issue of stress and the associated warpage, and the ability to handle the wafer/die without yield loss.

TSV scaling: Shrinking the TSV diam-eter would reduce the area penalty due to both the TSV area and the keep-out zone around each TSV. This would allow increased density of TSVs on the chip as well as redundant TSVs for yield improve-ment. An additional benefit would be reduced thermo-mechanical issues caused by the CTE mismatch between copper in the TSV and the surrounding silicon, since the volume of copper in the TSV would be

3D Stacking: Act II WAFER FAB & PACKAGING INTEGRATION

Figure 2. An X-ray tomograph shows microbump arrays on C4 bumps and metal lines in an interposer stack.

Bonding Method C4 FC (Controlled Collapse Chip

Connect)

C2 FC

(Chip Connect)

TC/LR (Local Reflow) FC

TC FC

Schematic Diagram

Major Bump Pitch Range at Application

>130 μm 140 μm ~ 60 μm 80 μm ~ 20 μm <30 μm

Bonding Method Conventional Reflow

Reflow With Cu Pillar

Thermal Compression

with Cu pillar

Thermal Compression

Bump Metallurgy Solder (SnAg or SnAgCu)

Cu + Solder (SnAg or Sn)

Cu + Solder (SnAg or Sn)

Cap Cu

Bump Collapse Yes No No No

Underfill Method - Capillary

- No Flow

- Capillary

- No Flow

- Wafer Level

- No Flow

- Wafer Level

- No Flow

- Wafer Level

Figure 3. Scaling roadmap of chip-to-chip interconnects. (Reference: SEMATECH)

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reduced. However, without a correspond-ing decrease in the TSV depth (wafer/die thickness), the aspect ratio of the TSV would increase, leading to the need for CVD or ALD processes as the aspect ratios exceed 10:1. As a result, these knobs are not independent of each other, since each has an impact on the other (typically adversely), so co-optimization of pro-cesses in both the front end as well as in assembly is essential.

Cost Considerations and Summary

Finally, cost is a complex issue, and needs to be addressed on multiple fronts. By its very nature, 3D promises to reduce costs by “disintegrating” the product so that, unlike a system-on-a-chip (SoC), it will be possible to manufacture each tier in the stack in the most economically viable manner. This results in the entire chip not being held hostage to the cost of the highest node, as is the norm in SoC. In addition, stacking alone has the virtue of increasing device density in a given foot-print without lithographic scaling.

Finally, 2.5D and 3D have the potential to become true platform technologies, which begin by stacking dissimilar CMOS technologies, and rapidly assimilating non-CMOS technologies onto the platform in a cost-effective fashion. The true benefits of 3D will be realized as we go beyond today’s “pipecleaner” products and increase 3D’s footprint in the industry.

References1. Xilinx, www.xilinx.com.2. Hybrid Memory Cube Consortium,

www.hybridmemorycube.org.3. International Technology Roadmap

for Semiconductors, 2011 Edition, Interconnect Chapter, www.itrs.net.

4. Sitaram Arkalgud, “Scaling 2.5D/3D: The Next R&D Challenge,” Second Annual IEEE Global Interposer Technology Workshop, Georgia Institute of Technology, Nov. 14–16, 2012.

About the Authors

Sitaram ArkalgudSitaram Arkalgud is vice president–3D

products at Invensas, where he recent-ly joined after serving as director of SEMATECH’s Interconnect Division. He has more than 20 years of R&D and manufac-turing experience with the chip industry. He has a Ph.D. and a master’s degree in materials engineering from Rensselaer Polytechnic Institute, and a B.S. in met-allurgical engineering from Karnataka Regional Engineering College, Surathkal, India.


3D Stacking: Act II

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