Future Fab International Volume 41

In Association with: ISSUE 41 April 2012 www.future-fab.com

Accelerating the next technology revolution.

FUTURE FAB International | Issue 41

Welcome to the latest issueof Future Fab

Before you delve into the virtual pages of ourlatest issue, we wanted to have a quick rant. Doyou know what really annoys us here in the hal-lowed halls (ahem, office) of Mazik Media, thehome of Future Fab? The fact that so many thinkthat the semiconductor industry is yesterdaysnews, that its done, dusted and no longer of inter-est. Its rare to hear, see or read about our amaz-ing business outside of the handful of publishersthat are left clinging to life in this industry. MarkZuckerberg got a whole Hollywood film madeabout him and his face(book), and yet he andeveryone else in the dot-com world owe their exis-tence to the innovators of the traitorous eight ofShockley Labs fame, and if you dont know whatwere talking about, shame on you!

Well, were not going to take this laying down!What does this mean to you, our loyal readers?Well if you really want to know, send an email [email protected] well add you to a list of insiders.

We have big plans that are going to move usonto a different stage, literally. Watch this space ...but in the meantime, enjoy edition 41 in this, our16th proud year of existence!

Venimus, vidimus, venimus rabiem nosreflexae!

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CONTENTS | FUTURE FAB International | Issue 41

FUTURE VISIONS & CURRENT CONCERNS

11 IntroductionAlain E. Kaloyeros CNSE

12 Moores Law, Madmen andEconomistsPhillip Christie imec

18 Thought Leadership ProfileTotal Facility Solutions

20 Lithography 2020: Top Down Vs. Bottom UpGeoff Wild AZ Electronic Materials

CHIP ARCHITECTURE & INTEGRATION

25 IntroductionWarren Savage IPextreme

26 Semiconductor IP Standards:More Important Than You ThinkKaren Bartleson Synopsys

MANUFACTURING: FAB, SYSTEMS & SOFTWARE

31 IntroductionThomas Sonderman GLOBALFOUNDRIES

32 Thought Leadership ProfileCyberOptics

34 Advanced Process Control GoesManufacturing: APCM Conferencein EuropeKlaus Kabitzsch,1 Michael Klick,2 AndreasSteinbach,3 Alan Weber4 1DresdenUniversity of Technology 2PlasmetrexGmbH 3Von Ardenne AnlagentechnikGmbH 4Alan Weber & Associates

40 Fab Simulation and VariabilityJames P. Ignizio,1 Hernando Garrido2 1The Institute for Resource Management2Fresenius Medical Care

LITHOGRAPHY LANDSCAPE

48 IntroductionDaniel J.C. Herr Joint School ofNanoscience and Nanoengineering/UNC Greensboro

49 Section SponsorNikon

50 Optimum Dose for EUV: Technical vs. Economic DriversMoshe Preil GLOBALFOUNDRIES

Next generation lithography techniques continue to evolve, but IC makers need solutions today that will keep them on their aggressive technology roadmaps. In order to maintain production timelines, extension of ArF lithography is vital. To meet this challenge, Nikon developed two new 193 nm scannersthe latest evolutions of the proven Streamlign platform, which is already adopted in leading-edge facilities worldwide. The Nikon NSR-S621D immersion and NSR-S320F dry scanners satisfy the increasingly demanding requirements for imaging, overlay accuracy, and ultra-high productivity that are essential for cost-effective 22 nm applications and beyond.

Nikon. Evolution in Action. www.nikonprecision.com

4 | FUTURE FAB International | Issue 41

CONTENTS | FUTURE FAB International | Issue 41

FRONT END OF LINE

57 IntroductionDidier Louis CEA-Leti

58 Section SponsorHitachi

60 The Challenge to ReduceDissolved Oxygen for AdvancedProcessingChristiane Gottschalk ASTeX GmbH,a subsidiary of MKS Instruments

64 Thought Leadership ProfileSAFC Hitech

66 FDSOI for Next-GenerationSystem on Chip ApplicationsBruce Doris, Kangguo Cheng, Ali Khakifirooz IBM Research atAlbany NanoTech

METROLOGY, INSPECTION & FAILURE ANALYSIS

73 IntroductionAlain C. Diebold CNSE

74 Advanced TEM Imaging AnalysisTechniques Applied to BEOLProblemsFrieder H. Baumann IBMMicroelectronics Division

WAFER FAB & PACKAGING INTEGRATION

80 IntroductionPeter Ramm Fraunhofer EMFT

81 3D Hyper-Integration: Past,Present and FutureJames Jian-Qiang Lu RensselaerPolytechnic Institute

ASSEMBLY, TEST & PACKAGING TECHNOLOGIES

88 IntroductionWilliam T. Chen ASE (U.S.) Inc.

89 Design for Board-Level ReliabilityImprovement in eWLB PackagesWon Kyoung Choi, Yaojian Lin, ChenKang, Seng Guan Chow, Seung WookYoon, Pandi Chelvam Marimuthu STATS ChipPAC Ltd

99 Advertisers Index


EDITORIAL PANEL

Paolo A. GarginiDirector of Technology Strategy for Intel Corporation

Dr. Paolo Gargini is also responsible for worldwide research activities conducted outside Intel forthe Technology and Manufacturing Group by consortia, institutes and universities. He received doctorates in electrical engineering and physics from the Universita di Bologna, Italy.

Biographies of Future Fab's Panel MembersFor the full versions of the following biographies, please click here.

Welcome to our new Panel Member Mark McClear

Mark McClearGlobal Director, Applications Engineering, Cree LED Components

Mark McClear is responsible for LED lighting applications development and Crees ApplicationEngineering Technology centers worldwide. He holds a B.S. in electrical engineering from MichiganState University and an MBA from Babson College, and has 11 issued and published U.S. patents inelectronics, LED and solid state lighting.

Michel BrilloutSenior Adviser, CEA-Leti

Michel Brillout joined CEA-Leti in 1999, where he managed the silicon R&D. Prior to joining CEA-Leti, he worked for 23 years in the Centre National des Tlcommunications (France Telecom R&DCenter), where he held different positions in micro-electronics research. He graduated from colePolytechnique.

Alain E. KaloyerosSenior Vice President, CEO and Professor, College of Nanoscale Science and Engineering; University at Albany

Alain E. Kaloyeros has authored/co-authored over 150 articles and contributed to eight books onnanoscience, holds 13 U.S. patents, and has won numerous academic awards. He received his Ph.D.in experimental condensed matter physics from the University of Illinois, Urbana-Champaign, in 1987.

Gilbert J. DeclerckExecutive Officer, imec; Member of the Board of Directors, imec International

Gilbert J. Declerck received his Ph.D. in electrical engineering from the University of Leuven in1972. He has authored/co-authored over 200 papers and conference contributions. In 1993, he waselected fellow of the IEEE. Since July 1, 2009, Dr. Declerck has been executive officer imec and amember of the board of directors of imec International.

Didier LouisCorporate and International Communication Manager, CEA-Leti

Louis joined CEA-Leti (France) in 1985, where he received a Ph.D. in metallurgy/electrochemistryfrom the University of Grenoble. He has written more than 30 papers related to etching and strip-ping processing and has co-authored more than 60 scientific papers and eight patents.

6 | FUTURE FAB International | Issue 41 7www.future-fab.com |

EDITORIAL PANEL | FUTURE FAB International | Issue 41

Shishpal RawatChair, AccelleraDirector, Business-Enabling Programs; Intel Corp.

Shishpal Rawat holds M.S. and Ph.D. degrees in computer science from Pennsylvania StateUniversity, University Park, and a B. Tech. degree in electrical engineering from the Indian Instituteof Technology, Kanpur, India.

Jon CandelariaDirector, Interconnect and Packaging Sciences; SRC

Jon Candelaria has over 34 years experience in the electronics industry in a wide variety of engi-neering and managerial roles. He received his BSEE and MSEE from the University of New Mexico.

Yannick Le TiecTechnical Expert, CEA-Leti, MINATEC Campus

Yannick Le Tiec joined CEA-Leti in 1995 and received his Ph.D. in materials science and engineeringfrom the Polytechnic Institute, Grenoble, France, and his M.S. in chemistry from the National Schoolof Chemistry, Montpellier, France. He is a CEA-Leti assignee at IBM, Albany (NY), developing theadvanced 22 nm CMOS node and the FDSOI technology.

Alain C. DieboldEmpire Innovation Professor of Nanoscale Science; Executive Director,Center for Nanoscale Metrology, CNSE, University at Albany

Alains research focuses on the impact of nanoscale dimensions on the physical properties ofmaterials. He also works in the area of nanoelectronics metrology. Alain is an AVS Fellow and asenior member of IEEE.

Thomas SondermanVice President, Manufacturing Systems Technology; GLOBALFOUNDRIES

Thomas Sonderman obtained a B.S. in chemical engineering from the Missouri University ofScience and Technology in 1986 and an M.S. in electrical engineering from National TechnologicalUniversity in 1991. He is the author of 43 patents and has published numerous articles in the area ofautomated control and manufacturing technology.

Rohan AkolkarSenior Process Engineer, Components Research; Intel Corporation

Dr. Akolkar received the Norman Hackerman Prize of the Electrochemical Society in 2004, andnumerous Intel Logic Technology Development awards. He has authored more than 40 technicalpapers, invited talks, and U.S. patents in the area of electrodeposition.

Christo BojkovSenior Package Development Engineer, TriQuint Semiconductor

Dr. Christo Bojkov has published over 30 publications and holds 15 patents. Since receiving hisdoctorate in chemical engineering, he has worked and taught in academia for over 10 years inphysical chemistry and surface science.

Steve GreathouseGlobal Process Owner for Microelectronics, Plexus Corp.; Idaho

Steve Greathouse has published many articles on technical topics related to semiconductor pack-aging, failure analysis and lead-free packaging. He has a B.S. in electronic physics from WeberState University with advanced studies in material science and computer science.

Daniel J.C. HerrProfessor & Nanoscience Department Chair, JSNN; UNC Greensboro

Dr. Herr is a pioneer in collaborative nanotechnology research. He is professor and chair of theNanoscience Department at the new Joint School for Nanoscience and Nanoengineering inGreensboro, North Carolina. Until recently, Dr. Herr served as the director of SemiconductorResearch Corporations Nanomanufacturing Sciences area. He received his B.A. with honors inchemistry from Wesleyan University in 1976 and his Ph.D. from the University of California at SantaCruz in 1984.

William T. ChenSenior Technical Advisor, ASE (U.S.) Inc.

Bill Chen is the co-chair of the ITRS Assembly and Packaging International Technical WorkingGroup. He was elected a Fellow of IEEE and a Fellow of ASME. He received his B.Sc. at Universityof London, MSc at Brown University and Ph.D. at Cornell University.

Liam MaddenCorporate VP, FPGA Development & Silicon Technology; Xilinx, Inc.

Liam Madden is responsible for foundry technology, computer aided design and advanced pack-age design. He earned a BE from the University College Dublin and an MEng from CornellUniversity. Madden holds five patents in the area of technology and circuit design.

Alan WeberPresident, Alan Weber & Associates

Alans consulting company specializes in semiconductor advanced process control, e-diagnosticsand other related manufacturing systems technologies. He has a bachelors and a masters degreein electrical engineering from Rice University.

Yayi WeiSenior Member, Technical Staff; GLOBALFOUNDRIES

Dr. Wei investigates advanced lithography processes and materials. He has over 16 years of lithog-raphy experience, including DUV, 193 nm, 157 nm, 193 nm immersion, EUV and E-beam lithography.Dr. Wei has numerous publications and holds several patents in the field of lithography.

David G. SeilerChief, Semiconductor and Dimensional Metrology Division, NIST

David G. Seiler received his Ph.D. and M.S. degrees in physics from Purdue University and his B.S. in physics from Case Western University.


EDITORIAL PANEL | FUTURE FAB International | Issue 41

Giuseppe FazioAdvanced Process & Equipment Control Sr. Engineer; Micron Semiconductors Italy

With a laurea degree in applied physics from Milan University, Giuseppe has working experience inseveral sectors, from research to industry, and vast experience in industrial and scientific instru-mentation. He has authored/co-authored many articles, is an avid contributor at conferences andholds several patents in the semiconductor field.

Peter RabkinDirector of Device & Process Technology, SanDisk Corp.

Dr. Peter Rabkin focuses on development of novel 3D memory technologies and products. Heholds a masters degree in physics from Tartu University and a Ph.D. in physics of semiconductorsfrom the St. Petersburg Institute of Physics and Technology.

Sitaram R. ArkalgudDirector of Interconnect, SEMATECH

Sitaram R. Arkalgud has over 20 years of R&D and manufacturing experience within the chip indus-try. He has a Ph.D. and a masters degree in materials engineering from Rensselaer PolytechnicInstitute, and a B.S. in metallurgical engineering from Karnataka Regional Engineering College,Surathkal, India.

Daniel C. EdelsteinIBM Fellow; Manager, BEOL Technology Strategy, IBM T.J. Watson Research Center

Dr. Edelstein played a leadership role in IBMs industry-first Cu Chip technology in 1997, in theintroduction to manufacturing of Cu/Low-k insulation in 2004. He received his B.S., M.S., and Ph.D.degrees in applied physics from Cornell University.

Christian BoitHead, Semiconductor Devices at Berlin University of Technology, Germany

The Berlin University of Technology is an institution for research and development in the areas ofdevice simulation, technology, characterization and reliability. Christian Boit received a diploma inphysics and a Ph.D. in electrical engineering on power devices, then joined Siemens AGs ResearchLaboratories for Semiconductor Electronics in Munich and has been a pioneer on photoemission.

Pushkar P. AptePresident, Pravishyati Inc.

Dr. Pushkar P. Apte's strategy consulting firm focuses on the high-tech industry. He received hismasters and Ph.D. from Stanford University in materials science and electrical engineering, and hisbachelors degree in ceramic engineering from the Institute of Technology, Varanasi, India.

Dr. Jiang YanProfessor, IMECAS

Dr. Jiang Yan has authored and co-authored over 30 papers, holds 17 U.S. patents and five Chinapatents. He received his Ph.D. in electrical engineering from the University of Texas at Austin in 1999.

Klaus-Dieter RinnenDirector/Chief Analyst, Dataquest

Klaus-Dieter Rinnen is director for Dataquests semiconductor and electronics manufacturinggroup. He received a diploma degree in physics with minors in physical chemistry and mechanicalengineering in Germany, and a Ph.D. in applied physics from Stanford University.

John SchmitzVP & General Manager, Intellectual Property and Licensing; NXP

John Schmitz holds a master's degree in chemistry from Radboud University of Nijmegen,Netherlands, and a doctorate in physical chemistry from Radboud University Nijmegen. He hasauthored more than 45 papers in various scientific journals and has written books on IC technolo-gy and on thermodynamics.

Lode Lauwers Director Strategic Program Partnerships for Silicon Process & Device Technology, imec

Lode Lauwers has an M.S. in electronics engineering and a Ph.D. in applied sciences. He joinedimec in 1985 as a researcher. Lode manages imecs core partner research program on sub-32nmCMOS technologies.

Ehrenfried Zschech Division Director for Nanoanalysis & Testing, Fraunhofer Institute forNondestructive Testing; Dresden, Germany

Ehrenfried Zschech received his diploma degree in solid-state physics and his Dr. rer. nat. degreefrom Dresden University of Technology. He has published three books and over 100 papers in sci-entific journals on solid-state physics and materials science.

Janice M. GoldaDirector, Lithography Capital Equipment Development; Intel Corp.

Janice Golda manages an organization responsible for creating strategies and working with Intelslithography, mask and metrology suppliers and subsuppliers to deliver equipment meeting Intelsroadmap technology, capacity and cost requirements. She is a member of the Berkeley CXROAdvisory committee, is Chairman of the Board for the EUV LLC and holds one U.S. patent.

Luigi ColomboTI Fellow

Dr. Luigi Colombo is a TI Fellow working on the Nanoelectronic Research Initiative (NRI). He is author and co-author of over 130 publications, three book chapters, and holds over 60 U.S.patents. Dr. Colombo received his Ph.D. in materials science from the University of Rochester.

Warren SavageChief Executive Officer, IPextreme

Warren Savage has spent his entire career in Silicon Valley, working with leading companies, wherehe focused on building a global scalable semiconductor IP business. In 2004, he founded, and stillleads IPextreme in the mission of unlocking and monetizing captive intellectual property held withinsemiconductor companies and making it available to customers all over the world. He holds a B.S. incomputer engineering from Santa Clara University and an MBA from Pepperdine University.

FUTURE VISIONS & CURRENT CONCERNSClick here to return to Table of Contents

The best way to predict the future, ithas been said, is to invent it. Such is thecase with manufacturing, which relies onongoing innovation to enable advance-ments in reliability, efficiency and cost.

Few sectors reflect this reality betterthan a technology-heavy industry likenanoelectronics. But how long can inno-vation alone, particularly as it has beenmanifested over the past 47 years in theform of Moores Law, continue to supportthe fundamental economics that drive thecontinued pursuit of smaller and fasterdevices? In this context, most industryleaders would agree that lithography hasprovided many of the greatest challengesand rewarding solutions with respect tothe technical viability and associated economics of continued device scaling in the sub-100 nm device era.

Parsing the economic and technicalaspects of dimensional scaling of inte-grated circuits is an overarching theme in this editions Future Visions & CurrentConcerns section.

From an economic perspective, imecsPhillip Christie carries out a refresher onthe manufacturing model within GordonMoores Moores Law paper from 1965. Inhis article, he makes a number of thought-provoking and compelling conclusions

Alain E. KaloyerosSenior Vice President, CEO and Professor College of Nanoscale Science and Engineering; University at Albany

regarding the ultimate cost benefits ofcontinued device scaling, especially as itrelates to the concomitantly increasingcosts of patterning as devices shrink.

Looking more directly at the process-ing and manufacturing aspects of scal-ing, AZ Electronic Materials Geoff Wildoffers a novel perspective on an alterna-tive to conventional lithographic tech-nologies. He echoes the issue of theexponentially increasing cost of lithogra-phy with time, and suggests that, if cur-rent trends continue, the cost-per-pat-terning toll by 2020 will be approachinghalf a billion dollars. This prohibitive cap-ital cost will continue to marginalize allbut the largest chip manufacturers, caus-ing further erosion in market competi-tion. Mr. Wild discusses directed self-assembly as a potentially cost-effectivesolution for nanoscale patterning thatrelies on the composition of appliedblock copolymers to precisely define surface structures.

This introduction was co-authored by Alain E. Kaloyeros, Ph.D.; Eric T. Eisenbraun,Ph.D., CNSE associate professor of nano-science; and Steve Janack, CNSE vice pres-ident for Marketing and Communications.

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Peter RammHead of Device and 3D IntegrationDepartment, Fraunhofer EMFT; Munich

Peter Ramm received his physics and Dr. rer. nat.degrees from the University of Regensburg. He hasauthored or co-authored over 100 publications, includ-ing three book chapters and 23 patents.

Davide Lodi Baseline Defectivity & MetrologyEngineering Manager; MicronSemiconductors Italy

After graduating in physics from the University ofMilan, Davide Lodi started working in 1997 forSTMicroelec-tronics as a process engineer. Afterbecoming the manager of Wet Processes andMetrology Engineer-ing at the NVM R&D Agrate site,he moved to Numonyx, which was acquired byMicron in 2010.

Stephen J. Buffat Staff Research Scientist, Lockheed Martin NanoSystems

Stephen Buffat is responsible for the startup andoperation of Lockheed Martins nanotechnology facili-ty and operation in Springfield, Mo. He has authoredor co-authored numerous articles on photolithogra-phy, etch and 300 mm surface preparation processtechnologies.

Steven E. SchulzPresident and CEO, Silicon Integration Initiative, Inc.

Since 2002, Steve Schulz has served as presidentand CEO of Si2, the leading worldwide consortiumof semiconductor and software companies charteredto develop EDA standards. He has a B.S. in electricalengineering from the University of Maryland atCollege Park, and an MBA from the University ofTexas at Dallas.

13www.future-fab.com |12 | FUTURE FAB International | Issue 41

FUTURE VISIONS & CURRENT CONCERNS FUTURE VISIONS & CURRENT CONCERNS

The economist Kenneth Boulding isfamously quoted as saying Anyone whobelieves exponential growth can go on for-ever in a finite world is either a madman or an economist. So engineers who areneither obviously mad nor practitioners ofthe dismal science have learned to livewith the surprising longevity of MooresLaw with what amounts to an intellectualshrug of the shoulders. This is highlyrational behavior, since history has shownthat predicting the end of Moores Law isessentially not at all cool.

While accepting that scaling devicesbelow the atomic scale is clearly going tobe a challenge, there appear to be no insur-mountable technological barriers to thecontinued health of Moores Law in themedium term. However, Moores Law is self-evidently not the driver of technologicalchange but rather a consequence of a particular set of economic incentives thatmake it extremely profitable to continue toincrease the number of components on achip every couple of years. The purpose of this article is to identify these incentivesand to speculate on what might happen ifthese incentives change and how the indus-try might evolve to accommodate them.

Moores original 1965 paper[1] madetwo key assumptions. The first was thatthe cost per chip was nearly independent

of the number of components[2] on thechip. In other words, the cost per comp-onent was nearly inversely proportional to the number of components.

This creates a powerful incentive for achip company to drive down this comp-lexity curve until, as stated by the secondassumption, the smaller distance betweencomponents rapidly leads to decreasedyields and this overwhelms the cost advan-tages of putting more components on achip. This results in an optimum componentcount at minimum cost for a fixed techno-logy. This is illustrated in Figure 1, which hasbeen generated using the same manufac-turing and defect models used in Moorespaper, and where the resulting optimumnumber of components per chip at mini-mum cost for a given technology node isindicated by a circle. This graph (which inits original form contained data for onlytwo nodes) was used by Moore to infer adoubling of the component count everytwo years which, in various modified forms,later became identified as Moores Law.

Viewed from this perspective, the keyeconomic principle driving Moores Law isthat each successive technology node suc-ceeds in controlling defect densities, there-by increasing the maximum number ofcomponents per chip that can be achievedat minimum cost. A corollary is that, if the

Moores Law, Madmen and Economists

cost of a chip is determined only by itsprocessing costs, then the costs associatedwith masks, design effort and processingequipment must be assumed insignificant.

Unfortunately, what is often referred toas Moores Second Law (more accuratelyreferred to as Rocks Law), says that thesenon-recurring costs are also rising expo-nentially with each node. The only way toride the Moores Law curve is to amortizethe non-recurring cost overhead over larg-er and larger numbers of wafers, or to useincreasingly bigger wafer sizes. In effect,the continuation of Moores Law requiresthe demand for a product to be infinite.

To gain more insight into the conse-quences of finite demand for products, we can add a term to Moores model thataccounts for non-recurring costs. The meth-od is quite general, but to provide a specificexample, we shall consider mask costs.

Due to the limitations of optical litho-graphy, the ratio of mask costs to wafer processing costs (that is, the ratio of non-recurring to recurring costs) hasincreased by a factor of 10 as we havetransitioned from 0.5 m (500 nm) tech-nology to 28 nm technology. Mooresmodel, however, refers to costs per com-ponent, and while processing costs per

Phillip Christie imec

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Figure 1. An Extension of the Manufacturing Model Proposed in Moores 1965 Paper[1] to Illustrate the Manufacture of Chips at Minimum Cost


component have been falling appropriate-ly, the mask costs per component haveremained approximately constant. If thisconstant, non-recurring amount is addedto the manufacturing cost in Mooresmodel, then we obtain the sequence ofcurves shown in Figure 2. These datahave been generated by assuming thatthe non-recurring mask costs have beenspread over 10,000 wafers and that thearea of a chip at each node is constant.The result is that there is no benefit in

transitioning to a new technology nodewhen the processing cost per componentbecomes comparable to the mask costper component.

In this model, there are only three waysto continue to follow Moores Law andincrease the number of components perchip with each new technology node: 1)spread the non-recurring costs over anincreased number of wafers and so effec-tively lower the non-recurring cost floor;2) use bigger wafers; and 3) the most

heretical option is to produce componentsat a higher than minimum cost.

The strategy of processing more andmore wafers has pushed Moores underly-ing infinite demand requirement to its lim-its. For the most aggressive technologynodes, there are fewer and fewer productsthat can be sold in enough volume to beeconomically viable. This has made it evermore difficult for smaller businesses, andeven medium-sized businesses, to takeadvantage of the improved performance of the latest technology nodes. The secondstrategy of increasing the wafer size waslast performed at the 130 nm node, butmarshalling the required industry invest-ment to implement a transition from 300mm to 450 mm wafers looks like it mighthappen, at the earliest, in 2015. But, as forthe first option, only a dwindling numberof products that can be sold in the hugevolumes required to hit the minimum costpoint will benefit from it.

The third option will result in a startling-ly new business experience for the majori-ty of companies. By following this strategy,their new product will have more compo-nents (at the same area), at possibly fasterclock rates and reduced power, but it willcost more to reach economically viableproduction volumes. For these companies,Moores Law will have passed through aminimum price point. Should we worryabout this?

Some insight may be gained from theauto industry. Figure 3 shows 100 yearsof average car prices[3] expressed in2010 dollars. The phase of exponentiallyfalling average manufacturing cost percar lasted for 40 years until 1940. Asmaller data set for the Ford Model T(which may be interpreted as represent-ing the minimum car cost, also convertedto 2010 dollars) also exhibits a dramatic

price reduction phase that lasted until itpassed through a minimum price pointafter which it stopped production in 1927.Due to a lack of published data, it is a point for speculation as to whether theprice of the most expensive cars with thebiggest profit margins has ever passedthrough a minimum price point! It is notthe purpose of this article to assert theeconomic similarities between the auto-motive and semiconductor industries, asclearly there are very large differences.Our only goal is to postulate that a mini-mum price point does not necessarilyimply the end of growth but that someadjustment to long-term business modelsmay be required to ensure continuedprofitability.

So might we be approaching a mini-mum price point in the semiconductorindustry? It is still very early in the adop-tion cycle to make concrete predictions,but there is some evidence that the tran-sition to 32/28 nm technologies will notresult in the cost savings that have beenexperienced historically.

In another example of the durability ofMoores original paper, he writes:

Clearly, we will be able to build suchcomponent-crammed equipment. Next weask under what circumstances we shoulddo it. [...] It may prove more economical to build large systems out of smaller func-tions, which are separately packaged andinterconnected.

Clearly, this second assembly approachlost out to the much more attractive economics of large-scale integration, butwhat are we to make of the emergence of 3D die stacking and interposer strate-gies that seem to be gaining headwaytoday? This has been referred to in manyarticles as moving Moores Law to the thirddimension, but the higher assembly costs

Moores Law, Madmen and Economists FUTURE VISIONS & CURRENT CONCERNS

Figure 2. The Addition of Non-recurring Costs Results in a Shift Away From Moores if Constrained by Minimum Cost


of these techniques make it difficult toaccept that they qualify for the minimumcost criterion that drives Moores Law.

An interesting conjecture about passingthrough a minimum price point is that itresults in the end of technology commodi-tization. This concept provided the ration-ale for companies transitioning to a fab-litestrategy that essentially regarded wafercapacity as a commodity to be traded, like wheat or iron ore. In a scenario wherechip prices are rising due to finite product

demand, foundries like Japanese car manufacturers in earlier decades can gainmarket share by offering increased prod-uction flexibility with ever-more-targetedoptions to offset the advantages that themega-volume customers currently have inearly access to leading-edge technology.Some evidence for this is that the numberof options offered with each new technolo-gy node has been growing rapidly, and atthe 28 nm node, even a high-performanceoption targeted for mobile devices is on

offer from a foundry. Several of theseoptions come with additional extendedthreshold voltages (ultra-low and ultra-high), as well the possibility of the low-costtuning of device characteristics by selectingseveral nm-scale offsets (both positive and negative) to transistor gate lengths.

In a post-minimum price-point world, thecosts and risks associated with flexible, tar-geted manufacturing need to be carefullycontrolled. It only makes sense if the cus-tomer meaning the company designingthe marketing for the product produced bythe foundry has a good grasp of how dif-ferent technology choices affect perform-ance. The foundry customer must be able toassess how the multiple technology choicesoffered by the foundry affect the perform-ance of the product during the early designphase. This level of knowledge that can be supported within large companies mayprove to be a big challenge for the smalland mediums-sized businesses that willbenefit most from this strategy.

The closer coupling between designand technology also makes it harder toshop around. Guaranteeing access to limit-ed, tailored wafer capacity will create large incentives for foundries to lock incustomers. This may even lead to upfrontpayments to ensure product delivery. Inthis scenario, the fabless and fab-lite cus-tomers become heavily invested in theirown foundry access, a model that hasbeen termed foundry-lite.

The idea of rising prices with each newtechnology node will take some getting usedto. It will require much better communicationbetween the producers and consumers oftechnology. But these changes will not nec-essarily stop the growth and profitability ofthe chip industry, unless you subscribe to theviews of madmen or economists.

Endnotes1. The original article by Gordon E. Moore,

Cramming more components ontointegrated circuits, Electronics, pp. 114-117, April 1965 has been reprinted in Proc. IEEE, vol. 86, No. 1, pp. 82-85,January 1998.

2. In this article, the use of the word component in Moores original paperis continued and implies the smallestdesign component that could representa simple logic gate, such as an inverterwith two transistors, a SRAM memorybit with six transistors or an individualtransistor.

3. U.S. Department of Energy, VehicleTechnology program. The data havebeen expressed in 2010 dollars usingthe GDP deflator.

About the Author

Phillip Christie Phillip Christie has over 25 years

international experience in IC technologyresearch and development. Based in theBrussels area at imec, a world-leading center for nanotechnology research anddevelopment, he is responsible for foundry technology assessment, tactics and strate-gy for small/medium businesses and fab-less/fab-lite companies. Phillip is a regularspeaker at conferences, with an extensiveportfolio of published articles and peer-reviewed research papers.


Moores Law, Madmen and Economists FUTURE VISIONS & CURRENT CONCERNS

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E-MAILthis articleFigure 3. Manufacturing costs for cars expressed in 2010 dollars. Red circles indicate average costs,

blue circles indicate Ford Model T prices.

Future Visions & Current Concerns


Thought Leadership Profile

Over the past two years, the semicon-ductor manufacturing industry has facedsignificant challenges in order to meet thedemanding technology curve of MooresLaw as well as the constraints of the con-sumer market.

Remaining competitive in this environ-ment seems to require the impossible: con-tinuing to innovate and achieve technol-o-gical breakthroughs at an ever-lower costper die. And yet, this is exactly the trenddemanded by our industry. While our worktoday is more challenging than ever before for example, the requirements for cleanli-ness integrity for 20 nm tools has neverbeen higher it must be achieved at an

even lower cost than the less advancednodes required just a few short years ago.

The semiconductor market continues tobe hyperefficient in meeting ever-evolvingtechnology and consumer demands. Thisefficiency improvement and ability toincorporate change has been seen acrossall aspects of the semiconductor manu-facturing supply chain, literally from theground up. Even facility design and buildhas stepped up to meet highly compressedwork schedules and adjusting to changewhile ensuring facilities are equipped fortruly next-generation requirements.

Total Facility Solutions is uniquely pos-itioned in the industry to address these

market challenges. Our portfolio of designand build services can take a facility all theway from 3D CAD design to self-performspecialty construction, including testingand validation, from a single vendor. Ourunique and comprehensive offering allowsus to address projects from start to finishunder one umbrella, leading to cost savingsand schedule efficiencies, and also adjust-ing to changing conditions, especially rela-tive to sourcing multiple vendors to per-form these same roles.

Total Facility Solutions has developed its own methods for providing higher levelsof performance and safety to address mar-ket requirements. Our teams are more effi-cient than ever. Even while dealing withmuch more complex equipment and facilitydemands, we are able to complete muchlarger and more complex installations inless time, enabling our customers to rampto production faster than ever before.

At the heart of our ability to continu-ously innovate and achieve increased effi-ciencies while maintaining strict safetystandards is our focus on employee train-ing. Our industry-leading training ensuresthat our workforce is always up-to-datewith the latest market and technologychanges. Our private-public partnershipsthat focus on integrated curriculum areunique in the industry, and enable the con-tinued advance of increased performanceat the lowest possible cost.


Total Facility Solutions vision is to bethe preferred, single-source providerof process-critical infrastructure forcustomers in the semiconductor, lifescience, photovoltaic and data centerindustries.

Joe CestariPresident

Mike Anderson Executive Vice President/Chief Operating Officer

Chris Walton Vice President, East Region

Robert Hill Vice President, West Region

Joe MinerVice President, Electrical

Total Facility Solutions 1001 Klein Road Suite 400Plano, Texas 75074Phone [email protected]

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FUTURE VISIONS & CURRENT CONCERNS FUTURE VISIONS & CURRENT CONCERNS

AbstractAs the costs of lithography continue

to escalate for future generations, a viableand complementary alternative is emerg-ing in the form of directed self-assembly(DSA). In lithography, all the informationfor the patterning is transmitted topdown from the mask, but cost scales with complexity. The DSA approach uses a bottom up chemical approach, similarto that used in nature, to drive complexitywith a potentially compelling cost of own-ership. This article reviews the opportunityand current status of the work.

By 2020, CMOS technology may havereached its physical limit, and we may beproducing devices based on new designsand new materials, such as graphene ornanotubes. While we do not know withcertainty what we will be making, it is asafe bet it will be made by some form oflithography. EUV lithography will haveironed out the bugs by 2020, but at a highcost: Extrapolating the historical exponen-tial increase in the cost of exposure toolsleads to a sticker price of $300-500 mil-lion per tool (Figure 1). By 2015, it is esti-mated that 30 percent of layers will haveto use some form of advanced patterning:

either multiple patterning, or EUV; by2020, that number will have risen to wellover 50 percent. For the 8 nm node or forsmaller devices, it may even be necessaryto use EUV in combination with multiplepatterning, an even-more-frightening costperspective. We may be able to developthe technology needed for this kind ofprocess/tool combination, but the questionis whether the economics can ever supportit in mass production. There is a growingfeeling that something has to give thatlithography is in need of a new and lower-cost paradigm.

The current lithography processes canbe thought of as a top down approach:All the information needed to make a chiplayer is encoded in a mask and transferredin the exposure step. With increasingamounts of information, this top-downapproach bumps up against the limits ofphysics and becomes exponentially moreexpensive. In contrast, systems in natureoften use a bottom up approach, inwhich components of a structure havebuilt-in chemical intelligence and self-assemble into the final functional structure.In a bottom-up approach, the cost of astructure can rise linearly, or even less thanlinearly, with the amount of information it contains.

Lithography 2020: Top Down Vs. Bottom Up

Today, the most advanced technologythat uses a bottom-up approach for semi-conductor applications is the directed self-assembly (DSA) of block copolymers. Inblock copolymers, the long, connectedstrings of monomer A and monomer B(i.e., AAAAA BBBBB ) prefer to inter-act with their own kind rather than withthe other monomer, resulting in phase sep-aration. Since the two strings are chemical-ly bound, they cannot move too far awayfrom each other, and the block copolymerstherefore spontaneously self-assemble into a number of defined 3D phases thatdepend only on their chemical composi-

tion (Figure 2). Of these phases, thehexagonal rod and lamellar phases bear astriking similarity to the contact hole andline/space patterns made by photolithog-raphy, if they are oriented perpendicularlyto the wafer surface. This vertical orienta-tion can be achieved by coating the wafersurface with a material that has equalaffinity to both A and B phases a neutralunderlayer.

Even with a neutral underlayer, however,the self-assembled patterns are not imme-diately useful for chip-making. This isbecause they will not naturally assemble in the right spot on the wafer, nor in the

Geoff Wild AZ Electronic Materials

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1

10

100

1985 1990 1995 2000 2005 2010 2015 2020

To

ol C

ost

[$ m

illio

n]

Figure 1. Historical Cost of Exposure Tools ($ million)


desired chip layout. For example, a lamellarphase on a neutral underlayer will arrangeitself in a fingerprintlike pattern that is use-less for chip-making (Figure 3). Directedself-assembly solves this problem by pro-viding guide structures to which the pat-terns can align themselves. In the exampleof Figure 3, the guide structures are linestraditionally patterned by 193 nm immer-sion lithography, and their size and spacingis chosen so that four lamellae pairs can fitinto the space previously occupied by oneguide structure. Etching away block B

selectively yields a 13 nm line/space struc-ture that has four times the frequency ofthe guide line. This is much smaller thancan be achieved by immersion lithographyand is a significant challenge to make withEUVL.

Higher-frequency multiplication factorsof six and more are possible, as is theoption of pinning more than one lamella to the guide structure, which could expandthe use of existing 193 nm immersion toolsets to the 8 nm node (Figure 4). DSA atthese feature sizes will require develop-

ment of new polymers; however, comparedto, for example, changing the EUV wave-length to 6.7 nm, this is a comparativelysimple and cheap development task.

Beyond line/space frequency multiplica-tion, DSA processes can also provide con-tact hole multiplication and rectification,with the latter being of particular interestfor contacts made by EUV lithography,which suffer from low CD uniformity dueto shot noise. The cost of the DSA process,

not counting the formation of the guidestructures, is almost independent of fea-ture size, requiring only the coating andannealing of the neutral underlayer andblock copolymer, and an etch step. Theeconomics of DSA patterning comparestherefore very favorably with that of multiple patterning and EUVL processes.

This low-cost/high-performance prom-ise of DSA has recently led to a surge ininterest from both industry and academia.

Lithography 2020: Top Down vs. Bottom Up FUTURE VISIONS & CURRENT CONCERNS

Figure 3. Concept of DSA for line/space frequency multiplication. (right): Cross section of 13 nm L/S patterns made with DSA using 193 nm immersion guide structures (after dry etch). Courtesy of IBM

Figure 4. 12.5 nm L/S DSA structures on guidelines patterned with 193 nm dry lithography (35 nmlines/150 nm pitch - 6x pitch division with guide structure width 1.5 L0). The same approach can enablethe use of 193 nm immersion lithography for the 8 nm node (24 nm guide structure, 120 nm pitch).

Figure 2. a) Block Copolymer Morphologies; b) Self-assembly of A-B Block Copolymer Into a Lamellar Phase

CHIP ARCHITECTURE & INTEGRATIONClick here to return to Table of Contents

One of the key lessons from theindustrial revolution was that standard-ization enables markets to grow atexplosive rates. Standardization radicallyaltered the landscape of transportation(standard railroad gauges), warfare(interchangeable parts in Winchesterrifles) and production (Henry Fordsassembly line). Indeed, even the distri-bution method of electricity involved apitched battle between Nicola Tesla (AC) and Thomas Edison (DC) as towhat standard would be adopted for the power grid we still use today.

As it was 100 years ago, standardiza-tion today allows industries to grow inimportant new directions by incorporat-

Warren SavageChief Executive Officer, IPextreme

ing the combined wisdom of the tech-nical community into a format that thefuture can be built upon. Because of theglobalization of our economies, thesetechnical standards have a faster andmore widespread effect than ever before.

In the following paper by KarenBartleson of Synopsys, you will see theimportant role that standards play in thesemiconductor market today. Importantnew standards are continuously requiredto enable new efficiencies in design,interchange, quality and connectivitythat will be required for the industry tokeep pace with the relentless demand ofconsumers and to capture the ingenuityof our engineers.

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Promising results have already beenobtained on one of the main questionsabout DSA whether its thermodynamicsand kinetics can lead to defectivity levelscommensurable with chip-making. A jointIBM/AMAT full wafer study found noimmersion specific defects and was able to place an upper limit of


CHIP ARCHITECTURE & INTEGRATION CHIP ARCHITECTURE & INTEGRATION

What Are Technical Standards?Standards are abundant in todays

world, and they are quite diverse. Thereare standards for health and safety, stan-dards for measurement and even stan-dards for human behavior. The type ofstandard that is most apparent in the semi-conductor industry is the technical stan-dard. A technical standard is defined inWikipedia as an established norm orrequirement about technical systems. It isusually a formal document that establishesuniform engineering or technical criteria,methods, processes and practices.

Modern system-on-chips (SoCs) dependheavily on technical standards. Designdescriptions are written in standard lan-guages. Design intent, such as low-powermanagement, is written in standard formats.A design database, such as OpenAccess, isat the heart of the process for custom andanalog design. Electronic design tools inter-operate with each other, configured intosophisticated flows, using industry stan-dards from formal committees and thosethat arise as de facto standards.

SoCs are not designed from scratch.They start with building blocks known assemiconductor IP. Within the industry, the

blocks are called simply IP, not to beconfused with Internet Protocol or intel-lectual property in the general sense. IPblocks, too, rely on standards long beforethey find their way into an SoC.

The Importance of Standards for IP

At the beginning of an IPs life, stan-dards come into play. The IP is designedand verified using standard hardwaredescription languages like Verilog andSystemC. The IP is then sold as a designwritten in Verilog (or other HDL) accompa-nied with a testbench in SystemC (or otherlanguage). Additional information, war-ranties and so on also come with an IPproduct, but standards form the fabric ofthe IP. A positive result of using a standardto design an IP is that it can be readilyinteroperable with other IP and parts ofthe SoC that use the same standard.

The IP can also implement a standard.This is particularly true for interface IP.Interfaces have become household wordsby now, such as USB and Ethernet. (Well,maybe Ethernet isnt a household wordunless your household is composed ofgeeks.) An SoC or a less complex

Semiconductor IPStandards: More Important Than You Think

regular integrated circuit often needssome type of common method for com-municating with the outside world. Themost effective way to implement an inter-face standard is to buy an existing IP.Designing your own USB interface mightbe a fun challenge, but probably not worththe time and effort. There are many USB IP vendors that will be happy to save youthe time and effort, for a price, of course.

The burning question, then, is how doyou know if the IP you want to purchasehas the level of quality that you need?Again, standards can help. The standardofficially known as 1734-2011 - IEEEStandard for Quality of Electronic andSoftware Intellectual Property Used in

System and System on Chip (SoC)Designs was created for this purpose.

From the IP vendors perspective, thereis a need to protect the source code ofthe IPs design. When an IP is representedin a standard language, the design mighteasily be seen and understood. It would be harmful, if not devastating, to the IPowners business to have a competitorreverse-engineer and clone the IP. Thelegal system could be called upon in thiscase, but its better to prevent it from happening in the first place. There is astandards project under way in the IEEEStandards Association called P1735 -Recommended Practice for Encryption and Management of Electronic DesignIntellectual Property (IP) that has the goal of addressing this need in addition to other IP interoperability challenges.

Possibly the most important role thatstandards play in the IP arena is allowingthe IP to talk to other IP and custom-designed portions within an integrated circuit or SoC. This was the original charterof the Virtual Socket Interface Alliance(VSIA). The alliance was formed among a group of interested electronic designautomation vendors and customers. At the time, they viewed an advanced circuitdesign as if it were a PCB with sockets intowhich IP and other design parts would beplugged into. They specified standards existing ones and ones that needed to bedeveloped that would allow the IP andother parts to interface and communicatewith each other. As the industry movedforward, the standards were employed and evolved so that SoCs could become a reality. Eventually, VSIA declared its mis-sion had been accomplished, its standardswere transferred to the IEEE StandardsAssociation and its doors were closed.

Karen BartlesonSynopsys

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Two Prime ExamplesToday there are numerous standards

that benefit IP developers and customers.There are many effective standards andseveral organizations addressing the stan-dardization needs and challenges of IPdevelopment and integration.

A prime example is the standard calledIP-XACT, more formally known as 1685-2009 - IEEE Standard for IP-XACT,Standard Structure for Packaging,Integrating, and Reusing IP within ToolFlows. A second, and quite obvious,example is USB.

IP-XACT was originally developed bythe SPIRIT Consortium (Structure forPackaging, Integrating and Re-using IPwithin Tool-flows). When SPIRIT mergedwith Accellera, a premier standards-settingorganization in the electronic designautomation industry, work on IP-XACTcontinued within Accellera. After ratifica-tion by Accellera, IP-XACT was transferred

to the IEEE Standards Association for formalization under this ANSI-accreditedstandards-development organization.

IP-XACT is an XML schema for des-cribing IP in a way that is language- andvendor-neutral. There are several stan-dard design languages being used for IPdescriptions today: C, C++, Verilog, VHDL,SystemVerilog, SystemC, e, OpenVera andPSL. IP-XACT enables interoperability andreuse of IP by employing XML, which issimply plain text. Interestingly, XML is astandard itself, from the World Wide WebConsortium (W3C), with far-reaching usethroughout the Internet and far beyondthe IP marketplace.

The drivers behind IP-XACT are:improving time to market; needing to manage ever-increasing complexity; andhaving to reduce the cost of developmentand verification for integrated circuitdesign. Time to market is a nice way ofsaying whoever gets there first makes the most money. Think of how complexelectronic products have become mobiledevices, tablets, the Internet of every-thing and its obvious why managingcomplexity is imperative. Reducing costs is another nice way of saying makingmore money. Standards arent always recognized as helping companies makemore money, but its true.

One of the best examples of a hugelysuccessful IP standard is the USB (univer-sal serial bus) interface standard. Imple-mentation of USB in products is visible inpractically every electronic product on themarket today, from smartphones to televi-sions to servers.

The USB standard was developed by a special, nonprofit corporation called theUSB Implementers Forum Inc. Currently,there are almost 700 member companiesin the USB-IF from all around the world.

The USB-IF promotes market adoption,enhancement and compliance of the USBstandard. In order to license the USB logofor use with a product, which indicatesthat the product is compliant with thestandard, the vendor must pass testingrequirements at a USB-IF complianceworkshop or at a certified test lab. Be-cause IP (called silicon building blocks by the USB-IF) is as much a product assomething like a tablet is, the USB-IF callsout and specifies testing requirementsexplicitly for IP.

Not only is the USB-IF concerned withthe standard that is, the USB specifica-tion itself but also with both hardwareand software compatibility. Electricallyspeaking, devices, connectors, hubs andperipherals must work together, the same

way that power outlets do. Software in anoperating system must be leveraged so theOS can be used with a variety of PCs andperipherals. These concerns affect every-one including hardware suppliers, softwaredevelopers and IP creators.

How You Can ParticipateStandards organizations thrive on par-

ticipation from people and companies thatknow the value of standards and want toensure the standards are effective, usable,adopted and maintained. Consumers andsuppliers both play a role in creating goodstandards. In the case of IP standards, itsalso a business-to-business (B2B) involve-ment, as the end-customer the consumer probably doesnt care how standards arecreated or what their technical merits are.

Semiconductor IP Standards: More Important Than You Think CHIP ARCHITECTURE & INTEGRATION

MANUFACTURING: FABS, SYSTEMS & SOFTWAREClick here to return to Table of Contents

In the design and implementation ofmanufacturing control systems, it can besaid that there has been an appreciation forthe need to understand the functionality tobe delivered by those solutions. As contin-ued development of factory automationprogresses to more integrated and holisticfab solutions, however, there is commen-surate need to understand the effect of agiven solution on the overall manufacturingenvironment. Effective development andimplementation of systems and softwaremust therefore understand the larger set of manufacturing performance indicators in truly gauging the impact of any givensolution. The authors of the following twopapers illustrate this need to fully appreci-ate the increasing scope of solution devel-opment and impact.

Ignizio and Garrido discuss the particu-lar impact of variability at the unit processlevel on simulation of fab capacity andcycle time. The inherent challenge present-

Thomas SondermanVice President, Manufacturing Systems Technology; GLOBALFOUNDRIES

ed is in accurately modeling these fab met-rics without a sufficient understanding ofthe magnitude and sources of variability at the unit operation level. This has implica-tions for the modeling methodology itself,but also in the interpretation of the resultsand the subsequent actions to be taken to improve fab capacity and cycle time.

Kabitzsch et al. present discussion fromthe 11th European AEC/APC Conference,and discuss the evolution of this confer-ence into a European Advanced ProcessControl and Manufacturing Conference. As has been evident in the evolving con-ference program, interest in the discussionof APC solutions is extending in scope toevaluate their fuller impact to manufactur-ing. To this end, the authors highlight theexpanded program that includes a Manu-facturing Effectiveness and Productivitysection to more completely discuss thecosts and benefit associated with APCsolutions.

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They simply want the products they buy to work well.

As a designer of integrated circuits andelectronic products that embody IP, youwant to be sure that IP standards are imple-mentable and testable. As a supplier ofdesign automation tools, you know thatstandards must be clearly defined and read-ily supported by your products. The bestway to ensure good standards is to partici-pate in their creation and maintenance.

Standards organizations welcome yourparticipation with open arms. Joining isalmost always a straightforward step.Websites give information about member-ship and any fees that might be required.(Standards development like any product cant happen without funding.) Eachorganization has a set of bylaws and/orpolicies and procedures that you shouldread before joining. Then, bring yourexpertise, enthusiasm and business acu-men to the table, where youll ultimatelybe rewarded with robust standards to propel your industry forward.

About the Author

Karen BartlesonKaren Bartleson is senior director of

Community Marketing at Synopsys, respon-sible for interoperability, standards andsocial media programs. She was electedpresident of the IEEE Standards Associationfor 2013-2014. Karen authored The TenCommandments for Effective Standardsand The Standards Game Blog.


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Semiconductor IP Standards: More Important Than You Think

Manufacturing: Fabs, Systems & Software


Thought Leadership Profile

The days of taking manual measure-ments to obtain data about your semicon-ductor equipment and processes is over.Committed to innovating measurementtechnology, CyberOptics Semiconductoroffers a wireless set of advanced measure-ment solutions for leveling, gapping andteaching semiconductor equipment. Work-ing together or alone, the companysWaferSense technology: Increases fab effectiveness/yield Fine-tunes existing equipment Improves the reproducibility of

already-tight processes Reduces overall cost of operations

A wafer-like form factor allowsWaferSense products to travel like wafersthrough equipment, making for easy installa-tion, minimal machine downtime and accessto difficult locations. WaferSense also linksremotely to a laptop, providing real-timeresults useful to establish standards andconduct meaningful data analysis.

WaferSense Auto Vibration System(AVS): With vibration tied to semiconduc-tor process equipment failure, low yieldsand cycle times, the AVS enables engineersto identify vibration anomalies duringwafer processing by filtering out accept-

able vibration frequencies produced byregular slow-moving equipment or high-frequency noises between 1 to 200 Hz.http://www.cyberopticssemi.com/products/wafersense/avs/

WaferSense Airborne Particle Sensor(APS): This patented particle-sensing technology monitors airborne particles inprocess equipment, reporting informationin real time to allow engineers to efficientlyvalidate and analyze wafer contamination.By reducing the time and expense associ-ated with process equipment particle qual-ification, the APS improves die yield andcompresses final wafer inspection.http://www.cyberopticssemi.com/products/wafersense/aps/

WaferSense Auto Gapping System(AGS): Available in both 300 mm and 200mm form factors, the AGS measures gapscritical to the outcome of semiconductorprocesses such as thin-film deposition, sput-tering and etch. Consisting of three capaci-tive distance sensors, the AGS measures thegaps between shower heads and pedestalsat three points that define a plane to ensureaccurate and reproducible equipment setups. http://www.cyberopticssemi.com/products/wafersense/ags/

WaferSense Auto Teaching System(ATS): Wireless and wafer-like, the ATSmoves through semiconductor equipmentto capture three-dimensional offset data (x, y and z) for accurate calibration oftransfer positions. Because it is vacuumcompatible, ATS can take measurementswhile equipment is sealed, saving you bothqualification time and consumables.http://www.cyberopticssemi.com/products/wafersense/ats/

WaferSense Auto Leveling System(ALS): Leveling semiconductor equipmentcan be a cumbersome task, taking severalhours to complete, which causes equip-ment downtime and loss of revenue.Compared to traditional wired or manualmethods, the WaferSense ALS can signifi-cantly reduce the time it takes to com-plete this task, as the user is not requiredto break down equipment or defeat a vacuum chamber. http://www.cyberopticssemi.com/ products/wafersense/als2/

To see how the WaferSense productsfit into your processes, click here or contact the company [email protected] or 800.366.9131.

Mark HannafordDirector of Sales

Business ContactLindsey DietzInside Sales and Marketing Phone 503.495.22171.800.366.9131Fax [email protected]

CyberOptics Semiconductor, Inc.9130 SW Pioneer Ct., Ste. DWilsonville, OR 970701.503.495.2200www.CyberOpticsSemi.comCSsales@CyberOptics.com

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E-MAILthis articleAutomated Measurement Devices Measure

Critical Parameters in SemiconductorFabrication Processes/Equipment



MANUFACTURING: FABS, SYSTEMS & SOFTWARE MANUFACTURING: FABS, SYSTEMS & SOFTWARE

Abstract Manufacturers, suppliers and the scien-

tific communities of semiconductor, photo-voltaic, LED, flat panel, MEMS and otherrelevant industries are invited to the 12thEuropean Advanced Process Control andManufacturing conference, taking place atMINATEC Grenoble on April 16-18, 2012.

Beyond the established topics of equip-ment and process control on unit pro-cess and fab level, the new agenda alsoincludes current challenges and futureneeds of manufacturing effectiveness.

Contributions of the 11thEuropean AEC/APC Conference at a Glance

The 11th European Advanced EquipmentControl/Advanced Process Control confer-ence took place in Dresden, Germany, April4-6, 2011. More than 160 attendees listenedto 10 keynotes and invited talks, 29 oralpresentations, 22 posters and two tutorials.Organizers managed a sophisticated trade-off between an expanded area of topicsand the need for detailed scientificexchange. Two parallel sessions on unitprocess and factory-level control enabled

an emphasis on methodologies and ITinfrastructure.

The conference last year highlightednew APC strategies, including less reactiveand more predictive approaches at thefactory level, as well as new ideas princi-pally based on increased process under-standing for process control at the unitprocess level. Enhanced equipment qualityassurance (EEQA) as a new approach isnow within the scope of APC: Its major target is to increase productivity and manufacturability by focusing on equip-ment characterization. Process control inLED manufacturing was shown to be anew and fast-growing APC applicationsarea. General trends were also discussed,as a number of contributions dealt with higher APC effectiveness throughincreased process understanding.

The program was well balancedbetween the traditional APC approacheson the one hand, and new needs, prob-lems and methodologies on the other, e.g., talks on fab logistics and perform-ance (A. Gellrich).

The session on plasma processes (seventalks) comprised different approaches for

Advanced Process ControlGoes Manufacturing: APCMConference in Europe

understanding plasma instabilities in orderto avoid yield loss in manufacturing (N.Urbansky), and advanced plasma diagnos-tics that will be required in the future forrobust plasma process models, e.g., for virtual metrology (VM). An important contribution from the session on thermalprocesses and implant (three talks) was asystematic comparison of control methodsat the equipment level (D. de Roover).Another interesting example in the metrol-ogy session (four talks) was a study ofoptimal metrology sampling strategies (A. Subramanian). Other sessions weredevoted to lithography (two talks) andAPC applications (two talks).

A second part of the talks dealt withfab-level requirements and methodologies,IT infrastructure, etc. The session on dataanalysis, modeling and visualization (seventalks) covered a wide range of topics, fromanomaly detection in time-series data (J. DAmour) to model stability in adaptiveVM (A. Dementjev). A session on IT infra-structure (four talks) included talks on veryfast databases (W. Benn) to new standard-ization approaches for sensor interfaces in manufacturing (D. Suchland).

APC Embraces ManufacturabilityA number of high-quality keynotes and

invited talks focused on more strategic

Klaus Kabitzsch,1 Michael Klick,2 Andreas Steinbach,3 Alan Weber41Dresden University of Technology 2Plasmetrex GmbH 3Von Ardenne Anlagentechnik GmbH 4Alan Weber & Associates

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1 2 3 4 5 6 7

Many similarities tosemiconductor manufacturingin both front-end and back-endprocessing

Assessment of Value

Encapsulate

DriverInstall

Thermal Mgmt/Heat Sink

Soldering

Phosphor

Optics

DieMounting

WireBonding

Binning/Packing

Sorting/Inspect

Probing

Scribing/Dicing

ReflectiveCoating

LaserLiftoff

Lapping

Passivation

Metalization

Etch

Litho/Aligner

Metrology

Lower tech challenge, Min. US Participation

High tech challenge, No US Leadership

High tech challenge, US Leadership

ActiveLayer

Base/BufferLayer

Score/Test

PolishWafer

SliceWafer

GrowIngot

Substrate/Wafering

EpitaxialDeposition

WaferFabrication

DieFabrication

Packaging,Optics,Submount

Source,Drivers,Control

Systems andFixtures

End mkt.specific

Other

Signage

Mobile

Auto

Sign/Display

Illumination

Figure 1. Analyzing the Problem: LED Value Chain


objectives, future trends and visionary ideas.Semiconductor manufacturing is a verycomplex process chain, so the approach forunderstanding and control of these process-es must be deeply interdisciplinary.

In contrast to the traditional heuristicapproaches, future-unit process-levelAPC systems will take into account thespecific properties of the process. Thisrequires robust and simple process mod-els based on process understanding,including models of the equipment andits key components. These reflect theimportant properties of the process andenable a first-level data selection andcompression with completely differentmodels and parameters from litho toPECVD or CMP.

APC at the fab level will continue to use effective standard algorithms, includ-ing data projection methods such as PCA.Here the effectiveness is much higherwhen it is based on validated, pre-processed data from process-level APC.

Equipment models are the core part ofISMIs EEQA program, and consequently,were also the main focus of this confer-ence, beginning with the tutorials dealingwith general and RF equipment models. Intwo of the invited talks, this was discussedin the context of equipment health moni-toring (invited talk, G. Crispieri, keynoteAlan Weber), and finally referenced as oneof the future trends in APC methodologyrelated to updates of the ITRS (J. Moyne).Here a better and more detailed under-

standing of equipment properties is thetarget for increase in productivity, whilealso directly addressing the issues ofchamber matching and improvement offab ramp-up.

For APC at the fab level, deeper under-standing of yield dependencies will be thecore area over the next few years. We haveto consider not only the static behavior ofequipment or process models, focusing onmethods like correlation or PCA; dynamicbehavior becomes even more important inthe coming years. This will enable a betterview of the future behavior of equipmentand the entire fab. As a result, accurateprediction of yield, equipment states andmaintenance needs will be more feasible.

For both unit process and fab-level sys-tems, feedback control should not alwaysbe the dominant choice. Model-basedfeed-forward control will become muchmore important in the next years, in com-bination with better prediction capabilitiesacross different time horizons (less reac-tive, more predictive). However, this willrequire far better process models (staticand dynamic) than we have today, becausefeed-forward control also opens the doorsto optimization-based control systems.

APC in LED ManufacturingThis year, LED manufacturing was the

hot topic in new APC applications. Twotalks discussed this application area fromthe supplier (J. Moyne, Applied Materials)and user (H. Zull, OSRAM) points of view.Both talks have shown very impressivelythat APC methodology must always fit theprocess chain and address the economicrequirements for cost saving, which is driven mainly by the LED manufacturers.Solutions at the unit process level wellestablished in silicon wafer manufacturing cannot be transferred without adapt-

ation. This holds true for APC both at theunit process and fab levels.

Benefit Calculation of APC Projects

One of the more interactive sessionswas a lively panel discussion on APC ROI(return on investment). The panel includedseasoned participants from across thevalue chain, including device makers,equipment suppliers and APC softwaresuppliers. This breadth of coverageensured that none of the factors in the ROI formula would be discounted, under-scoring the principle that for an implemen-tation project to be viable, the benefitmust accrue to all the stakeholders.

Some of the key insights include: 1) ROI for many projects is not empha-sized, because APC investments are nowconsidered strategically vital, and nolonger an optional technology; however,ROI can still be useful for ranking potentialprocess/productivity improvement projectsafter a fab is running; 2) FDC can be welljustified during fab ramp-up in addition to full production, because the earlier the equipment is characterized, the morequickly the processes can be stabilizedand qualified; 3) too often we forget themanpower savings in ROI calculations,since we assume the avoidance of scrapwafers is the largest benefit; but when youhave limited staff, the opportunity cost oftying up a process or equipment engineeron a problem that could have been avoid-ed with an FDC or preventive maintenancesolution can be significant; and 4) fabs arestarting to recognize and consider thehidden cost of internal solutions whenmaking buy vs. build decisions for APCsoftware; while this is welcome news forcommercial software suppliers, there arentthat many left to hear it.

Advanced Process Control Goes Manufacturing: APCM Conference in Europe MANUFACTURING: FABS, SYSTEMS & SOFTWARE

Figure 2. Near-Future CIM and APC Infrastructure Courtesy of Applied Materials, Inc., all rights reserved


12th European APCM ConferenceThe 12th European Advanced Process

Control and Manufacturing conference willtake place at MINATEC Grenoble on April16-18 this year. Beyond the established top-ics of equipment and process control onunit process and fab level, the new agendaalso includes current challenges and fu-ture needs of manufacturing effectiveness.About 80 oral presentations and posters of topics such as semiconductor, photo-voltaic, LED, flat panel, MEMS and otherrelevant industries are expected.

1. Advanced Process Control on UnitProcess Level APC applications at unit processes Unit process control methods Tool and sensor data analysis Maintenance & tool optimization Enhanced equipment quality assur-

ance (EEQA)2. Advanced Process Control on Fab Level

Fab-level process control methods Virtual metrology Yield management Factory data analysis IT infrastructure

3. Manufacturing Effectiveness andProductivity Unit process & equipment productivity Factory productivity and automation Factory modeling, simulation and

optimization Cost optimization and end-of-life

equipment issues Environment and green manufacturing

The keynote of Jeremy Read (vice presi-dent, Applied Materials) will focus on predic-tion as the future enabler for quality man-agement across the semiconductor manu-facturing application space. In this talk, acohesive manufacturing automation predic-

tion infrastructure and strategy will be pre-sented. Key elements of that strategy includ-ing predictive maintenance, virtual metrolo-gy (sensor fusion), predictive scheduling andpredictive yield will be highlighted in termsof what these technologies can offer andwhat we have achieved with them to date.The potential impact of these technologiestoday and in the future in areas such as qual-ity management and process control forspecific applications (e.g., automotive) willbe explored, as well as challenges in imple-mentation such as the culture change asso-ciated with getting the necessary algorith-mic solutions accepted on the factory floorin order to move from a reactive to predic-tive paradigm. Further, an ultimate vision willbe presented of the future factory environ-ment with intra- and inter- factory predictionsystems in place enabling this new predictiveparadigm in manufacturing.

The increasing role of APC in the ITRS,and challenges, opportunities and syner-gies of 450 mm wafers are further keyaspects of the upcoming conference.

Traditionally, this conference has alsoalways been a platform of training and edu-cation. As in 2011, there will be again twotutorials; the first one will focus on dataanalysis, multi-dimensional visualization andgeometric process control, demonstratingparallel coordinates and the synergistic tech-nologies of multi-dimensional visualizationand geometric process control they havespawned in the solution of ostensibly com-plex problems drawn from a spectrum ofengineering (as well as other) disciplines.

The second tutorial deals with APC and corrective, preventive and then predic-tive maintenance; and how maintenancemethodology, supported by advancedprocess control, opens new equipmentengineering and manufacturing opportun-ities for cycle time, cost and yield.

Beyond the industry exhibition, theEuropean APCM conference offers an excel-lent opportunity for user group meetings,which are organized by the companies them-selves, in coordination with the conference.

For further information, please seewww.apcm-europe.org.

Endnote1. N. Patibandla et al. DOE SSL

Manufacturing R&D Workshop; April 2010

About the Authors

Klaus KabitzschKlaus Kabitzsch received his diploma

and a Ph.D. (1982) in electrical engineeringand communications technology. He sub-sequently worked in the industry in thearea of control of machines and equip-ment. After 1989, Dr. Kabitzsch worked atthe universities of Leipzig and Dresden andfocused his research on sensor networks,distributed systems, real-time software and automation. He became professor and head of the department of TechnicalComputer Sciences in 1993 at the DresdenUniversity of Technology. Dr. Kabitzschscurrent projects focus on the automationdomain, component-based softwaredesign, design tools for networkedautomation, energy and quality manage-ment, data analysis, advanced processcontrol and predictive technologies.

Michael KlickMichael Klick is CEO of the Plasmetrex

GmbH, a plasma process control solutionprovider. He received his diploma in tech-nology of electronic devices in 1987 and his Ph.D. in plasma physics from Ernst-

Moritz-Arndt-University Greifswald in 1992.Dr. Klick has over 15 years experience innonlinear modeling of industrial RF plasmasand development of plasma sensor systemsfor etch and deposition in semiconductorand PV manufacturing. He holds severalpatents in this area. Dr. Klick has beenworking on the qualification of process and maintenance personnel since 2003,and gives regular lessons for studentsabout industrial plasma technology at theRuhr-University Bochum. Assessment, mod-eling, and RF and plasma chamber match-ing for plasma tools in manufacturing arehis current key activities.

Andreas SteinbachAndreas Steinbach is working on

process development at Von ArdenneAnlagentechnik GmbH, a worldwide lead-ing manufacturer of equipment for indus-trial vacuum processes of plasma and elec-tron beam technologies. He received hisdiploma for physics in 1983 and his Ph.D. in physics from Dresden University ofTechnology in 1990. Dr. Steinbach has over25 years experience in industrial plasmaprocesses for etch and deposition in semi-conductor and thin film manufacturing,and holds several patents in this area.Since 1998, he has been working on pro-cess control in semiconductor and thin filmtechnology. From the beginning in 2000,Dr. Steinbach was one of the leading headsorganizing the European Advanced Pro-cess Control and Manufacturing Confer-ence.

Alan Weber See bio on page 7.


Advanced Process Control Goes Manufacturing: APCM Conference in Europe MANUFACTURING: FABS, SYSTEMS & SOFTWARE

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MANUFACTURING: FABS, SYSTEMS & SOFTWARE MANUFACTURING: FABS, SYSTEMS & SOFTWARE

AbstractSimulation, specifically discrete event

simulation, is widely employed throughoutthe manufacturing sector particularly insemiconductor and photovoltaic fabs forprediction and assessment of factory per-formance. Of special interest is fab cycletime and capacity. Whether it be a pro-posed, ramping or mature fab, it is vital tohave accurate estimates of facility perform-ance. Conventional wisdom among simula-tion personnel is that once a detailed fabsimulation model has been developed themodel should be run for a period of one topossibly two years of simulated time so asto reach the steady state performance ofthe simulated fab. This process is repeateda number of times and the average of theresults are employed in the decision-mak-ing process (e.g., should more or fewertools be used?). Again, conventional wis-dom holds that such a process is sufficientto establish accurate estimates of fab per-formance. That assumption is challenged in this paper.

IntroductionDecision-making depends upon pred-

ictions. Some predictions are subjective,based on little more than guesses. Others

are developed through a more analyticalprocess. Whether subjective or analytical,predictions are made on the assumptionthat a given future event, condition or per-formance metric is indeed predictable. Aswill be discussed, however, the validity ofany prediction depends in large part on knowing what we dont know. Morespecifically, it is vital to know the sourceand amount of variability existing withineach segment of the fab.

In the semiconductor and photovoltaic(PV) industries, predictions are made atboth the macro level (e.g., future state ofthe economy, competition, demand for anew product and cost of silicon) and microlevel (e.g., predicted plant capacity, yieldand cycle time). In this paper, our focuswill be at the micro level; i.e., predictions of fab performance.

Consider a fab, either operational or to be built. Two performance metrics oneshould want to predict are fab capacity(e.g., maximum sustainable wafer flowrate) and fab cycle time (i.e., time betweenentry of a job into the fab and its depar-ture). Under the assumption that our pre-dictions are accurate, decisions such as thecapacity of each workstation (a.k.a., toolset) may be made. Poor predictions, how-

Fab Simulation and Variability

ever, may lead to either insufficient orexcess capacity. The cost of either error issignificant.

Methods for Performance Prediction

The three most common approaches forprediction of production line performanceare via spreadsheets, queuing models, andsimulation. Spreadsheets ignore variabili-ty, as well as the complex interactionsbetween workstations, and despite theirpopularity this quick and dirty approachto prediction poses a significant risk.

Queuing models do consider variabilityand, to a limited degree, workstation inter-actions. They have, however, two signifi-cant limitations. First, they only deliver predictions of the steady state of the facil-ity while ignoring the ups and downs

encountered prior to reaching that state.Second, while queuing models have beenconstructed for small factories or seg-ments of larger facilities, their develop-ment for something as massive and com-plex as a semiconductor fab would requirea heroic effort (and one would still be leftwith just a prediction of the facilityssteady state).

Most, if not all, semiconductor and pho-tovoltaic firms employ simulation modelswhen attempting to predict fab perform-ance. The outputs of the simulation of adetailed model of a fab provide forecaststhat are commonly accepted and actedupon. The four most widely acknowledgeddrawbacks of simulation, however, are: thetime and effort required to construct amodel; time and effort devoted to careand feeding of the model; time and effort

James P. Ignizio,1 Hernando Garrido21The Institute for Resource Management2Fresenius Medical Care

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WS-A WS-B WS-C WS-D WS-E WS-F

WS-G WS-H WS-I WS-J WS-K WS-L

Figure 1. The 12-Workstation Factory


necessary to collect supporting data; andthe extensive amount of training and prac-tice required to gain a reasonable degreeof proficiency in the art and science ofsimulation.

Based on our (real-world) experience, it may take a year or more just to con-struct a valid fab simulation model beforebeing able to conduct the experimentsnecessary to support fab performance pre-diction. As mentioned, conventional wis-dom throughout the semiconductor andPV industry holds that one should run themodel for one or two years of simulatedtime in order to reach steady state. Justone single simulation run, however, mayrequire a day or more to conduct. And onerun is hardly enough to obtain predictionswith any degree of confidence.

Because of the amount of time con-sumed by each simulation, firms may (andoften do) rely on the output of relatively

few experiments. They assume this is suffi-cient to obtain accurate predictions of fabperformance at steady state. This is anassumption the author disputes whetherone is dealing with a massive, complex fab or even a much simpler, much smallerfactory devoted to the production of lesscomplex products as shall now be illus-trated.

Illustration: The 12-WorkstationFactory

For purposes of illustration, consider an exceptionally simple factory consistingof just 12 workstations wherein: The facility services a single product,

flowing through the factory at a con-stant rate of 20 jobs per day.

There is zero transit time betweenworkstations, no rework and no re-entrancy.

This factory is depicted in Figure 1. Eachellipse represents a workstation and eachrectangle within an ellipse is a machine.Thus, in WS-A (i.e., workstation A) thereare six machines. If we believe that simu-lation delivers accurate predictions of fabperformance, then it should certainly pro-vide accurate predictions of the perform-ance of this tiny facility.

Table 1 lists a portion of the data for this factory. As may be seen, it containsthree constraints (workstations D, H and K each with utilizations of 98 percent).[Readers who wish to examine the com-plete data set, as well as actually run thisfactory via a queuing model, may do so at www.mhprofessional.com/ignizio.]

Assume we wish to predict average jobcycle time (a particularly important meas-ure). Since this factory is so small and sim-ple, a queuing model (e.g., the one referredto in the URL previously cited) may be

used to predict cycle time at steady state.The result for this facility is 90.42 days.Shouldnt we then expect a detailed simu-lation model of the same factory to reachessentially the same results if run for asufficient amount of simulated time?

Since simulation models of semicon-ductor fabs are run for one or two years of simulated time, it would follow that, ifconventional wisdom is indeed valid, thisshould be more than enough for ourexceedingly simple 12-workstation factoryto reach its steady state. To determine this,a detailed discrete event simulation modelof the 12-workstation factory was con-structed using the ExtendSim simulationplatform.

Simulation PlotsThe plot of Figure 2 provides a small, but

representative sample of the numerous runsmade. The horizontal axis represents simu-lated days (from 1 to 730 days) and the ver-

tical axis is the cycle time in days. The pre-dicted cycle time after two simulated yearsranges from 35 to 64 days nowhere nearthe true steady state value of 90.42 days.Stated another way, even after two years ofsimulated time, the factory has yet to reachsteady state (and, in fact, will not do soeven after 10 simulated years).

The primary rea

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