Functionality of AFTER+ chip applications & requirements

P. Baron CEA IRFU/SEDI/LDEF ACTAR WORKSHOP Bordeaux (CENBG) June 17, 2008 1

Functionality of AFTER+ chipFunctionality of AFTER+ chipapplications & requirementsapplications & requirements

At this time, AFTER+ must fit the specifications of:

•ACTAR/GANIL•TPC/GLAD/R3B/FAIR•TPC&ACTIVE TARGET/MSU•TPC/CENBG•SAMURAI TPC/RIKEN•…

2ACTAR WORKSHOP Bordeaux (CENBG) June 17, 2008

AFTER+: AFTER+: ArchitectureArchitecture

Main features for AFTER+:Main features for AFTER+:•72 Analog Channels; Slow Control & test [“spy” mode].72 Analog Channels; Slow Control & test [“spy” mode].

Main features for the channelMain features for the channel•Input Current Polarity:Input Current Polarity: positive positive oror negative. negative.•CSA + PZC + FilterCSA + PZC + Filter (semi-Gaussian order 2). (semi-Gaussian order 2).

[Possibility to bypass the CSA].[Possibility to bypass the CSA].•SCA:SCA: 511 analog memory cells. 511 analog memory cells. •Auto Triggering:Auto Triggering: discriminator + threshold (DAC) + inhibition. discriminator + threshold (DAC) + inhibition.

Main features for the readoutMain features for the readout•Analog OR of the 72 discriminator outputs [1 current output].Analog OR of the 72 discriminator outputs [1 current output].•Address of the hit channel (through slow control link).Address of the hit channel (through slow control link).•4 SCA readout modes.4 SCA readout modes.

[AD9229][AD9229]

AFTER+

511 cells

SCAFILTER

tpeak

CSA

1 channel

x72in

76 to 1

Charge range

Σ 72 discriminator outputs

DACDiscri

inhibit

BUFFER

Reset[hit channel registers]

Serial Interface Mode CKw & CKr

In Test CSA;CR;SCAin (N°1)

Asic “Spy” Mode

Readout

Mode

SCA MANAGERSLOW CONTROLW / R CK

TEST Power on

Reset

[+ indisc]

hit channel registers

12-BitADC

•Slow ControlSlow Control

•Power on resetPower on reset

•Test mode: Test mode:

calibration or testcalibration or test [channel/channel][channel/channel]

functionalfunctional [72 channels in one step][72 channels in one step]

•Spy mode on channel 1: Spy mode on channel 1:

CSACSAoutout, PZC, PZCoutout, FILTER, FILTERoutout or or DISCRIDISCRIin.in.


AFTER+: AFTER+: Mode of operationMode of operation

Discri_inDiscri_in

Discri_outDiscri_out

Hit_channelHit_channel

Trigger_outTrigger_out

Write_SCAWrite_SCARead_Address_hit channelRead_Address_hit channel

ResetReset

Read_SCARead_SCA

Data_SCA_outData_SCA_out

SCA_inSCA_in

Channel iChannel i

Stop Sampling:Stop Sampling: on external or local Triggeron external or local Trigger

SCA writeSCA write address readaddress read SCA readSCA read SCA writeSCA write

AFTER+

SCAFILTER

CSA

1 channel

x72

in

76 to 1

SCA MANAGERSLOW CONTROL Write Read TEST

DAC Discriinhibit

BUFFER

Trigger_out

Asic management (local or global)Asic management (local or global)

SCA read: READ & CKread

SCA write: Write & CKwrite

Slow control: Din, Dout, CK, CS

Test: DAC

ADC control & Data

Trigger control: multiplicity & detection

Reset: hit_channel register Reset

12-BitADC

DAC

CSA_inCSA_in


AFTER+: AFTER+: SCA SCA

SCA Manager

SCA write

76

lin

es

511 cells

SCA read

Clk write Clk read R Vreturn:0,7V

In B

uff

ero

ut

W

Analog Memory: Analog Memory:

7272 channels + channels + 44 dummy channels dummy channels [for common mode or Fix pattern [for common mode or Fix pattern noise rejection purpose].noise rejection purpose].

•Write: Write: 1MHz to 100MHz1MHz to 100MHz•Read: Read: 20MHz 20MHz •Dynamic:Dynamic: 1.5V (full range) 1.5V (full range) •Clock:Clock: LVDS LVDS •Mode (W & R):Mode (W & R): CMOS CMOS

CLKwrite

CLKread

Write

Read

Write phase Write phaseRead phase


AFTER+: AFTER+: SCA Write PhaseSCA Write Phase

•Fsampling: Fsampling: 1MHz to 100MHz.1MHz to 100MHz.•Peaking Time: Peaking Time: 50ns to 1µs (16 values). 50ns to 1µs (16 values).

511 cells

SCAFILTER

tpeak

CSA

channel

Cf

DACDiscri

PAD

x

y

z

particleparticle

z0z1

Tz=z0

ttri

gg

er

Tz=z1

ttrigger – tz=z0 ≤ 511 /Fsamplingt0

= a

rriv

al t

ime

TimezmaxLdriftpad

Tz=zmax

tdriftzmax

tdriftz1

tdriftz0

c0c510

c509

ci-2c1 c.

cici-1

ci+

1ci

+2

• Architecture : circular memory

• Sampling condition : 511x(1/Fsampling) ≥ Tdriftmax

• Peaking Time : Tpeak ≥ N x (1/Fsampling)


c0c51

0c

509

ci-

2

c1

c.

cici-

1

ci+

1c

i+2

c0c51

0c

509

ci-

2

c1

c.

cici-

1

ci+

1c

i+2

AFTER+: AFTER+: SCA Read PhaseSCA Read Phase• Channel Readout mode : all channels; hit channels or specific channels

Read_SCARead_SCA

CKR_SCACKR_SCA

Data_SCA_outData_SCA_out

9xTrck 9xTrck 61xTrck

Address of the last Column read

Column n+510 address Vlow

Vreset

Column n

3xTrck 76xTrck

C0 C1 C75Vreset

3xTrck 76xTrck

C0 C1 C75

509x3xTrck+ 509x76xTrck

C0 C1 C75 Vlow

Column n+1 lumn n+510

Readout Time:Readout Time: 511511xx [ [n n channelchannel + 3] + 3]xxTrckTrck + 79 + 79xxTrckTrck = 80.6 µs + 25.55 µs = 80.6 µs + 25.55 µsxxnnchannel channel [[TrckTrck = 50 ns] = 50 ns]

. . nn = 1 channel => Readout time = 106.15 µs. = 1 channel => Readout time = 106.15 µs.

. . nn = 10 channels => Readout time = 336.1 µs. = 10 channels => Readout time = 336.1 µs.

. . nn = 36 channels => Readout time = 1 ms. = 36 channels => Readout time = 1 ms.

. . nn = 76 channels => Readout time = 2.022 ms. = 76 channels => Readout time = 2.022 ms.

c0c51

0c

509

ci-

2

c1

c.

cici-

1

ci+

1c

i+2

c0c51

0c

509

ci-

2

c1

c.

cici-

1

ci+

1c

i+2

Column nColumn n

Channel 0Channel 0

Channel 2Channel 2

Channel nChannel n

Channel 75Channel 75


AFTER+: AFTER+: SCA Read PhaseSCA Read Phase• Hit or specific channels: Slow control serial link & hit channel register (72 bits)

Readout of the Readout of the hit channel addresshit channel address

idle

X 1 ADD<6:0> XXXXX

Address <71 :0>

r/wb=1=> read

Y idle

Sc_dinSc_din

Sc_ckSc_ck

Sc_enSc_en

Sc_doutSc_dout

8.5xTck:8.5xTck:425ns425ns 72xTck:72xTck:3.6µs3.6µs

Write_SCAWrite_SCARead_address_hit channelRead_address_hit channel

ClearClearRead_SCARead_SCA

Write_address_read channelWrite_address_read channel

idle

X 0 ADD<6:0> Address Data <71 :0>

r/wb=0=> write

idle

Sc_dinSc_din

Sc_ckSc_ck

Sc_enSc_en

Sc_doutSc_dout

7.5xTck:375ns7.5xTck:375ns 72xTck:3.6µs72xTck:3.6µs

XXXXX

Write of the readout Write of the readout channel addresschannel address


AFTER+: AFTER+: SCA Read PhaseSCA Read Phase• SCA readout mode: 511, 256 or 128 analog memory cells / channel

Write phase:Tdrift ≤ 511 / FsamplingRead phase:SCAcells = 511

0510

Stop(trigger)

Readout phase

Write phase:2 x Tdrift ≤ 511 / FsamplingRead phase:SCAcells = 256

0510

Stop(trigger)

Readout phase

Write phase:4 x Tdrift ≤ 511 / FsamplingRead phase:SCAcells = 128

0510

Stop(trigger)

Readout phase

•511 analog memory cells / channel: 511 analog memory cells / channel:

cici+1

ci



InternalInternalLogicalLogicalOperationOperation

Write phase

Write phase

Write phase


4-bit DAC

AFTER+: AFTER+: Threshold channelThreshold channel• Architecture: L.E.D + DAC (4 bits/channel + 3 bits/72 channels)

FILTERAnalog outCS

A

1 channel

Discri

PZC

G2

+

-Sign

Polarity

Memory Hit Channel

511 cells

SCA

Inhibit

Gain

OR_hit channelOR_hit channel

Iin I=Iin

Hit channel 01

Iin I=Iin

Hit channel 02

Iin I=Iin

Hit channel i

Iin I=Iin

Hit channel 72

72 x72 x IIinin

Slow Control Register(2 bits)

Iin

3-bit DAC

• Trigger output: analog OR of the 72 hit channel registers.

Need specifications:Need specifications:- Current value- Rise & Fall time- Rout&Cout- Linearity (72*Iin ??)


AFTER+: AFTER+: Architecture of the test systemArchitecture of the test system• 3 test modes: Test, Functionality & Calibration

•Calibration: Charge injected channel by channel (selection 1/72 channel by Slow Control).

selj

seli

x72Pulse Generator

ASIC

•Functionality of the global electronic system: Charge injected on all channels (or a part), at the same time.

[in this mode, the FPN channels can be tested]

Pulse Generator selj

seli

x76

ASIC

•Test: Charge injected channel by channel (selection 1/72 channel by Slow Control).

[1 internal injection capacitor/charge range]

selj

seli

x72Pulse Generator

ASIC

X3(1/Charge range)

Ccali


AFTER+: AFTER+: RequirementsRequirementsParameter Value

Polarity of detector signal Negative or PositiveNumber of channels 72External Preamplifier Yes; access to the filter or SCA inputsCharge measurementInput dynamic range 120 fC; 1 pC; 10 pCGain Adjustable/(channel) Output dynamic range 2V p-pI.N.L < 2% Resolution < 850 e- (Charge range: 120fC; Peaking Time: 200ns; Cinchannel. < 30pF)SamplingPeaking time value 50 ns to 1 µs (16 values)Number of SCA Time bins 511Sampling Frequency 1 MHz to 100 MHz Time resolutionJitter 60 ps rmsSkew < 700 ps rmsTriggerDiscriminator solution L.E.DTrigger Output/Multiplicity OR of the 72 hit channel registers; Current outputDynamic range 5% of input charge rangeI.N.L < 5%Threshold value 4-bit DAC/channel + (3-bit + polarity bit) common DACMinimum threshold value ≥ noiseReadoutReadout frequency 20 MHz to 25 MHzChannel Readout mode Hit channel; specific channels; all channelsSCA Readout mode 511 cells; 256 cells; 128 cellsTestcalibration 1 channel / 72; external test capacitortest 1 channel / 72; internal test capacitor (1/charge range)functional 1, few or 76 channels; internal test capacitor/channelCounting rate < 1 kHzPower consumption < 10 mW / channel

Functionality of AFTER+ chip applications & requirements

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