Functional Test of Small-Delay Faults using SAT and Craig Interpolation

Presenter: Chien-Yen Kuo

ATPG for small delay fault

• Small delay fault– Assumed to be at the output of a logic gate– Small enough to be detected only with sufficiently

long sensitizable path(cf. gross-delay fault)• Aim to generate test sequences for these

faults in sequential circuit – SATSEQ

SAT-based bounded model checking

• To see if a property is reachable from initial state in a circuit

• Encode circuit and in propositional formula

• From , solve – SAT, is reached in step from – UNSAT, incrementally increase

Fixed point

• For FSM of circuit, reachable states eventually stops growing at fixed point in Boolean space– Once stops, report as unreachable from

• However, the necessary may be very large– Exponentially grows with #FF in worst case

• Here, Craig interpolation is applied to speedup the growing

Craig interpolation

• Let , be two propositional formulas, and is UNSAT

• There is a formula (interpolation) such that

Model checking flow

• Let be the interpolation of – and , if is UNSAT– and , if their conjunction is UNSAT

MC-instance

• Introduced for applying model checking to ATPG

Sequence for one fault

• Consist of 3 sub-sequences

Initial state

• Two candidates– Synchronized state, if exist, or – Restart state (all-0 state)

• Synchronized sequence – Sends any state to one and the same state

(synchronized state)1

0

0

101

Two-pattern delay test

• To sensitize PO or FF to fault– Pattern 1: Control initial value at fault site– Pattern 2: Control final value and propagate fault

• Different in at least one PO or FF

Longest sensitizable path

• Sensitizable path that sums to maximal delay• Let SAT iff a sensitizable path through gate with

length no less then exists• Model checking– To make sure start state of test pair is reachable– : initial state– Lift literals in , say

• • Final state = start state of

Invalidation and immunity

• Unexpected fault propagation may invalidate the test– F-invalidation– I-invalidation– P-invalidation– I- and P-invalidation can be ruled out by

sufficiently long clock period if no gross-delay fault• To avoid F-invalidation (F-immune)– Enforce X (unknown) on all off-path sensitized FF

Fault propagation

• Applied only when the sensitized path ends on FF

• Define variables and for each circuit line – Fault-free and faulty– ends with rising transition , – ends with falling transition ,

Fault propagation

• If no immunity is applied, assume only one FF is sensitized

• Model checking – : ending state of two-pattern delay test– Identical and at PI in every time frame– : different and in at least one PO only in last time

frame

Sequence connection

• Connect ending state of last test to beginning state of next test

• Also, initialize two-pattern delay test• Asymmetric travelling salesman problem – MC-instances for building distances – : number of test sequences

Sequence connection

• Greedy nearest neighbor – : ending state of last test sequence– : disjunction of reachability of start states of

unconnected sequences – If no unconnected sequence is reachable, restart to

initial state • For tests start from initial state– No over-testing– If no sub-sequence to detect fault, the fault cannot

manifest itself during operation

Experimental result

Conclusions

• SATSEQ, a non-scan ATPG tool for detecting small delay fault in sequential circuit– Less test length compared to scan TAT– Fully deterministic, guarantee to produce shortest

possible sub-sequences