Fujitsu - Seemless Integration of IP Cores into System LSI - IP & Cores
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Transcript of Fujitsu - Seemless Integration of IP Cores into System LSI - IP & Cores
5/10/2018 Fujitsu - Seemless Integration of IP Cores into System LSI - IP & Cores - slidepdf....
http://slidepdf.com/reader/full/fujitsu-seemless-integration-of-ip-cores-into-system-lsi-i
Seemless Integration
of IP Cores intoSystem LSI
Page 1 of 4
Fujitsu’s SoC design methodology and solution platform provides seamless integration of IP cores into
system LSI. The IP library consists of diverse sets of re-usable system building blocks
Fujitsu Semiconductor Europe
FactsheetIP & Cores
As a leading global ASIC provider and total-
solutions provider, Fujitsu delivers innovative
solutions that enable customers to
differentiate their products and maximise their
time-to-market advantage. Together with
skilled engineers, this has created the
established environment required to developand produce advanced ASIC designs.
Fujitsu Semiconductor Europe operates its ASIC
Design Centres from Langen (Frankfurt) and
Munich, Germany and is supported by design
centres for ASIC and foundry services
throughout the world. Support can therefore
be delivered locally, which is increasingly
important in today’s complex ASIC designs.
By using third-party vendor tools and Fujitsu's
own CAD tools, we ensure an innovative,
mature design flow, providing customers at the
same time with a global network for system
development and support.
Fujitsu’s advanced technologies and products
include high-end deep sub-micron process
(40nm, 65nm, 90nm, 0.13µm, 0.18µm) and
standard process technology (0.25µm,
0.35µm). Embedded memory with access time
in the pico-second range helps to deliver the
system performance required for today’s SoC
designs.
The Fujitsu IP portfolio, in combination withour experienced application support, enables
customers to achieve right-first-time design
and shorter design cycle times.
Sample IP cores include:I Computational cores: ARM®, DSP,
multi-channel VoIPI Memory controller: SRAM controller,
DRAM controller, DDR controllerI Connectivity IPs: USB, PCI, I2C,
Ethernet, IEEE 1394
Packaging support options range from small
FBGA/QFP to high pin-count, enhanced-
performance FCBGA solutions.
Mobile PC
Industrial Automotive
28-nm
1000
100
10
G a t e L e n g t h ( n m )
Year
1999 2001 2003 2005 2007 2009 2011 2013
180-nm
130-nm
90-nm
65-nm40-nm
FSL Fab(Fujitsu Semiconductor Ltd.)
Outsourced Fab
(CS80A)
(CS90A)
(CS100A)
(CS200A)
(CS350LP)
(CS450LP) 22-nm(CS500LP)
CMOS technology roadmap
5/10/2018 Fujitsu - Seemless Integration of IP Cores into System LSI - IP & Cores - slidepdf....
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Factsheet Fujitsu IP & Cores
Page 2 of 4
90nmI Standard Cells
- Multiple Vth
I Memory
- SRAM 1RW, 2RW
- RF 1R1W, 2R2W
- Mask ROM
- OTP
I Standard I/Os
- 2.5V/3.3V / 5V tolerant
- 3.3V PCI- Oscillator
- Analogue
I High Speed I/O
- CDR Tx/Rx
- FPD Link Tx+Rx
- HDMI Tx 2.25Gbps
- MIPI D-PHY Rx 650Mbps
- MIPI D-PHY Tx 650Mbps
- PCI Express 2.5Gbps PHY
- SATA 1.5G / 3.0G PHY
- SubLVDS Rx / Tx 650Mbps
- LVDS
- MDDR, DDR2, DLL
- SSTL2, SSTL18
- USB2.0 PHY
I APLLs
- Input frequency up to: 200MHz
- Output frequency: 50MHz...1.6GHz
- SSCG
- Low power, low jitter
I ADC / DAC
- Resolution: 6 - 14-bit
- Sample rate up to: 1Gsps
I Analogue
- POR, LDO
- Audio Codec
I Cores
- ARM7TDMI-S
- ARM926EJ-S, ARM946E-S
- ARM1176JZF-S- CortexTM-M0, M4, A5, A15
- Cortex-M3, Cortex-R4F
- Cortex-A9
65nmI Standard Cells
- Multiple Vth
I Memory
- SRAM 1RW, 2RW
- RF 1R1W, 2R2W
- Mask ROM
- OTP
I Standard I/Os
- 3.3V LVCMOS
- Oscillator
- Analogue
I High Speed I/O
- CDR Tx/Rx
- FPD Link Tx+Rx
- HDMI Tx 1.20Gbps
- HDMI Tx 2.25Gbps
- MIPI D-PHY Rx 1Gbps
- MIPI D-PHY Tx 1Gbps
- PCI Express 2.5Gbps PHY
- SATA 1.5G / 3.0G PHY
- SubLVDS Rx+Tx 650Mbps
- SubLVDS Rx+Tx 1Gbps
- MDDR, DDR2, DDR3, DLL
- SSTL2, SSTL18, SSTL15
- USB2.0, USB3.0 PHY
I APLLs
- Input frequency up to: 200MHz
- Output frequency: 50MHz...1.6GHz
- SSCG
- Low power, low jitter
I ADC / DAC
- Resolution: 8 - 14-bit
- Sample rate up to: 200Msps
I Cores
- ARM7TDMI-S
- ARM926EJ-S, ARM946E-S
- ARM1176JZF-S- Cortex-M0, M4, A5, A15
- Cortex-M3, Cortex-R4F
- Cortex-A9
40nmI Standard Cells
- Multiple Vth
I Memory
- SRAM 1RW, 2RW
- RF 1R1W, 2R2W
- Mask ROM
- OTP
I Standard I/Os
- 3.3V LVCMOS
- Oscillator
- Analogue
I High Speed I/O
- HDMI Tx 1.5Gbps
- MIPI D-PHY Rx 1Gbps
- MIPI D-PHY Tx 1Gbps
- SATA 1.5G / 3.0G PHY
- SubLVDS Rx+Tx 650Mbps
- MDDR, DDR2, DDR3, DLL
- SSTL2, SSTL18, SSTL15
- USB2.0, USB3.0 PHY
I APLLs
- Input frequency up to: 200MHz
- Output frequency: 400MHz...1.2GHz
- SSCG
- Low power, low jitter
I ADC / DAC
- Resolution: 12-bit
- Sample rate up to: 220Msps
I Cores
- ARM7TDMI-S
- ARM926EJ-S, ARM946E-S
- ARM1176JZF-S- Cortex-M0, M4, A5, A15
- Cortex-M3, Cortex-R4F
- Cortex-A9
Selection from Fujitsu IP Portfolio
5/10/2018 Fujitsu - Seemless Integration of IP Cores into System LSI - IP & Cores - slidepdf....
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Page 3 of 4
ARM1176JZF-S
ARM926EJ-S
ARM946E-S
ARM7TDMI-S
ARM Core Line-up
Application
Real-Time
Microcontroller
2010 2011 2012 2013 2014
Cortex-R4F
Cortex-M3
Cortex-A9 Cortex-A15
Cortex-A5
Cortex-R7
Cortex-R5
Cortex-M4
Cortex-MO
ARM Processor Roadmap for ASIC/Foundry Service
ARM1176
ARM926
ARM946
ARM7 M3
A9
R4F
A5
M0
A15
R5
M4
Available
Designing
Planning
2010 2011 2012 2013 2014
Fujitsu ARM SoC Prototyping (FASP) Reference Design Roadmap
5/10/2018 Fujitsu - Seemless Integration of IP Cores into System LSI - IP & Cores - slidepdf....
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Page 4 of 4
Factsheet Fujitsu IP & Cores
FSEU-C32-02AUG11
[email protected]://emea.fujitsu.com/asic
All company and product trade marks and registered trademarks used throughout this literature are acknowledged asthe property of their respective owners.
FASP-M3 reference design block diagram
Trace
JTAG/
SWD
AHB BusMatrix
Cortex-M3 Core HDMAC
CPU Block
SWJ-DP
ExternalMemory
Clock Reset
TPIU ETM WIC
CRG
MEMC
Ahb2ApbSRAM
(I code)
SRAM
(D code)
SRAM
(work)
EXIU GPIO TIMER UART WDT MRBC
Instruction Data System
APB
Fujitsu ARM SoC Prototyping (FASP)I Non application-specific base platform
- Only basic peripherals are implementedI Easy customisation, easy chip development
- By changing the configuration of
Cortex-M3- By adding or removing peripherals,
replace BusMatrix
- By changing interrupt signal assignment
I Deliverables
- Reference design of SoC (RTL)
- Simulation environment (Testbench,
simulation script)
- Boot code (initialisation of Cortex-M3 andperipherals)
- Documents (Specifications, User Guide,
Implementation Guide)
FASP-M3 reference design concept