From Simulink to NoC-based MPSoC on FPGAfrobino/data/NoC_workshop/presentation.pdf · simulation...

From Simulink to NoC-based MPSoC on FPGASimulink front-end for the NoC System Generator (NSG)

Francesco Robino

KTH Royal Institute of Technology

ICES seminar

F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 1 / 17

Overview of the talk

Motivation

What is the problem?Our goal

Reaching the goal

Simulink simulation semanticsThe HeartBeat (HB) model in a MPSoC generated by NSGConnecting Simulink and HB NoC-based MPSoC semanticsExperimental evidences and results

Conclusion


The problem

Matlab/Simulink is today’s de-facto standard for model-based designin domains such as control engineering and signal processing.NoC-based MPSoCs are promising candidates for future embeddedsystem (potentially high performances, low power consumption,. . . ).Synthesis of a Simulink model onto NoC-based MPSoCs is still anopen issue.

Pe Pe

PePe

Pe

Pe

Application Instance

Platform Instance


Our goal

To enable an end-to-end design flow, we follow the principles of theplatform-based design methodology, constraining platform (MPSoC)and functionality (Simulink model) to share a common semanticdomain.

Pe Pe

PePe

Pe

Pe


Platform Instance

Common semanticsdomain


Simulink: an environment for system-level design

A Simulink model is graphically described through the use of blocks(e.g. an adder, a transfer function, etc.) and subsystems (a set ofblocks), linked by signals.

Using different blocks and subsystems, architecture and applicationspecification can be combined in a mixed HW/SW model.


Solvers and Simulink simulation semantics

Initialization

Simulationstop time?

Start simulation

Y

N

Store inputs

Compute outputs

Generate outputs

Advance simulation time

Stop simulation

Sim

ulat

ion

loop

Simulink simulates a dynamic system bycomputing its states at successive timesteps over a specified time span, usinginformation provided by the model.

A solver determines the time of the nextsimulation step and applies a numericalmethod to solve the set of ordinarydifferential equations (ODEs) that representthe model.

Different solvers embody different approachesto solve a model.



Initialization


Start simulation

Y

N

Store inputs

Compute outputs

Generate outputs


Stop simulation

Sim

ulat

ion

loop

Solvers:

fixed-step VS variable-step

0 0.25 0.5 0.75

S0 S0 S1 S2

1 1.25 1.5 1.75

S3 S3 S4 S4

0 0.5 0.75

S0 S1 S2

1 1.5

S3 S4

discrete VS continuous

Continuous: compute model’s continuousstates at the current time from the states atprevious time steps and the state derivatives(requires ordinary differential equations).

one-step VS multi-step

One-step solvers estimate y(tn) using only thesolution at the preceding time point y(tn−1)Multistep solvers use the results at severalpreceding time steps to compute the solution



Initialization


Start simulation

Y

N

Store inputs

Compute outputs

Generate outputs


Stop simulation

Sim

ulat

ion

loop

Our approach today targets the following solverconfiguration:

fixed-step (constant step size tstep)

discrete

one-step

However, it can be extended to other solvers too. . .


Simulink Embedded Coder

Execute rt_onestep

Interruptreceived?

Begin

Y

N

PE

SW

Initialize SW processes

Wait first interrupt

Interrupt

When we select a fixed-step solver, we can use theSimulink Embedded Coder to generate C code ofthe model for use on embedded processors. Thecode generated include:

Main scheduler sensitive on interrupt.

rt onestep function, implemented in theinterrupt service routine (ISR), describing thefunctionality of the system.

The generated software is compliant with theexecution model of the Simulink simulation!


The HeartBeat model in a MPSoC generated by NSG

Execute SW processes

HB tickreceived?

Begin

Y

N

PE

HB tick SW


Wait first HB tick

PE 0 PE 1

PE 2PE 3

0 1 2 3

3 6 5 8

PE 0

NoC

HB period

HB ticks

εc

0 1 2 3

7

NoC

εc

0 1 2

8

NoC

εc

431 2

9

NoC

εc

430 5

PE 1

PE 2PE 3

NoC System Generator

process networkand system specs

HB process wrapper

Simulink model


Connecting Simulink and HB NoC-based MPSoC semantics

Simulink

Initialization


Start simulation

Y

N

Store inputs

Compute outputs

Generate outputs


Stop simulation

Sim

ulat

ion

loop

Emb. Coder

Execute rt_onestep

Interruptreceived?

Begin

Y

N

PE

SW


Wait first interrupt

Interrupt

HeartBeat

Execute SW processes

HB tickreceived?

Begin

Y

N

PE

HB tick SW


Wait first HB tick

Table: Common semantics parameters and design rules

Simulink HB compliant MPSoCtime steps HB ticksstep size (tstep) HB period (tHB)simulation loop SW processes triggered by HB wrapperrt onestep SW running on one PEblocks instructions of SW processsubsystem SW processes on a single PE (rt onestep)signal NoC communication path


Platform Instance


Case study: DSP system (Digital FIR filter)

http://www.mathworks.se/help/dsp/ug/digital-filter-block.html


http://www.mathworks.se/help/dsp/ug/digital-filter-block.html

Case study: Embedded coder vs SLD HB methodology

PE 0

PE 0 PE 1

PE 2PE 3


Case study: results

Table: WCET, minimum tHB , memory requirements

1 PE 4 PEsSource Noise Filter Sink

WCET - Min. tHB [ms] 28 7,90 11,68 8,00 0,01Mem. req. w/o OS [KB] 53 33 27 21 16Mem. req. eCos [KB] +20 +20 for each PEMem. req. uCLinux [MB] +2 +2 for each PE

Splitting the system in 4 subsystems using this methodology, increases thethroughput of the system of ca 2.4×. If we would have created 4subsystems having equal WCET (i.e. 7 ms), we could have reached atheoretical 4× throughput increase.

The increase in throughput comes at the expense of memory.


Case study: semantics preserving?

[0.00003,0.00006,-0.001011,-0.006998,...]

[0.000000,0.453990,0.809017,0.987688,...]

[X,-0.014091,0.043682,0.440711,...]

[X,X,0.00003,0.00006,...]

[0.043682,0.440711,...]

[0.00003,0.00006,...]

[0.809017,0.987688,...]


Conclusions

We have described a system-level design flow that allows thesynthesis of Simulink models to NoC-based MPSoCs, generatinga working prototype on low-cost FPGAs.

The generated MPSoC is constrained to share a common semanticsdomain with the Simulink model, so that the results betweensimulation and implementation of the prototype are the same, withoutthe need of resource consuming SW components (such as OS).

Design methodology based on process constructors — HB processwrappers to provide execution semantics to the MPSoC.

Developed a synthesis methodology with similarities with synchronousHW design

Minimize HB period tHB .Exploits task, data and pipeline parallelism.


Questions?

Suggestions:

Can this approach be extended to other Simulink solvers?

Does this approach provide real-time guarantees?

No OS overheadQuite precise measurement of WCETWhen no shared connections, quite precise (and not pessimistic) WCCT

Why not everything asynchronous1? (see asynchronous CPUs)

1Asynchronous circuits are not governed by a global clock, but they use signals toindicate completion of instructions and operations, specified by data transfer protocols.


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