Thomas Mikolajick1,2 , Stefan Schmult2, Rico Hentschel1,

Patrick Hofmann1, and Andre Wachowiak1

1 NaMLab gGmbH

2 Chair of Nanoelectronic Materials, TU Dresden

From Bulk Gallium Nitride Material to Vertical GaN Devices

www.namlab.com

Outline

o Introduction GaN

o GaN HVPE material

Doping

o GaN Vertical Device

Trench gate MOSFET

Introduction GaN

GaN material properties• III-V compound semiconductor

• Hexagonal crystal lattice

• Direct semiconductor

• Wide bandgap ~3.4 eV

high breakdown E-field strength

• High mobility 2DEG at GaN/AlGaN

heterostructure interface

EVBM

ECBM

Ga

N

Ga-face

c-ax

is

p-GaN

MQW

n-GaN

Application of GaN Semiconductors

LEDLaser

DiodesPower

Devices

RFelectronic systems

OPTO - ELECTRONICS ELECTRONICS

car lighting

power supplypower management

electric vehiclehybrid electric vehicle

power amplifier

RF communicationsprojection

PV converter

industry

GaN for power devices

Melting point[x 1000°C]

Band gap[eV]

Breakdown fieldEcrit [MV/cm]

Electron mobility[x 1000 cm2/Vs]

Electronsat. velocity[x 107 cm/s]

Properties Si / SiC / GaN

GaN Levers:

Superior bulk properties for power

applications: Ecrit, µ, Egap

Higher temperature operation possible

HEMT device concept

Advantages of GaNLow on-state resistance at given voltage rating

- compact high voltage devices- fast efficient switching

Benefits on system level:- more efficient energy conversion- smaller inductors- smaller and low weighted converter systems

energy saving / innovative systems

Area specific Ron vs. Breakdown VoltageStephen Sque (NXP) – ESSDERC tutorial (2013)

GaN Material

Advantage:

• Low cost for large diameter: up to 200mm available

• Device processing in standard silicon fabs

Challenge:

large lattice and thermal expansion mismatch to Si

Core IP in complex strain management buffer

• Semi-Insulating properties by compensation of

residual n-type doping (N-vac.,O) with C, Fe,..

• Dislocation density in top layers: 1E8–5E8 cm-2

• Alternative Substrates: Sapphire, SiC ~ 150 mm

Advantage:

• No lattice and thermal expansion mismatch

• Low dislocation density of substrate < 3E6 cm-2

Challenge / Requirements:

high-quality regrowth without defect generation

• Freestanding GaN substrate wafer by HVPE growth

– wafer size 2-4“

• Chemical-mechanical polished substrate surface

• Doping of GaN substrate wafer

MOCVD hetero-epitaxy on host substrate Homo-epitaxy of functional devicelayers on GaN substrate

ExampleHEMT structureon Si (111)

n+ GaN wafer

Layer stack

dependent on deviceMOCVD (MBE)

GaN HVPE material

GaN HVPEHVPE: Hydride Vapour Phase Epitaxy:

• Growth on GaN/Sapphire Template

• Growth thickness: several 100 µm – 1 cm

• Growth rate: ~ 100 - 400 µm/h

• Growth Temp.: 850 - 1000 °C

• Dislocation density: ≤ 2E6 cm-2

• Low residual dopant conc. (uid): ≤ 1E16 cm-3NaMLab´s verticalHVPE Reactor

Doping GaNDoping during growth

Introduction of dopant to the growth atmosphere

Post growth doping

Ion implant lattice damage• High temp. anneal necessary• for pGaN: Mg (>1300°C)

material decomposition w/o cap

Diffusion• Small diffusion constants for Si and

Mg reported

Semi-insulating GaN

device, sensoryapplicationsMain dopants: FeGa , MnGa, C

n-type GaN

Optoelectronic, sensory, power applicationMain dopants: SiGa, GeGa, (ON)

p-type GaN (MOCVD)

Optoelectronic, powerapplicationDopant: MgGa

GaN:Si GaN:Ge GaN:Fe GaN:Mn

Si-Doping n-type

2017-11-15 T. Mikolajick

Local strain analyses by Raman spectroscopy using „E2high mode“

un-intentionallydoped-GaN

GaN:Si~2E18 cm-3

x-section

Patrick Hofmann et al J. Phys. D: Appl. Phys. 49 075502 (2016)

2“ GaN Boule

• Si SiGa, ED = 22–30 meV

• HVPE: dichlorosilane, thermal stability

• Reduction of threading dislocation prior Si doping to avoid tensile stress generation

HVPE GaN:Si samples ne ~2*1016 -4*1019 cm-3

Dichloro-Silane (DCS)

Linear dependency of chargecarriers on eff. DCS flow

Ge doping n-type

2017-11-15 T. Mikolajick

• n-type doping without tensile stress generation

• Vapour phase dopant smaller incorporation efficiency

• Solid State Doping line

0.01 0.1 10

1E16

1E17

1E18

1E19

1E20

1E21

Sample 1

Sample 2

Hall

SIMS

Co

nce

ntr

atio

n [cm

-3]

HCl flow [sccm]

Sample 3

0 1 2 3 4 5 6 7

1E16

1E17

1E18

1E19

1E20

1E21

Co

nce

ntra

tion

[cm

-3]

Sputter depth [mm]

Sample 3

Sample 2

Sample 1

FFT @ 5.2 rpm

FFT @ 2.6 rpm

Patrick Hofmann et al. J. Cryst. Growth 45 075502 (2016)

SIMS

Doping flux

Pyroelectricity ofsemi-insulating GaN

2017-11-15 T. Mikolajick

Change of spontaneous polarization due to change in temperature

Dependence of pyroeletric effect on c-lattice constant:Spontaneous polarization function of lattice constant and different dopants change c-lattice constant differently

Measure current with electrodeson c–plane surfaces

Sven Jachalke et al. Appl. Phys. Lett. 109, 142906 (2016)

T(t)I(t)

GaN:Fe / GaN:Mn / GaN:C

∆PS = p ∙ ∆T

GaN vertical device

GaN for power switches

V·I ≠ 0 Power LossEfficiency < 1

ISD

VSD

min. ILeak

VBD

ON

OFF

fast switching

by gate

Imax min RON

Source Drain

Gate

Performance Targets • Min. On-Resistance (RON)• Max. Break-Down Voltage VBD

• Fast Switching w/o Transients• Small Device Area / Large Wafer low cost

Stephen Sque (NXP) – ESSDERC tutorial (2013)

𝑉𝐵𝐷2

𝑅𝑂𝑁∗𝐴= 𝜇𝐸𝐶

3 𝜖/4 = 𝐶𝑚𝑎𝑡

highest for GaN

Advantages of GaNLow on-state resistance at given voltage rating

- compact high voltage devices- fast efficient switching

Benefits on system level:- more efficient energy conversion- smaller inductors- smaller and low weighted converter systems

energy saving / innovative systems

Area specific Ron vs. Breakdown Voltage

AlGaN

GaN2DEG

Passivation

Substrate Si(111)

Strain management(AlGaN/GaN) buffer

Compensated (C,Fe ..)

Gate-Drain distance

defines VBD

Source Drain HV

Gate

Gate

p

n(-) GaN drift

n(+) GaN Substrate

n(+)

Source

n(+)

Drain: HV

e-

Example: Trench MOSFETHEMT = High electron mobility transistor

Lateral GaN HEMT Vertical GaN Transistor

Advantages- area efficient scaling of breakdown voltage with

drift layer thickness (> 1 kV)- separation HV / isolation, less surface effects- GaN substrates dislocations density < 3E6 cm-2

Pros- High mobility 2DEG- large GaN-Si epi wafer up to 200 mm

Cons- Less area efficient for high voltages- Vertical buffer breakdown / trapping- Higher dislocation density > 1E8 cm-2

Con- Costly GaN substrates / Wafer size 2-4“

Vertical transistor device concepts in GaN

+ Vth = 2.5 V

+ high channel mobility

- Complex integration

Trench MOSFET

Examples

MOS Fin Tower

+ no p-GaN used

+ low Ron

- Vth~ 1V for fins < 500nm

Slanted HEMT p-GaN Gate

+ high Vth > 3V

- Lower channel mobility

Min Sun et al. IEEE EDL (2017) 48, p509Daisuke Shibata et al. IEDM (2016)

Pics from Jie Hu et al. Mat. Sci. Semi. Processing (2017)

• Ch. Gupta et al. IEEE EDL (2016) 37 p1601• Ray Li et al. IEEE EDL (2016) 37 p1466• Tohru Oka et al. APEX (2015) 8 p054101

Pseudo-vertical MOSFET device

e-

p GaN

n+ GaN

n- GaN

n+ GaN

SG

D

S

p GaNn+ GaN

n- GaN

n+ GaN

Sapphire

G S B D

„True“ vertical MOSFET Pseudo-vertical MOSFET

separated high and low voltage terminals

area efficient scaling of breakdown voltage with drift layer thickness

normally-off operation

better GaN material availability

Limitations in RON and VBD n- GaN thickness, TDD, top-sided Drain

process and characterization welltransferable to „true“ vertical devices

suitable test vehiclefor technology setup

n+/p/n- layer stack on freestandingGaN needed

(Low volt.)

(High volt.)

Benefits of MBE for n+ GaN regrowth

• Hydrogen free environment for PA-MBE

• Lower growth temperature (600-700°C)

• High quality regrowth: dislocation density n+ surface ~

2·109 cm-2 as on p GaN surface

Sapphire substrate

p GaN : Mg

n+ GaN : Si

n- GaN : Si

n+ GaN : Si

1,0

2,0

3,0

4,0

5,0

0 1 2 3 4 5

(nm)

(µm)

0

1

2

3

4

5

0

1

2

3

4

5

Dislocationexamples

prior to MBE overgrowth: H out-diffusion anneal

RRMS = 0.3 nm

RRMS = 0.4 nm

Dislocationexamples

≈ 300 µm

3500 nm

1000 nm

500 nm

200 nm

Atomic force microscope images

Pseudo vertical layer stack

Semiconductor Devices & Microsystems (ASDAM), 2016

Device integration

Gate trench etch (dry & wet)

Gate dielectric deposition (ALD-Al2O3)

Gate metal deposition & structuring (ALD-TiN)

Passivation (ALD-Al2O3)

Growth & p-GaN: Mg activation

Insulation / pseudo vert. etch

Ohmic contacts to n GaN (Ti/Al)

Upper n+ GaN etch

Ohmic contacts to p GaN (Ni/Au)

Gate

p GaNn+ GaN

n- GaN

n+ GaN

Source Body Drain

Sapphire

TiN

Ti/AlNi/Au

Ti/Al

Al2O3

Al2O3

GaN

200 nm

TiN

processed

2“ wafer

contact lithography

R. Hentschel et al. at ASDAM 2016

Device characteristics

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

VGS = 7 V to 12 V, 1 V step

Drain-Source Voltage VDS

(V)

Dra

in C

urr

. D

en

sity I

D (

mA

/mm

) Output characteristics

expected output control with increasing gateoverdrive withVth ~5 V

Transfer characteristic

ID(VDS) scaling but weak output saturation

= 5 V

Well controllable normally-off operation

R. Hentschel et al. at ASDAM 2016

p GaN

n+ GaN

n- GaN

n+ GaN

Sapphire

VGS 0V 0V VDS

G S B D

Body bias method: measure p-GaN:Mg activation

Transfer characteristics @ VBS

Vth = ΦMS −Qeff

Cox+ 2ϕF +

2qϵGaN𝐍𝐀− x (|2ϕF−UBS|)

Cox

Substrate control allows estimation of apparent hydrogen-free Mg acceptor sites

estimated concentration NA- = 8·1017 cm-3 (SIMS: NMg = 3·1018 cm-3 )

• Many Mg-sites hydrogen passivated

• p-GaN:Mg deep acceptor level ~ 0.18 eV

• reduced hole conc. in equilibrium at RT

p -GaN

n+ -GaN

n- -GaN

n+ -GaN

Sapphire

VGS 0V 0.1VVBS

G S B D

R. Hentschel et al. at ASDAM 2016

vertical GaN transistor benchmark

• Vertical GaN transistors beyond

lateral GaN HEMT

• Different device concepts with

different strength (VTH, RON, VBD)

2017-11-15 T. Mikolajick

[1] T. Oka et al. APEX 8, p054101 (2015)

[2] Daisuke Shibata et al. IEDM (2016)

[3] Min Sun et al. IEEE EDL 48, p509 (2017)

Graph by part from Daisuke Shibata et al. IEDM (2016)

[2] slanted HEMT p-GaN Gate

[1] Trench MOSFETL

VTH =1V

[3] Fin tower MOSFET

vertical

lateralHEMT

area specific RON vs. Breakdown Voltage

Summary and outlooko HVPE growth currently most productive technology for GaN wafer

o n-type doping opens door for vertical power devices

o Promising performance indicators of vertical GaN devices

(main competitor SiC MOSFET)

o Further understanding of interaction between material and device

important to foster vertical GaN power technology

o Reliability to be demonstrated on large device count

o Influence of defect density and different types on yield

o Availability and cost development of larger GaN wafer (100mm and

above) important for decision on manufacturing

Thank you for your kind attention !!!

Acknowledgement: “This work was financially supported by the European Fund for regional Development EFRD, the Free State of Saxony, Europe supports Saxony and the German Federal Ministry of Education und Research BMBF”

Cooperation:

Thanks to:

• Martin Krupinski

• Nadine Szábo

• Felix Schubert