TM

September 2013

2 TM

3 TM

>50 Year Legacy

>5,500 Engineers

>6,000 Patent Families

フリースケールは、A Global Leader in

Microcontrollers

Digital Networking

Automotive MCU

Analog & Sensors

RF

Five Core Product

Groups

Four Primary

Markets

Automotive

Networking

Industrial

Consumer

4 TM

Smart Mobile Devices

eReaders

Appliance & Home Energy

Control

Portable Medical

Smart Meters & Connectivity

Factory Automation and

Drives

Automotive Networking Industrial Consumer

General Embedded

General Embedded

Sensors for Phones and

Games

Powertrain

Cloud Computing

/ Data Centers

Routers & Switches

Servers & Security

Chassis & Safety

Wireless Base Stations

Advanced Driver

Assistance

Vehicle Networking &

Information

Networked Printers & Gateways

Radar & Vision Systems

5 TM

TM

小型セルから大型セルまで

幅広い拡張性を備えたマルチスタンダード対応

ワイヤレス基地局プロセッサ・ファミリ

• フェムトからマクロまで共通アーキテクチャ

• 高機能ヘテロジニアス・マルチコア

• LTEを含むマルチ・スタンダード対応

• 小型化、省電力、低コストを実現

5

DSP MPU ASIC FPGA

Basestation-on-a-Chip 基地局機能を1チップに

2011年発表

6 TM

• 8 to 16 users

(LTE (FDD, TDD), WCDMA,

CDMAx) and multi-mode

• >1000 users

• Multi-sector, Multi-

standard and multi-mode

• 3GPP Rel. 10 • 128 to 256 users

• Multi-standard and multi-

mode, 1 - 2 sectors

• 3GPP Rel. 10

• Pin compatible with B4860 • 32 to 100 users

(LTE (FDD, TDD), WCDMA)

and multi-mode

45 nm 28 nm

BSC9130/31 Femto

BSC9132 Pico

B4420 Micro

B4860 Macro

7 TM

Single Chip Femto Base Station

• Home Femtocell up to 8 users – BSC9130

• SMB Femtocell up to 16 users – BSC9131

Multi-standard Architecture

• LTE, WCDMA

• 2G/3G Sniffing and GPS Support

SoC Architecture

• e500 core, built on Power Architecture®

technology, subsystem (800 MHz – 1 GHz)

• SC3850 core, built on StarCore technology,

subsystem (800 MHz – 1 GHz)

• MAPLE-B2F Baseband Accelerator Engine

for LTE, WCDMA, CDMA2K and WiMAX

technologies

• Security engine - IPsec, Kasumi, Snow-3G

• IEEE®1588 v2, NTP

• 2x Ethernet RGMII and IEEE1588 v2

• JESD 207 RF transceiver interface

QorIQ Qonverge BSC9130 and BSC9131 Processors

7

最初の統合化SoC

8 TM

Single Chip Pico Base Station

• Scalable platform - up to 64 users

Multi-standard Architecture

• LTE, WCDMA, 802.16e

SoC Architecture

• Dual e500 cores, built on Power

Architecture®

technology, subsystem (1 GHz to 1.2 GHz)

• Dual SC3850 cores, built on StarCore

technology, subsystems (1 GHz to 1.2

GHz)

• MAPLE-B2P Baseband Accelerators

Engine for LTE, WCDMA and WiMAX

technologies

• Security engine - IPsec, Kasumi, Snow-3G

• IEEE®1588 v2, NTP

• 4 SerDes lanes, combining:

− 2x Ethernet SGMII

− 2x CPRI v4.1 @ 6.144G antenna

interface

− 1x PCIe @ 5G x2 lanes

• Quad JESD207 RF transceiver interfaces

QorIQ Qonverge BSC9132 Processors

8

複数コア化への拡張

9 TM

• Next-generation, dual-thread e6500 Power Architecture® cores offer highest coremark/watt with AltiVec SIMD technology for dramatic layer 2 scheduling acceleration

• Industry-leading performance SC3900 StarCore provides 2x DSP performance compared to competitive offerings

• Smart hardware acceleration for layer 1, layer 2, control and transport allows for best-in-class balance for the different processing layers, performance and cost

• LTE, HSPA+ and LTE-Advanced simultaneous multi-mode support

• Trusted system in unsupervised areas prevents running untrusted code and extraction of sensitive code or values

• High-speed, industry-standard interfaces provide antenna, Wi-Fi chipset and backhaul glueless connectivity

• Pin- and code-compatible with B4860 SoC, providing seamless hardware and software migration from macro to metro base stations

T1 T2

Power

e6500

32 KB

D-Cache

32 KB

I-Cache

T1 T2

Power

e6500

32 KB

D-Cache

32 KB

I-Cache

2MB Banked L2

StarCore™

SC3900 FVP

32 KB

D-Cache

32 KB

I-Cache

StarCore

SC3900 FVP

32 KB

D-Cache

32 KB

I-Cache

StarCore

SC3900 FVP

2MB Banked L2

CoreNet Cache Coherency Switch Fabric

Pre-fetch

8-Lanes 10G SERDES

Real-Time Debug

Watchpoint

Cross Trigger

Perf. Monitor

Corenet Trace

Aurora x2 PC

Ie x

4

5G

FMAN

Parse, Classify,

Distribute

iEEE®1588v2 Security

Engine

5.3

Queue

Mgr.

Buffer

Mgr.

Security Monitor

USB 2.0

IFC

2x DUART

4x I2C

2x eSPI

4x C

PR

I 9

.8G

GPIOs

MAPLE-B3

1x eTVPE

5x eFTPE

1x EQPE2

6x RISCs 1x DEPE

1x PUPE2

1x PDPE2

1x ULB2

1x ULF2

1x TCPE

1x CRPE

2x CRCPE

512KB

CoreNet

Platform

Cache

64-bit

DDR3

Memory

Controller

SD/MMC

2.5

G/1

G

8x D

MA

2.5

G/1

G

2.5

G/1

G

2.5

G/1

G

次世代コアおよび28nmプロセス採用による統合規模の拡大

10 TM

• Next generation, Power Architecture e6500 cores offer highest CoreMark/Watt with AltiVec technology for dramatic L2 scheduling acceleration

• Next generation, StarCore SC3900 provides 2x DSP performance compared to competitive offerings

• Above 21GHz of Programmable Performance

• Smart hardware acceleration for Layer 1, 2, Control and Transport allows for best in class performance, power and cost

• Large scale SoC integration allows for simpler programming models and easier load balancing

• Rich I/O including antenna interface provides flexibility and reduces overall system cost マクロ基地局の機能を1チップに

11 TM

Dev Systems

• Integrated IDE

• Optimizing

Compilers for DSP

and MPU

• Debugger

• Profilers/Tracing

• Simulation Tools

B4860 QDS

• Full features

development

• Software

development

• Evaluation

• Reference design

General

Purpose

Development

System

Dev Tools OS Partners Simulation Tools

• Linux

• VxWorks

• OSE & OSEck

• SmartDSP-OS

• ‘Vista’

Modeling/Analysis

Application

Software

• LTE and WCDMA

Layer 1 Software

Libraries

TM

• Transport &

Control Software

• Device functional

accurate model

• Core

performance

accurate model

BasePort™ PHY product

12 TM

• Higher density solutions

− Doubling in performance or greater

• Super Macro development

− Leverage RRH & DAS

• Centralized BTS with large resource pools

− L1, MAC Scheduler, L2, Transport & Control

• Cloud-RAN with virtualized, pooled resources

− Specialized L1, virtualised GPP for higher level functions

Remote Radio Heads

CPRI Fiber

Connections

BBU Pool/Hotel

更なる高集積・高密度化

集中化によるプロセッシング機能ブロックのプール化

組込みプロセッサの更なる高性能化要求

13 TM

16-Lane 10GHz SERDES

64-bit

DDR2/3

Memory

Controller

CoreNet Coherency Fabric

PAMU PAMU PAMU Peripheral Access

Mgmt Unit

Security Fuse Processor

Security Monitor

2x USB 2.0 w/PHY

IFC

Power Management

SD/MMC

4x DUART

4x I2C

SPI, GPIO

64-bit

DDR2/3

Memory

Controller

64-bit

DDR3

Memory

Controller

64-bit

DDR3

Memory

Controller

512KB

Corenet

Platform Cache

512KB

Corenet

Platform Cache

PAMU

Queue

Mgr.

Buffer

Mgr.

Pattern

Match

Engine

2.0

Security 5.0

64-bit

DDR2/3

Memory

Controller

64-bit

DDR3

Memory

Controller

512KB

Corenet

Platform Cache

RMAN

DCE

1.0

Parse, Classify,

Distribute

1/ 10G

1/ 10G

1G

1G

1G

1G

FMan

1G

1G

Parse, Classify,

Distribute

1/ 10G

1/ 10G

1G

1G

1G

1G

FMan

1G

1G

Inte

rla

ken L

A

16-Lane 10GHz SERDES

Processor

• 12x e6500, 64b, up to 1.8GHz

• Dual threaded, with128b AltiVec

• Arranged as 3 clusters of 4 CPUs, with

2MB L2 per cluster; 256KB per thread

Memory Subsystem

• 1.5MB CoreNet Platform Cache w/ECC

• 3x DDR3 Controllers up to 2.1GHz

• Each with up to 1TB addressability (40 bit

physical addressing)

• HW Data Prefetching

CoreNet Switch Fabric

High Speed Serial IO

• 4 PCIe Controllers, with Gen3

• SR-IOV support

• 2 sRIO Controllers

• Type 9 and 11 messaging

• Interworking to DPAA via Rman

• 1 Interlaken Look-Aside at up to10GHz

• 2 SATA 2.0 3Gb/s

• 2 USB 2.0 with PHY

Network IO

• 2 Frame Managers, each with:

• Up to 25Gbps parse/classify/distribute

• 2x10GE, 6x1GE

• HiGig, Data Center Bridging Support

• SGMII, QSGMII, XAUI, XFI

HiGig DCB HiGig DCB

Pre

-fetc

h

2MB Banked L2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

2MB Banked L2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

2MB Banked L2

Power ®

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ®

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ®

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ®

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Watchpoint Cross Trigger

Perf Monitor

CoreNet Trace

Aurora

Real Time Debug

SA

TA

2

.0

SA

TA

2.0

PC

Ie

PC

Ie

2xDMA

sR

IO

sR

IO

PC

Ie

PC

Ie

24スレッドがシングルチップに

プロセッシング機能のブロック化、プール化

14 TM

高性能 • 業界最高のCoreMarkスコア

• 業界最高のワット当りCoreMarkスコア • 64ビット Power Architecture®コア

• デュアル・スレッドにより、シングル・スレッドの 1.7倍の性能を実現

• クラスタ型共有L2キャッシュ

• 128ビット AltiVec SIMDユニット

─ 192 GFLOPS

余裕のあるメモリ空間 • 40ビットの実アドレス

• 1テラバイトの物理アドレス空間

生産性の向上 • コア仮想化

─ 組込みハイパーバイザ

─ 論理から物理へのHWアドレス変換

高いエネルギー効率 • 他社ハイエンド・プロセッサより、

1.4～3倍の電力効率 • Drowsyモード： クラスタ単位、コア単位、および

AltiVecユニットに対して個別に電力制御可能

e6500 Core Complex

CoreNet Interface 40-bit Address Bus 256-bit Rd & Wr Data Busses

CoreNet Double Data Processor Port

T T

32K

Altivec

e6500

32K

PM

C T T

32K

Altivec

e6500

32K

PM

C T T

32K

Altivec

e6500

32K

PM

C T T

32K

Altivec

e6500

32K

PM

C

2MB 16-way Shared L2 Cache, 4 Banks

*Source: www.coremark.org

CoreMarkTM CoreMarkTM / Watt

Dual x12 thread

server processors

@2.266GHz *

32 core

processor

@1.5GHz*

T4240

@1.8GHz

1.4x 3x

CoreMarkTM Benchmarks

T4240 - Industry’s Best

• CoreMark Score

• CoreMark per Watt

基地局設備の省電力化に貢献

15 TM

PowerQUICC

1995

1998

PowerQUICC II

PowerQUICC II Pro

2004

PowerQUICC III

2003

• Power Architecture® cores, QUICC engine multiprotocol packet processing, security processing acceleration

QorIQ Processing

Platforms • Scalable family (P1 to P5) of

communications processors

• New multicore architecture

• Hardware-assisted Hypervisor, CoreNet on-chip fabric, Data Path (DPAA) & security acceleration

• 45nm node

Jun

2008

Feb 2011

QorIQ Qonverge

Processing Platforms • New wireless architecture:

integrates MPU, DSP, and accelerator cores in a heterogeneous SoC platform

QorIQ Advanced

Multiprocessing

T Series • Next-Generation Multicore

Platform

• New Power Architecture e6500 multi-threaded core

• 4X application performance

• 28 nm technology

Jun

2011

• Strong execution

• Over a dozen new products

Jun

2010

QorIQ P5 Platform • New 64-bit Power

Architecture e5500 core

• 2X performance from previous generationn

70+製品を量産中

15年以上の供給実績

マルチコア・プラットフォーム

45nmプロセス

Power とDSPの統合

新しい64bitマルチスレッドコア

28nmプロセス

64bit拡張

WCDMA

2001 年

10月~

HSDPA

2006 年8月~

LTE

2010 年12月~

16 TM

次世代QorIQ

アーキテクチャ

2011 QorIQ T Series

2008 QorIQ Multicore

1995

20 Years of Networking

ingenuity from

the #1 Leader in

Communications Processing

Accelerating the

Network’s IQ

2012

QorIQ next-generation

platform based

on Layerscape architecture (レイヤスケープ・アーキテクチャ）

第1世代 第2世代 第3世代

2012年発表

17 TM

• モジュラー型ハードウェア・フレームワー

ク

− GPPL: 汎用ソフトウェア処理

− APPL: パケット・オフロード処理

− EPIL: ワイヤレートI/Oスイッチング

• 各レイヤは個別に拡張可能

• CPUコアに依存しない（Core-agnostic）

SoCプラットフォーム

（Power Architectureコア or ARMコ

ア）

• APPLはGPPLから自立し、C言語によ

るフル・プログラミングが可能

• コアの違いを吸収する一貫したソフト

ウェアAPI/ライブラリ

Layerscapeアーキテクチャは、データパス・アクセラレーション・アーキテクチャ

（DPAA） の進化形

Syste

m In

terf

ace

s

Syste

m C

on

tro

l

Syste

m V

isu

aliz

atio

n (

De

bu

g/T

un

ing

)

General-Purpose Processing Layer (GPPL)

Accelerated Packet Processing Layer (APPL)

Express Packet I/O Layer (EPIL)

CPU(s) Caches Mem.

Cont.

Accelerated Packet Processor

Security

Engine

Pattern

Match

Engine

Load

Balance

Engine

Decomp

Engine

L2-L7 Switch

Engine

Packet

Buffer

Ethernet

Interlaken

SERDES

RapidIO PCI-Express 100/40/10/1G

アプリケーションに最適な組み合わせを可能にするプラットフォーム

18 TM

QorIQ

Qonverge Platform

基地局向けSoC

• Base station-on-chip（基地局機能を1チップ化）

• 微細化プロセス(28nm)

• QorIQ + Starcore DSP + Baseband Accelerator

通信プロセッサ

• シングルコアから24仮想マルチ・コアまで

• 微細化プロセス(28nm)

• 各種アクセラレータを搭載

• 従来Power Architecture 製品のソフトウェアの流用（互換性）

QorIQ Digital Networking

Processors

次世代通信プロセッサ・アーキテクチャ

• Core-agnostic platform for both Power and ARM architectures

• Industry’s first software-aware system architecture

Layerscape Architecture

for Next-Generation

QorIQ Platforms

19 TM

TM