7/28/2019 FPGAs for Software Radio

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FPGAs for Software Radio

In the last decade, ASICs (applicationspecific ICs) and DSPs have been de-ployed to handle nearly all the signal

processing functions associated with radiocommunications. Even though field-program-mable gate arrays have been around for

decades, the latest generation of FPGAs is sopowerful that it is now displacing bothASICs and DSPs in the latest software radioapplications. Furthermore, a new class ofdesign tools opens up FPGAs to both hard-ware and software engineers. Debuggingthese new devices has been greatly simpli-fied by excellent modeling and analysis tools.

Perhaps the most exciting new twist indesign tools is the growing libraries of IP(intellectual property) cores available fromFPGA vendors, and a whole new industryof third party companies that offer IP coresfor specific application areas.

Software Radio FunctionsFigure 1 shows a typical wireless commu-

nication software radio system with varioussignal processing tasks identified. Usually,the digital downconverter or digital receiversection is handled in a dedicated ASIC deviceconsisting of three major blocks: the mixer,the local oscillator and the filter.

The local oscillator, or NCO, consists of aphase accumulator, which is just a registerand an adder available as standard library

blocks for virtually all FPGAs. The phasevalue in the accumulator drives a sine/cosinelookup table which can be implemented as asimple ROM (read-only-memory). The mixeris nothing more than a pair of digital multi-pliers, now available as dedicated hardwareresources in the latest FPGAs.

Programmable DSPs are often used toimplement some common demodulation,decoding and analysis functions. However,FPGA vendors and third parties now offer agood selection of IP libraries to handleViterbi, Reed-Solomon, convolutional andtrellis decoders, data encryption standardengines, and various noisy channel models.

Both FFT and discrete cosine transformcores are also available with several differ-

ent block lengths.Several vendorsare offering scal-able FFT enginesranging in sizefrom 16 to 1024points and higherusing complex ra-dix 4 algorithms.Since the FFT oper-

ates on blocks of data, the block memoryRAM available with the newer FPGA de-vices allows some design tradeoffs. You cansave memory by doing an in-place FFT witha single block, or move up to a swinging

buffer arrangement to provide continuous

real-time calculations.To help with control functions, a long

list of IP cores is available for popular pro-cessors. The benefit here is that by using awell-supported core processor, one cantake advantage of existing code and thesoftware development tools already inplace for these engines.

For speech and video signals, a widerange of IP cores including ADPCM, J-PEGand color space converters is available. Thesame is true for the decimating low passfilter which usually consists of several CICfilter stages followed by a FIR filter. If

some or all of these signal processing func-tions are handled by the FPGA, theprogrammable DSP can then concentrate onthe control and analysis functions, muchmore appropriate for its capabilities.

Digital Receiver ASICs vs. FPGAsAlthough digital receiver functions can

be implemented within the FPGA, it candraw more power and cost much more perchannel than an ASIC, depending on manyfactors like sampling frequency, filter char-acteristics, and signal-to-noise requirements.

Usually, the ASIC digital receiver hasbeen designed with a full set of standardoperating modes and features and has beenmore thoroughly tested and characterizedthan a custom combination of IP core

building blocks available for FPGAs. Thisgap will obviously shrink as the cores be-come more complete. Since the ASIChardware is optimized for dedicated func-tions, the latest ASIC devices are usuallythe better choice for extremely high-perfor-mance receiver applications.

However, if you cant buy a standarddigital receiver ASIC with just the rightphase and frequency characteristics, theflexibility of the FPGA might get the jobdone. Also, for proof-of-concept systems orwhen time-to-market is critical, FPGAs areoften the right choice.

When the required signal-to-noise ratios,filter skirts, or frequency templates are

beyond the complexity of the standardfilter inside a commercial ASIC, the flexibil-ity of IP core filter designs for FPGAs canprovide just about any characteristic.

Figure 1. Digital signal

processing functions forsoftware radio.

A/DCONVERTER

RFTRANSLATOR

DIGITALLOW PASS

FILTERDEMOD

ANALYSIS/CONTROL

DIGITALLOCAL

OSCILLATOR

DIGITALMIXER

A/DCLOCK

DECODE

ANTENNA

Front End Digital Downconverter Programmable DSP

With Moores law at work,these FPGA devices sportincredibly small silicon geom-etries capable of operating atvery low core voltages and veryhigh clock speeds.

Most of these new devicestake advantage of ball gridarray packaging to deliver thou-sands of I/O pins while keepingthe footprint very small.

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Pentek, Inc.

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PROC A PROC CPROC B PROC D

Model 4294Quad G4PowerPC

VME Board

Model 6230VIM Module

4-CHNARROW-

BANDDIG. RCVR

4-CHNARROW-

BANDDIG. RCVR

4-CHNARROW-

BANDDIG. RCVR

4-CHNARROW-

BANDDIG. RCVR

4-CHNARROW-

BANDDIG. RCVR

4-CHNARROW-

BANDDIG. RCVR

4-CHNARROW-

BANDDIG. RCVR

4-CHNARROW-

BANDDIG. RCVR

14-BIT80 MHz A/D

14-BIT80 MHz A/D

14-BIT80 MHz A/D

14-BIT80 MHz A/D

14 14 14 14

Control ControlFrontPanel

I/O

ControlControlControl Control

Virtex-E FPGA Virtex-E FPGA16

FrontPanel

I/O

RF In RF In RF In RF In

RF TRANSFORMEROR AMPLIFIER &

LOW PASS FILTER(Filter may be

bypassed)

RF TRANSFORMEROR AMPLIFIER &

LOW PASS FILTER(Filter may be

bypassed)

RF TRANSFORMEROR AMPLIFIER &

LOW PASS FILTER(Filter may be

bypassed)

RF TRANSFORMEROR AMPLIFIER &

LOW PASS FILTER(Filter may be

bypassed)

DSPs vs. FPGAsWhile FPGAs can handle many of the

tasks traditionally performed on a program-mable DSP chip, there are several factorsworth considering. For example, even thoughtodays FPGAs have quite a bit of on-boardRAM, its still a far cry from the large externalSDRAMs normally surrounding a DSP chip.

In spite of all the best design tools and simu-lators, DSP code (like any software) alwaysseems to need more memory sooner or later.Newer FPGAs are now capable of embeddingSDRAM controller cores to help alleviate thisshortcoming.

While FPGA code can be reconfiguredfor new modes of operation and featureenhancements, its usually much easier tomake the more significant changes on aprogrammable DSP instead. Sometimes,a very small change can have a profoundimpact on the gate and logic cell topology.

System ExampleFigure 2 shows a 32-channel digital

receiver system suitable for a wide rangeof applications such as signal intelligence,direction finding, and signal trackingreceivers. It consists of a Pentek Model6230 VIM-4 mezzanine module attachedto a Model 4294 Quad G4 PowerPC VIMprocessor board at the bottom.

The receiver module has four 14-bit80 MHz A/D converters for digitizing IF orHF analog inputs entering through frontpanel SMA connectors. All four A/Ds feed a

bank of eight quad digital downconverter

ASICs with four channels of local oscillator,mixer and filter in each chip.

On board are two Xilinx Virtex-E FPGAs,each receiving the sixteen baseband signalsfrom the four quad receiver chips. The

FPGAs are used to handle data formattingand channel selection for delivery throughthe VIM interface to the 32-bit mezzanineFIFOs on the processor board. Since thereceiver signals flow through the FPGAs,they can also be used to perform demodu-lation and decoding functions to offloadthese tasks from the DSP.

All four A/Ds are connected to all eightquad receiver chips. Inside the front end ofeach receiver chip is a programmable cross-

bar switch that allows each of the fournarrowband channels inside to indepen-dently select any one of the four A/D inputs.

This means all 32 receiver channels onboard can independently select which A/Dor antenna they are looking at. This providesa very dynamic antenna-to-channel assign-ment scheme for systems that need toadapt to changing traffic patterns.

The digital outputs of two A/D convert-ers are delivered directly into each FPGA.

This allows wideband A/D data to streamdirectly through the FPGA to the DSP sincethe high bandwidth of the VIM interfacesupports clock rates up to 100 MHz.

Even more important, it also allows theFPGA to handle signal processing algo-rithms on the raw A/D data before it goesto the processor, again, to offload some ofits tasks. After handling the factory standardfunctions of data formatting and control, ahigh percentage of these resources is stillavailable for custom applications.

The factory default code takes care of allthe basic functions for most applications

including selection of channels for deliveryto the DSP board, selection of real or complexdata modes, selection of receiver data or rawA/D data, and selection of data packingmodes. For custom signal processing tasks,

the optional design kit for each prod-uct includes the VHDL source codefor all these standard factory defaultmodes.

Users can extend the factory codeby adding their own algorithms atappropriate points in the signalflow path. FPGA algorithms can bedeveloped and simulated by draw-

ing on the Pentek GateFlow DesignKit and on the wealth of IP cores anddesign tools available for thesedevices. Once compiled, the customcode can be downloaded throughutility loaders into a non-volatile usermemory on the board.

FPGAs are successfully tak-ing up many of the roles

formerly played by DSPs and

ASICs. One of the major benefitsof the IP core concept is that,like high-level languages, thesecores can migrate to the next

generation devices. This meansthat the wealth of core functionscan accumulate and diversify,eliminating the need to startover again for each new family.

Pentek offers the GateFlowcollection of FPGA Resources,compatible with the XilinxVirtex products.

GateFlow includes the FPGA

Design Kit which allows theengineer to implement customalgorithms and signal process-ing functions.

The GateFlow IP Core Libraryis a collection of highly optimizedPentek IP Cores for implement-ing functions such as FFTs andDigital Receivers on any Xilinx

FPGA platform.The GateFlow Installed

Cores are high-performancesignal processing functionsinstalled at the factory in the

FPGAs of Pentek boards.

Figure 2. 32-Channel softwareradio system.

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