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FPGA Setup for NVMe-IP demo · 2 Demo setup 1) Power off system. 2) Check DIP switch setting for...
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dg_nvmeip_fpgasetup_xilinx_en.doc 22-Dec-20 Page 1 FPGA Setup for NVMe-IP/NVMeG3-IP/NVMeG4-IP demo Rev4.2 22-Dec-20 This document describes the FPGA and environment setup for running NVMe-IP, NVMeG3-IP or NVMeG4-IP demo on FPGA development board by using the PCIe adapter board (AB18-PCIeX16, AB17-M2FMC or AB16-PCIeXOVR adapter board) with NVMe SSD. User controls the test operation via Serial console. 1 Environment Requirement To run the demo on FPGA development board, please prepare following environment. 1) Supported FPGA Development board: NVMe-IP : AC701, ZC706, VC707, KCU105, KCU116, ZCU106 or VCU118 NVMeG3-IP : KCU105, KCU116, ZCU102, ZCU106 or VCU118 NVMeG4-IP : KCU116, ZCU102, ZCU106 or VCU118 2) PC installing Xilinx programmer software (Vivado) and Serial console software such as HyperTerminal or TeraTerm 3) The PCIe adapter board (AB18-PCIeX16, AB17-M2FMC or AB16-PCIeXOVR adapter board) provided by Design Gateway https://dgway.com/ABseries_E.html 4) Xilinx power adapter for FPGA board 5) ATX power supply for AB18-PCIeX16 adapter board 6) NVMe SSD connecting with PCIe adapter board 7) One micro USB cable for programming FPGA, connecting between FPGA board and PC 8) One mini/micro USB cable for Serial console, connecting between FPGA board and PC Figure 1-1 NVMe-IP demo environment setup on VC707 (PCIe Gen2)
Transcript of FPGA Setup for NVMe-IP demo · 2 Demo setup 1) Power off system. 2) Check DIP switch setting for...
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FPGA Setup for NVMe-IP/NVMeG3-IP/NVMeG4-IP demo Rev4.2 22-Dec-20
This document describes the FPGA and environment setup for running NVMe-IP, NVMeG3-IP or NVMeG4-IP demo on FPGA development board by using the PCIe adapter board (AB18-PCIeX16, AB17-M2FMC or AB16-PCIeXOVR adapter board) with NVMe SSD. User controls the test operation via Serial console.
1 Environment Requirement
To run the demo on FPGA development board, please prepare following environment. 1) Supported FPGA Development board:
NVMe-IP : AC701, ZC706, VC707, KCU105, KCU116, ZCU106 or VCU118 NVMeG3-IP : KCU105, KCU116, ZCU102, ZCU106 or VCU118 NVMeG4-IP : KCU116, ZCU102, ZCU106 or VCU118
2) PC installing Xilinx programmer software (Vivado) and Serial console software such as HyperTerminal or TeraTerm
3) The PCIe adapter board (AB18-PCIeX16, AB17-M2FMC or AB16-PCIeXOVR adapter board) provided by Design Gateway https://dgway.com/ABseries_E.html
4) Xilinx power adapter for FPGA board 5) ATX power supply for AB18-PCIeX16 adapter board 6) NVMe SSD connecting with PCIe adapter board 7) One micro USB cable for programming FPGA, connecting between FPGA board and PC 8) One mini/micro USB cable for Serial console, connecting between FPGA board and PC
Figure 1-1 NVMe-IP demo environment setup on VC707 (PCIe Gen2)
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Figure 1-2 NVMe-IP demo environment setup on ZC706 (PCIe Gen2)
Figure 1-3 NVMe-IP demo environment setup on AC701 (PCIe Gen2)
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Figure 1-4 NVMe-IP/NVMeG3-IP demo environment setup on KCU105 with AB18 (PCIe Gen3)
Figure 1-5 NVMe-IP demo environment setup on KCU105 with AB17 (PCIe Gen3)
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Figure 1-6 NVMe-IP/NVMeG3-IP/NVMeG4-IP demo environment setup on KCU116
with AB18 (PCIe Gen3/Gen4)
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Figure 1-7 NVMeG3-IP/NVMeG4-IP demo environment setup on ZCU102
with AB17 (PCIe Gen3/Gen4)
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Figure 1-8 NVMe-IP/NVMeG3-IP/NVMeG4-IP demo environment setup on ZCU106
with AB18 (PCIe Gen3/Gen4)
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Figure 1-9 NVMe-IP/NVMeG3-IP/NVMeG4-IP demo environment setup on ZCU106
with AB17 (PCIe Gen3/Gen4)
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Figure 1-10 NVMe-IP/NVMeG3-IP/NVMeG4-IP demo environment setup on VCU118
with AB18 (PCIe Gen3/Gen4)
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Figure 1-11 NVMe-IP/NVMeG3-IP/NVMeG4-IP demo environment setup on VCU118
with AB17 (PCIe Gen3/Gen4)
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2 Demo setup
1) Power off system. 2) Check DIP switch setting for JTAG configuration on Zynq board.
• For ZC706 board, set SW11=all OFF to configure PS from JTAG and set SW4[1:2]=[OFF ON] to connect JTAG with USB-to-JTAG interface, as shown in Figure 2-1.
Figure 2-1 SW11 setting to configure PS from JTAG on ZC706
• For ZCU106/ZCU102 board, set SW6=all ON to configure PS from JTAG, as shown in Figure 2-2.
Figure 2-2 SW6 setting to configure PS from JTAG on ZCU106
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3) Setup and connect NVMe SSD to PCIe adapter board.
For AB18-PCIeX16 and AB16-PCIeXOVR, a) Confirm that two mini jumpers are inserted at J5 connector on AB18. b) Connect ATX power supply to AB board. c) Connect PCIe connector on FPGA board to FPGA Side (A-side) and connect NVMe
PCIe SSD to device side (B-Side) on AB board, as shown in Figure 2-3 Warning: Please confirm that the SSD is inserted in the correct side of AB18 (B-side, not A-side) before power on system.
Figure 2-3 Setup AB18-PCIeX16 connection
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For AB17-M2FMC, a) Connect M.2 NVMe SSD to Drive#1 M.2 connector on AB17-M2FMC. b) Connect AB17-M2FMC to HPC/HPC1 connector on KCU105(J22), ZCU106(J5),
ZCU102(J4) or HSPC on VCU118 (J22), as shown in Figure 2-4
Figure 2-4 Setup AB17-M2FMC connection
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4) Connect USB cables for JTAG programming and Serial console.
a) For AC701/VC707/ZC706, connect micro USB cable for JTAG and mini USB cable for Serial console.
b) For KCU105/KCU116/ZCU106/VCU118, connect two micro USB cables for JTAG and Serial console.
Figure 2-5 USB cable connection
5) Power on FPGA development board and adapter board, as shown in Figure 2-6.
Figure 2-6 Turn on power switch on FPGA and adapter board
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6) After connecting USB cables to PC, additional COM port is detected. For
Ultrascale/Ultrascale+ board, many COM ports are detected. In case of KCU105, KCU116 and VCU118, select Standard COM port. In case of ZCU106, select the lowest number for ZCU106 board. On Serial console, set Buad rate=115,200, Data=8-bit, Non-Parity and Stop = 1, as shown in Figure 2-7.
Figure 2-7 Select and set COM port
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7) For AB17-M2FMC connection on KCU105 or VCU118 board, user must set VADJ on FMC
connector as following step.
For KCU105 board, open Serial console to connect with Enhanced COM port (Buad rate=115,200 Data=8 bit Non-Parity Stop=1). The console shows System Controller menu, as shown in Figure 2-8. To set VADJ of FMC to 1.8V, the following step is recommended. a) Input ‘4’ to select Adjust FMC Settings. b) Input ‘4’ to set FMC VADJ to 1.8V. c) Input ‘0’ to return to Main Menu. d) Input ‘2’ to get PMBUS Voltages. e) Input ‘7’ to get VADJ1V8 Voltage. The output voltage of this menu must be equal to
1.8V to confirm that VADJ has been set completely.
For more details of System Controller, please check “UG917 KCU105 Board User Guide” in section “Appendix C: System Controller”. https://www.xilinx.com/support/documentation/boards_and_kits/kcu105/ug917-kcu105-eval-bd.pdf
Figure 2-8 Setting VADJ of FMC for KCU105
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For VCU118 board, open SCUI.exe and run following step. a) Select File->Change the System Controller Port. b) Select COM port number which is Enhanced COM Port. c) Click “OK” button to confirm the port. d) Select FMC tab -> Set VADJ tab -> Current tab. Click “Set VADJ to 1.8V” button. e) Select Voltages tab and click “Get VADJ_1V8 Voltage” button. The output voltage
must be equal to 1.8V to confirm that VADJ has been set completely.
System controller tool (SCUI.exe) can be downloaded from Xilinx website. https://www.xilinx.com/products/boards-and-kits/vcu118.html#documentation
Direct link for SCUI.exe on Vivado2017.4. https://www.xilinx.com/member/forms/download/design-license.html?cid=07015756-bc89-402c-9308-2be69db6f96c&filename=rdf0396-vcu118-system-controller-c-2017-4.zip
Figure 2-9 Setting VADJ of FMC for VCU118
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8) Download and program configuration file and firmware to FPGA board.
For AC701, VC707, KCU105, KCU116 and VCU118, configure FPGA by using Vivado, as shown in Figure 2-10.
Figure 2-10 Program FPGA by Vivado
For ZC706, ZCU106 or ZCU102 board, open Vivado TCL shell and run NVMeIPTest_xxx.bat, NVMeG3IPTest_xxx.bat or NVMeG4IPTest_xxx.bat as shown in Figure 2-11.
Figure 2-11 Command script to download demo file on Vivado TCL shell
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9) Check LED status on FPGA board. The description of LED is as follows.
Table 2-1 LED Definition
GPIO LED ON OFF
0 Normal operation Clock is not locked or reset button is pressed 1/R System is busy Idle status 2/C IP Error detect Normal operation 3/L Data verification fail Normal operation
10) After programming completely, LED[0] and LED[1] are ON during PCIe initialization
process. Then, LED[1] changes to OFF after PCIe completes initialization process.
Figure 2-12 LED status after program configuration file and PCIe initialization complete
11) Main menu is displayed on Serial console. Now it is ready to receive command from the
user.
Figure 2-13 Main menu after IP finishes initialization
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3 Revision History
Revision Date Description
1.0 2-Jun-16 Initial version release
4.0 29-Jun-20 Remove instruction from the document and include NVMeG3-IP
4.1 27-Aug-20 Support KCU116
4.2 22-Dec-20 Support NVMeG4-IP
