FPGA Programming Language Verilog HDL VHDL • Types of Verilog ... consortium of companies and...

• FPGA Programming Language: Verilog HDL

and VHDL

• Types of Verilog coding style.

• Grammar of Verilog HDL.

FPGA Programming Language

Verilog HDL

Prepared By-

Mohammed Abdul Kader

Lecturer, EEE, IIUC

Lecture Materials on "Verilog HDL", By- Mohammed Abdul Kader, Lecturer, EEE, IIUC 2

In FPGA it is possible to build digital circuits of any complexity simply by configuring and connecting

CLB’s and this is done by programming.

Two popular ways to accomplish this are-

(a) Schematic entry and

(b) HDLs (Hardware Description language).

Before HDLs were popular, engineers used to design everything with schematics. Schematics are

wonderfully easy for small designs, but are painfully unmanageable for a large design (think about

Intel engineers drawing schematics for Pentium, which has millions of gates! it is unacceptably

complex).

There are different types of HDL. Some of it are vendor dependent where the HDL code is only

usable under the software provided by the specific vendor. For example, AHDL (Altera hardware

description language) from altera company, Lola (Logic Language) from European Silicon Structure

(ES2) company etc. are some example of vendor dependent HDL tools.

The most popular, widely accepted industry standard and vendor independent HDL tool for digital

system design are-

(a) Verilog HDL

(b) VHDL (Very high speed Hardware Description Language).

FPGA Programming Language


Verilog HDL and VHDL

Verilog HDL is introduced by Cadence Data Systems, Inc and later its control is transferred to a

consortium of companies and universities known as Open Verilog International (OVI) where as

VHDL is used primarily by defense contractors.

VHDL is popular in European countries whereas Verilog HDL is widely used in Asia and America.

Currently Verilog HDL is used by the famous IC design companies such as Motorolla, Intel etc.

Verilog HDL is IEEE standard and easier than VHDL. In VHDL libraries to be used for a program

have to be declared whereas it is not necessary in Verilog HDL programming. It is less error prone.

It has many pre-defined features very specific to IC Design.

FPGA Programming

Schematic Entry Hardware Description

language

Verilog HDL VHDL


Types of Verilog Coding Style

There are three types of Verilog coding style as follows:

RTL Verilog Code: Digital circuit can be represented in different ways such as gate level

representation, transistor level representation etc. RTL, acronym of Register Transfer Level, is also

another type of representation style for digital circuit. The reason why it is named as RTL is that any

complex digital system can be partitioned into different modules where each module is basically

consists of registers and gates. Information is stored in the register and specific operation is performed

using the information, and then it is transferred among the register.

For Example, we may define an addition event : X=A+B; It means that the sum of the content of

register A and register B is transferred to the storage device X. Figure shows the example of RTL code

of a 2/1 Mux.


Types of Verilog Coding Style (Cont.)

Structural Verilog Code: It describe the components and interconnections present in a design.

Electronic design Automation (EDA) tool compiles and synthesizes the RTL code of a design and

produces the netlist of the design in the form of structural code.

The example of structural code for a circuit of 2/1 Mux is shown below-


Types of Verilog Coding Style (Cont.)

Behavioral Verilog Code: Behavioral code describes the functionality and behavior of the

functional block diagram of a design. It is often used for system level modeling and simulation of a

design. An example of behavioral Verilog code (using fork and join) shown below. Usually many of the

commands in behavioral code are not synthesizable. For example, wait command as shown below. The

code length of a design is much smaller than to write for RTL code of the same design because it is only

for simulation purpose.


Grammar of Verilog HDL Convention and Syntax used in Verilog HDL are very much similar to those in C programming

language.

Identifiers

Identifiers are the names to give for an object (such as input, output, module etc) in the design. It

must start with a letter or underscore (a-z, A-Z, _).

Identifiers may contain alphabetic characters, numeric characters, the underscore and the doller

sign (a-z, A-Z, 0-9, _, $).

Never use the Verilog keywords as identifier.

Identifier can be up to 1024 character long.

Keywords

Verilog has a number of keywords or reserve words that can not be used as identifiers or any other

purpose than it is identified for.

All keywords are used in lower case in the Verilog code.

Some important keywords are given below-


Grammar of Verilog HDL (Cont.) So

me

im

po

rtan

t k

eyw

ord

s


Som

e i

mp

ort

ant

key

wo

rds

Grammar of Verilog HDL (Cont.)



Case Sensitivity

Verilog is a case sensitive language. Lower case letters are unique from upper case letters. All Verilog

keywords are lower case.

Comments

Comment is written for clarification and can be used anywhere in the program. Single line comments

starts with ‘//’ and multiple line comment starts with ‘/*’ and ends with ‘*/’.

Example:

Single line comment: //This is a single line comment.

Multiple line comment: /* This is a multiple line comment

where more than one line is needed */

White Space

White spaces are- Blank spaces, Tabs, New-line, Carriage returns etc. It is used to make code more

readable. Verilog is not a white space-sensitive language except inside quotes.


Escaped Identifiers

Verilog HDL allows any character to be used in an identifier by escaping the identifier. Escaped

identifiers provide a means of including any of the printable ASCII characters in an identifier.

Escaped identifiers begin with the back slash ( \ ). Entire identifier is escaped by the back slash.

Escaped identifier is terminated by white space (Characters such as commas, parentheses, and

semicolons become part of the escaped identifier unless preceded by a white space)

Example of escape identifiers: Verilog does not allow to identifier to start with a numeric

character. So if you really want to use a identifier to start with a numeric value then use a escape

character as shown below.



Numbers in Verilog

You can specify constant numbers in decimal, hexadecimal, octal, or binary format. Negative numbers

are represented in 2's complement form. When used in a number, the question mark (?) character is the

Verilog alternative for the z character. The underscore character (_) is legal anywhere in a number except

as the first character, where it is ignored.

• Verilog expands <value> filling the specified <size> by working from right-to-left.

• When <size> is smaller than <value>, then leftmost bits of <value> are truncated.

• X Stands for unknown and Z stands for high impedance, 1 for logic high or 1 and 0 for logic low or 0.

Integer Numbers

Verilog HDL allows integer numbers to be specified as-

• Radix and hex digits (a,b,c,d,e,f) are case

insensitive.

• Spaces are allowed between the size, radix and

value.

• Sized or unsized numbers (Unsized size is 32 bits).

• In a radix of binary, octal, decimal, or hexadecimal.

Syntax: <size>'<radix><value>;



Real Numbers

•Verilog supports real constants and variables

•Verilog converts real numbers to integers by rounding

•Real Numbers can not contain 'Z' and 'X'

•Real numbers may be specified in either decimal or scientific notation

< value >.< value > OR < mantissa >E< exponent >

•Real numbers are rounded off to the nearest integer when assigning to an integer.

Signed and Unsigned Numbers

Verilog Supports both types of numbers, but with certain restrictions. Like in C language we don't have

int and unint types to say if a number is signed integer or unsigned integer.

Any number that does not have negative sign prefix is a positive number. Or indirect way would be

"Unsigned".

Negative numbers can be specified by putting a minus sign before the size for a constant number, thus

they become signed numbers. Verilog internally represents negative numbers in 2's complement format.



Verilog Operators


FPGA Programming Language Verilog HDL VHDL • Types of Verilog ... consortium of companies and...

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