Fpga Implementation of Memory Controller Fsm Using Simulink2

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FPGA Implementation of Memory Controller FSM using simulink

Project report submitted in partial fulfillment of the requirement for the award of the Degree

of B.Tech

By

A. DEEPAK KUMAR08BD1A0402

K. R. BHARAT RAM-08BD1A0425

K.RANADHEER REDDY-08BD1A0423

Department of Electronics and Instrumentation Engineering

Keshav Memorial Institute of Technology

(Affiliated to Jawaharlal Nehru Technological University)

Hyderabad


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Certificate

This is to certify that the project report entitled being submitted by Mr/Mrs.. in

partial fulfillment for the award of the Degree of Bachelor of Technology in tothe Jawarlal Nehru Technological University is a record of bonafied work carried out by him

under my guidance and supervision.

The results embodied in this project report have not been submitted to any other University or

Institute for the award of any Degree or Diploma.

(HOD) Guide Name

Designation


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CERTIFICATE

ACKNOWLEDGEMENT


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ABSTRACT

A finite-state machine (FSM) or simply astate machine, is a mathematical model used to

design computer programs and digital logic circuits. It is conceived as an abstract machine that

can be in one of a finite number ofstates. The machine is in only one state at a time; the state itis in at any given time is called the current state. It can change from one state to another when

initiated by a triggering event or condition, this is called a transition. A particular FSM is defined

by a list of the possible states it can transition to from each state, and the triggering condition for

each transition.

Finite-state machines can model a large number of problems, among which are electronic design

automation, communication protocol design, parsing and other engineering applications. In

biology and artificial intelligence research etc.

Simulink software models, simulates, and analyzes dynamic systems. It enables you to pose a

question about a system, model the system, and see what happens. With Simulink, you can easilybuild models from scratch, or modify existing models to meet your needs. Simulink supports

linear and nonlinear systems, modeled in continuous time, sampled time, or a hybrid of the two.

Simulink HDL Coder software lets you generate hardware description language (HDL) code

based on Simulink models and Stateflow finite-state machines. The coder brings the Model-

Based Design approach into the domain of application-specific integrated circuit (ASIC) and

field programmable gate array (FPGA) development. Using the coder, system architects anddesigners can spend more time on fine-tuning algorithms and models through rapid prototyping

and experimentation and less time on HDL coding.

we use a Simulink model to simulate a design intended for realization as an ASIC or FPGA.

Once satisfied that the model meets design requirements, you run the Simulink HDL Codercompatibility checker utility to examine model semantics and blocks for HDL code generation

compatibility. You then invoke the coder, using either the command line or the graphical user

interface. The coder generates VHDL or Verilog code that implements the design embodied inthe model.
http://en.wikipedia.org/wiki/Abstract_machinehttp://en.wikipedia.org/wiki/Abstract_machinehttp://en.wikipedia.org/wiki/Abstract_machinehttp://en.wikipedia.org/wiki/Mathematical_modelhttp://en.wikipedia.org/wiki/Computer_programshttp://en.wikipedia.org/wiki/Digital_logichttp://en.wikipedia.org/wiki/State_%28computer_science%29http://en.wikipedia.org/wiki/State_%28computer_science%29http://en.wikipedia.org/wiki/State_%28computer_science%29http://en.wikipedia.org/wiki/Electronic_design_automationhttp://en.wikipedia.org/wiki/Electronic_design_automationhttp://en.wikipedia.org/wiki/Communication_protocolhttp://en.wikipedia.org/wiki/Parsinghttp://en.wikipedia.org/wiki/Biologyhttp://en.wikipedia.org/wiki/Artificial_intelligencehttp://en.wikipedia.org/wiki/Artificial_intelligencehttp://en.wikipedia.org/wiki/Biologyhttp://en.wikipedia.org/wiki/Parsinghttp://en.wikipedia.org/wiki/Communication_protocolhttp://en.wikipedia.org/wiki/Electronic_design_automationhttp://en.wikipedia.org/wiki/Electronic_design_automationhttp://en.wikipedia.org/wiki/State_%28computer_science%29http://en.wikipedia.org/wiki/Digital_logichttp://en.wikipedia.org/wiki/Computer_programshttp://en.wikipedia.org/wiki/Mathematical_modelhttp://en.wikipedia.org/wiki/Abstract_machine


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CONTENTS

1. INTRODUCTION

2. FSM

2.1 INTRODUCTION TO FSM

2.2 BLOCK DIAGRAM OF FSM

2.3 MEALY MACHINE

2.4 MOORE MACHINE

2.5 MEMORY CONTROLLER FSM

2.6APPLICATIONS OF FSM

2.6.1 HARWARE APPLICATIONS

2.6.2 SOFTWARE APPLICATIONS

2.7 ADVANTAGES OF FSM

2.8 DISADVANTAGES OF FSM

3. HARWARE AND SOFTWARE USED

3.1 SOFTWARE

3.1.1 MATLAB

3.1.2 SIMULINK

3.1.3 XILINX

3.1.4 VERILOG

4. IMPLEMENTATION OF FSM USING SIMULINK

4.1 MAIN BLOCK DIAGRAM IN SIMULINK

4.2 MEALY BLOCK DIAGRAM IN SIMULINK

4.3 MOORE BLOCK DIAGRAM IN SIMULINK

5. RESULTS

5.1 CODING


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5.1.1 MEALY MACHINE CODE

5.1.2 MOORE MACHINE CODE

5.1.3 MEMORY CONTROLLER CODE


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CHAPTER 1

INTRODUCTION


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1 INTRODUCTION

At a low level of abstraction, a protocol is often most easily understood as a state machine.Design criteria can also easily be expressed in terms of desirable or undesirable protocol states and state transitions.

In a way, the protocol state symbolizes the assumptions that each process in the system makes about the others. It

defines what actions a process is allowed to take, which events it expects to happen, and how it will respond to those

events.

The formal model of a communicating finite state machine plays an important role in

three different areas of protocol design: formal validation, protocol synthesis, and

conformance testing. This chapter introduces the main concepts. First the basic finite

state machine model is discussed. There are several, equally valid, ways of extending this basic model into a model

for communicating finite state machines. We select one of those models and formalize it in a definition of a

generalized communicating finite state machine. The model can readily be applied to represent PROMELA

specifications and to build an automated validator.

There exist many variations of the basic finite state machine model. Rather than list

them all, we conclude this chapter with a discussion of two of the more interesting

examples: the Petri Net and the FIFO Net.


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CHAPTER 2

FINITE STATE MACHINE


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2 FINITE STATE MACHINE

2.1 INTRODUCTION TO FINITE STATE MACHINES

It is a generic model for sequential circuits used in sequential circuit design .

In general, a state machine is any device that stores the status of something at a given time and

can operate on input to change the status and/or cause an action or output to take place for any

given change. A computer is basically a state machine and each machine instruction is input that

changes one or more states and may cause other actions to take place. Each computer's data

register stores a state. The read-only memory from which a boot program is loaded stores a state

(the boot program itself is an initial state). The operating system is itself a state and eachapplication that runs begins with some initial state that may change as it begins to handle input.

Thus, at any moment in time, a computer system can be seen as a very complex set of states and

each program in it as a state machine. In practice, however, state machines are used to develop

and describe specific device or program interactions.

To summarize it, a state machine can be described as:

An initial state or record of something stored someplace A set of possible input events

A set of new states that may result from the input A set of possible actions or output events that result from a new state

In their bookReal-time Object-oriented Modeling, Bran Selic & Garth Gullekson view a statemachine as:

A set of input events A set of output events A set of states A function that maps states and input to output A function that maps states and inputs to states (which is called a state transition

function)

A description of the initial stateA finite state machine is one that has a limited or finite number of possible states. (An infinite

state machine can be conceived but is not practical.) A finite state machine can be used both as a

development tool for approaching and solving problems and as a formal way of describing thesolution for later developers and system maintainers. There are a number of ways to show state

machines, from simple tables through graphically animated illustrations.


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FSM: Formal definition

An FSM is a quintuple: (X, Y, Q, q0, , O), where:

X is a finite set of input symbols also known as the input alphabet.Y is a finite set of output

symbols also known as the output alphabet,Q is a finite set of states,q0 in Q is the initial state,

: Q x XQ is a next-state or state transition function, and O: Q x XY is an output function.In some variants of FSM more than one state could be specified as an initial state. Also,

sometimes it is convenient to add FQ as a set of final or accepting states while specifying anFSM.

State diagram representation of FSMA state diagram is a directed graph that contains nodes representing states and edges representing

state transitions and output functions. Each node is labeled with the state it represents. Each

directed edge in a state diagram connects two states. Each edge is labeled i /o where i denotes aninput symbol that belongs to the input alphabet X and o denotes an output symbol that belongs to

the output alphabet O. i is also known as the input portion of the edge and o its output portion.

Tabular representation of FSM :

A table is often used as an alternative to the state diagram to represent the state transition

function and the output function O. The table consists of two sub-tables that consist of one ormore columns each. The leftmost sub table is the output or the action sub-table. The rows are

labeled by the states of the FSM. The rightmost sub-table is the next state sub-table.


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Properties of FSM :

Completely specified: An FSM M is said to be completely specified if from each state in M there

exists a transition for each input symbol.

Strongly connected: An FSM M is considered strongly connected if for each pair of states (qi qj)

there exists an input sequence that takes M from state qi to qj.

STATE DIAGRAM :

The design of an FSM normally starts with an abstract, graphic description, such as astate diagram or an ASM chart. Both descriptions utilize symbolic state notations, show thetransition among the states and indicate the output values under various conditions. A statediagram or an ASM chart can capture all the needed information (i.e., state, input, output, next-state function, and output function) in a single graph.

.

A state diagram consists of nodes, which are drawn as circles (also known as bubbles), and one-direction transition arcs. The notation for nodes and arcs is shown in Figure 10.2. A noderepresents a unique state of the FSM and it has a unique symbolic name. An arc represents atransition from one state to another and is labeled with the condition that will cause thetransition. The condition is expressed as a logic expression composed of input signals. An arcwill be taken when the corresponding logic expression is evaluated to be logic '1'.


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The output values are also specified on the state diagram. The Moore output is a function of stateand thus is naturally placed inside the state bubble. On the other hand, the Mealy output dependson both state and input and thus is placed under the condition expression of the transition arcs. Toreduce the clutter, we list only the output signals that are activated or asserted. An output signalwill assume the default, unasserted value (notdon't-care) if it is not listed inside the state bubbleor under the logic expression of an arc. We use the

following notation for an asserted output value:

signal_name


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Edges : represent transitions from one state to another as caused by the input (identifiedby their symbols drawn on the edges). An edge is usually drawn as an arrow directed from

the present state to the next state. This mapping describes the state transition that is to occur

on input of a particular symbol. This is written mathematically as : Q Q, so by

(transition function) in the definition of the FA is given both the pair of vertices connected

by an edge and the symbol on an edge in a diagram representing this FA. Item (q,a)= p in

the definition of the FA means that from the state named q under input symbol a, the

transition to the state p occurs in this machine. In the diagram representing this FA, this is

represented by an edge labeled by a pointing from the vertex labeled by q to the vertex

labeled by p.

Start state q0: (not shown in the examples below). The start state q0 Q is usuallyrepresented by an arrow with no origin pointing to the state. In older texts, the start state is

not shown and must be inferred from the text.

Accepting state(s) F: If used, for example for accepting automata, F Q is the acceptingstate. It is usually drawn as a double circle. Sometimes the accept state(s) function as " Final"

(halt, trapped) states.

For a deterministic finite automaton (DFA), nondeterministic finite

automaton (NFA), generalized nondeterministic finite automaton (GNFA), or Moore machine,

the input is denoted on each edge. For a Mealy machine, input and output are signified on eachedge, separated with a slash "/": "1/0" denotes the state change upon encountering the symbol "1"

causing the symbol "0" to be output. For a Moore machine the state's output is usually written

inside the state's circle, also separated from the state's designator with a slash "/". There are also

variants that combine these two notations.

For example, if a state has a number of outputs (e.g. "a= motor counter-clockwise=1, b= caution

light inactive=0") the diagram should reflect this : e.g. "q5/1,0" designates state q5 with outputs

a=1, b=0. This designator will be written inside the state's circle.

Example: DFA, NFA, GNFA, or Moore machine

S1 and S2 are states and S1 is an accepting state or a final state. Each edge is labeled with theinput. This example shows an acceptor for strings over {0,1} that contain an even number of

zeros.


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[Example: Mealy machine

S0, S1, and S2 are states. Each edge is labeled with "j /k" wherej is the input and kis the

output.

ASM CHART

An algorithmic state machine (ASM) chart is an alternative method for representing an FSM.Although an ASM chart contains the same amount of information as a state diagram, it is moredescriptive. We can use an ASM chart to specify the complex sequencing of events involvingcommands (input) and actions (output), which is the hallmark of complex algorithms. An ASMchart representation can easily be transformed to VHDL code. It can also be extended to describeFSMD (FSM with a data path), which is discussed in the next two chapters.

An ASM chart is constructed of a network of ASM blocks. An ASM blockconsists of onestate box and an optional network of decision boxes and conditional output boxes. A typicalASM block is shown in Figure 10.4. The state box, as its name indicates, represents a state in anFSM. It is identified by a symbolic state name on the top left corner of the state box. The action oroutput listed inside the box describes the desired output signal values when the FSM enters thisstate. Since the outputs rely on the state only, they correspond to the Moore outputs of the FSM.To reduce the clutter, we list only signals that are activated or asserted. An output signal willassume the default, unasserted value if it is not listed

inside the box. We use the same notation for an asserted output signal:
http://en.wikipedia.org/wiki/File:DFAexample.svghttp://en.wikipedia.org/wiki/File:Mealymachine_jaredwf.pnghttp://en.wikipedia.org/wiki/File:DFAexample.svg


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signal_name b) and (c /= 1). Depending on the value of the Boolean expression, the FSM can follow eitherthe true path or the false path, which are labeled as T or F in the exit paths of the decision box. Ifnecessary, we can cascade multiple decision boxes inside an ASM block to describe a complexcondition.

A conditional output box also lists asserted output signals. However, it can only be placedafter an exit path of a decision box. It implies that these output signals can be asserted only if thecondition of the previous decision box is met. Since the condition is composed of a Booleanexpression of input signals, these output signals' values depend on the current state and inputsignals, and thus they are Mealy outputs. Again, to reduce clutter, we place a conditional outputbox in an ASM block only when the corresponding output signal is asserted. The output signalassumes the default, unasserted value when there is no conditional output box.

Since an ASM chart is another way of representing an FSM, an ASM chart can be converted

to a state diagram and vice versa. An ASM block corresponds to a state and its transition arcs of astate diagram. The key for the conversion is the transformation between the logic expressions ofthe transition arcs in a state diagram and the decision boxes in an ASM chart.

Since an ASM chart is used to model an FSM, two rules apply:

1. For a given input combination, there is one unique exit path from the current ASM

block.


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2. The exit path of an ASM block must always lead to a state box. The state box can be

the state box of the current ASM block or a state box of another ASM block.

The conversion can best be explained by examining several examples. The first example is

shown below. It is an FSM with no branching arches. The state diagram and the ASM chart arealmost identical.

The second example is also shown below . The FSM has two transition arcs from the

s0 state and has a Mealy output, y. The logic expressions a and a of the transition arches

are translated into a decision box with Boolean expression a = 1. Note that the two states

are transformed into two ASM blocks. The decision and conditional output boxes are not new

states, just actions associated with the ASM block s0.


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ADVANTAGE OF ASM CHART OVER STATE DIAGRAM

The output of the FSM is more complex and depends on various input

conditions. The state diagram needs multiple logic expressions in the transition arc to express

various input conditions. The ASM chart can accommodate the situation and is more descriptive.

2.2 BLOCK DIAGRAM OF FSM

2.2.1 GENERAL BLOCK DIAGRAM

NEXT STATE

LOGIC

Q

QSET

CLR

D

Q

QSET

CLR

D

.

.

.

STATE MEMORY

OUTPUT LOGIC

CLK

INPUTS

PREVIOUS STATE

NEXT

STATE

OUTPUTS


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The block diagram of an FSM is shown below . It is similar to the block diagram of a regularsequential circuit. The state register is the memory element that stores the state of the FSM. It is

synchronized by a global clock. The next-state logic implements the next-state function, whoseinput is the current state and input signals. The output logic implements the output function.This diagram includes both Moore output logic, whose input is the current state, and Mealyoutput logic, whose input is the current state and input signals. The main application of an FSMis to realize operations that are performed in a sequence of steps. A large digital system usuallyinvolves complex tasks or algorithms, which can be expressed as a sequence of actions based onsystem status and external commands. An FSM can function as the control circuit (known as the control path) that coordinates and governs the operations of other units (known as the data path)of the system. Our coverage of FSM focuses on this aspect. The actual construction of suchsystems is discussed in the next two chapters. FSMs can also be used in many simple tasks, suchas detecting a unique pattern from an input data stream or generating a specific sequence of outputvalues.

It is similar to the block diagram of a regular sequential circuit. The state register is the memoryelement that stores the state of the FSM. It is synchronized by a global clock. The next-state logicimplements the next-state function, whose input is the current state and input signals. The outputlogic implements the output function. This diagram includes both Moore output logic, whoseinput is the current state, and Mealy output logic, whose input is the current state and inputsignals. The main application of an FSM is to realize operations that are performed in a sequenceof steps. A large digital system usually involves complex tasks or algorithms, which can beexpressed as a sequence of actions based on system status and external commands. An FSM canfunction as the control circuit (known as the control path) that coordinates and governs theoperations of other units (known as the data path) of the system. Our coverage of FSM focuses onthis aspect. The actual construction of such systems is discussed in the next two chapters. FSMscan also be used in many simple tasks, such as detecting a unique pattern from an input data

stream or generating a specific sequence of output values.

2.2.2 BLOCK DIAGRAM USING MEALY AND MOORE OUTPUT LOGIC


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State memory: Set ofn flip-flops that hold the state of the machine (up to 2^n distinctstates).

Next state logic: Combinational circuit that determines the next state as a function of thecurrent state and the input.

Output logic: Combinational circuit that determines the output as a function of the currentstate and the input.

2.3 MEALY MACHINE

FORMAL DEFINITION

A Mealy machine is a 6-tuple, (S, S0, , ,T, G), consisting of the following:

a finite set of states (S) a start state (also called initial state) S0 which is an element of (S)


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a finite set called the input alphabet () a finite set called the output alphabet () a transition function (T: S S) mapping pairs of a state and an input symbol to the

corresponding next state.

an output function (G : S ) mapping pairs of a state and an input symbol to thecorresponding output symbol.

In some formulations, the transition and output functions are coalesced into a single function

(T: S S ).

STATE DIAGRAM OF MEALY MACHINE

STATE TABLE OF MEALY MACHINE


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BLOCK DIAGRAM OF MEALY MACHINE

Mealy machine is a finite state machine , whose output values are determined solely byits current state and current inputs.

Accordingly, the outputs may change asynchronously in response to any

change in the inputs.


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SIMPLE MEALY MACHINE

Simple Mealy machine has one input and one output. Each transition edge is labeled with the

value of the input (shown in red) and the value of the output (shown in blue). The machine starts

in state Si. (In this example, the output is theexclusive-orof the two most-recent input values;thus, the machine implements an edge detector, outputting a one every time the input flips and a

zero otherwise.)

State diagram for a simple Mealy machine with one input and one output.

COMPLEX MEALY MACHINE

More complex Mealy machines can have multiple inputs as well as multiple outputs.

2.4 MOORE MACHINE
http://en.wikipedia.org/wiki/Exclusive_orhttp://en.wikipedia.org/wiki/Exclusive_orhttp://en.wikipedia.org/wiki/Exclusive_orhttp://en.wikipedia.org/wiki/State_diagramhttp://en.wikipedia.org/wiki/State_diagramhttp://en.wikipedia.org/wiki/Exclusive_or


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FORMAL DEFINITION

A Moore machine can be defined as a 6-tuple ( S, S0, , ,T, G ) consisting of the following:

a finite set of states ( S ) a start state (also called initial state) S0 which is an element of (S) a finite set called the input alphabet ( ) a finite set called the output alphabet ( ) a transition function (T: S S) mapping a state and the input alphabet to the next

state

an output function (G : S ) mapping each state to the output alphabetThe Moore machine is a finite state transducer.

STATE DIAGRAM OF MOORE MACHINE


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STATE TABLE OF MOORE MACHINE

BLOCK DIAGRAM OF MOORE MACHINE

moore machine is a finite state machine , whose output values are determined solely byits current state.


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SIMPLE MOORE SYSTEMS

Simple Moore machine have one input and one output:

edge detector using XOR binary adding machine clocked sequential systems ( a restricted form of Moore machine where the state

changes only when the global clock signal changes )

Most digital electronic systems are designed as clocked sequential systems. Clocked sequential

systems are a restricted form of Moore machine where the state changes only when the globalclock signal changes. Typically the current state is stored in flip-flops, and a global clock signal

is connected to the "clock" input of the flip-flops. Clocked sequential systems are one way to

solve metastability problems. A typical electronic Moore machine includes a combinational

logic chain to decode the current state into the outputs (lambda). The instant the current statechanges, those changes ripple through that chain, and almost instantaneously the output gets

updated. There are design techniques to ensure that no glitches occur on the outputs during that

brief period while those changes are rippling through the chain, but most systems are designed sothat glitches during that brief transition time are ignored or are irrelevant. The outputs then staythe same indefinitely (LEDs stay bright, power stays connected to the motors, solenoids stay

energized, etc.), until the Moore machine changes state again.

State diagramfor an edge detector using XOR.


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The integration of the memory controller onto the die of the microprocessor is not a newconcept. Some microprocessors in the 1990s such as the DEC Alpha 21066 and HP PA-

7300LC had integrated memory controllers, but rather than for performance gains, this

was implemented to reduce the cost of systems by eliminating the need for an external

memory controller.

STATE DIAGRAM OF MEMORY CONTROLLER FSM :

The following figure shows the state diagram of a hypothetical memory controller FSM. Thecontroller is between a processor and a memory chip, interpreting commands from the processorand then generating a control

sequence accordingly. The commands, mem, rw and burst, from the processor constitute

the input signals of the FSM. The mem signal is asserted to high when a memory access isrequired. The rw signal indicates the type of memory access, and its value can be either '1' or '0',for memory read and memory write respectively. The burstsignal is for a special

mode of a memory read operation. If it is asserted, four consecutive read operations will

be performed. The memory chip has two control signals, oe (for output enable) and we

(for write enable), which need to be asserted during the memory read and memory write

respectively. The two output signals of the FSM, oe and we, are connected to the memory

chip's control signals. For comparison purpose, we also add an artificial Mealy output

signal, we me, to the state diagram.

Initially, the FSM is in the idle state, waiting for the mem command from the processor. Oncemem is asserted, the FSM examines the value ofrw and moves to either the read1

state or the write state. These input conditions can be formalized to logic expressions, as

shown in the transition arcs from the idle state:

1) mem' : represents that no memory operation is required.

2)mem rw: represents that a memory read operation is required.

3) mem rw': represents that a memory write operation is required.

The results of these logic expressions are checked at the rising edge of the clock. If the

mem expression is true (i.e., mem is '0'), the FSM stays in the idle state. If the memrw


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expression is true (i.e., both mem and rw are '1'), the FSM moves to the read1 state. Once it isthere, the oe signal is activated, as indicated in the state bubble. On the other hand, if the memrw' expression is true (i.e., mem is '1' and rw is '0'), the FSM moves to the write state andactivates the we signal.

After the FSM reaches the read1 state, the burstsignal is examined at the next rising

edge of the clock. If it is '1', the FSM will go through read2, read3 and read4 states in

the next three clock cycles and then return to the idle state. Otherwise, the FSM returns to the idlestate. We use the notation "-" to represent the "always true" condition. After the FSM reaches thewrite state, it will return to the idle state at the next rising edge of the clock.

The we_ me signal is asserted only when the FSM is in the idle state and the mem rw'

expression is true. It will be deactivated when the FSM moves away from the idle state


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(i.e., to the write state). It is a Mealy output since its value depends on the state and the

input signals (i.e., mem and rw).

In practice, we usually want to force an FSM into an initial state during system initial-

ization. It is frequently done by an asynchronous reset signal, similar to the asynchronous reset

signal used in a register of a regular sequential circuit. Sometimes a solid dot is used to indicatethis transition, as shown above. This transition is only for system initialization and has no effecton normal FSM operation.

ASM CHART OF MEMORY CONTORLLER

The ASM chart is created from the state diagram.


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TIMING AND PERFORMANCE OF AN FSM

Operation of a synchronous FSM

While a state diagram or an ASM chart shows all the states and transitions, it does not provideinformation about when a transition takes place. In a synchronous FSM, the state transition iscontrolled by the rising edge of the system clock. Mealy output and Moore output are notdirectly related to the clock but are responding to input or state change. However, since a Mooreoutput depends only on the state, its transition is indirectly synchronized by the clock.

The timing of a synchronous FSM can best be explained by examining the operation of an ASMblock. In an ASM chart, each ASM block represents a state of the FSM. Instead of moving"continuously" from one block to another block, as in a traditional flowchart, the transitionsbetween ASM blocks can occur only at the rising edge of the clock. The operation of an ASMblock transition can be interpreted as follows:

1. At the rising edge of the clock, the FSM enters a new state (and thus a new ASM block).

2. During the clock period, the FSM performs several operations. It activates the Moore outputsignals asserted in this state. It evaluates various Boolean expressions of the decision boxes andactivates the Mealy output signals accordingly.

3. At the next rising edge of the clock (which is the end of the current clock period), theresults of Boolean expressions are examined simultaneously, an exit path is determined, and theFSM enters the designated new ASM block.

A state and its transitions in a state diagram are interpreted in the same manner.

10.3.2 Performance of an FSM

When an FSM is synthesized, the physical components introduce propagation delays. Since theblock diagram of an FSM is almost identical to that of a regular sequential circuit, the timinganalysis of an FSM is similar to that of a regular sequential circuit, as discussed in Section 8.6.The main timing parameters associated with the block diagram of Figure 10.1

are:

Tcq, Tsetup, Thold: the clock-to-q delay, setup time and hold time of the state register.

Tnext(max): the maximal propagation delay of the next-state logic.

Toutput(mo): the propagation delay of output logic for the Moore output. Toutput(me): the propagation delay of output logic for the Mealy output.

As in a regular sequential circuit, the performance of an FSM is characterized by the maximalclock rate (or minimal clock period). The minimal clock period is

Tc = Tcq + Tnext(max) + Tsetup


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Since an FSM is frequently used as the controller, the response of the

output signal is also important. A Moore output is characterized by the

clock-to-output delay, which is

Tco(mo) = Tcq + Toutput(mo)

A Mealy output may respond to the change of a state or an input

signal. The former is characterized by the clock-to-output delay,

similar to the Moore output:

Tco(me) = Tcq + Toutput(me)

The latter is just the propagation delay of Mealy output logic,which is Toutput(me).


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2.6 APPLICATIONS OF FSM

Finite-state machines can model a large number of problems, among which are electronic

design automation, communication protocol design, parsing and other engineering

applications. In biology and artificial intelligence research, state machines or hierarchies of

state machines are sometimes used to describe neurological systems, and in linguistics they

can be used to describe the grammars of natural languages.

2.6.1 HARDWARE APPLICATIONS

In a digital circuit, an FSM may be built using a programmable logic device,a programmable logic controller, logic gates and flip flops or relays. More

specifically, a hardware implementation requires a register to store state variables, a

block of combinational logic which determines the state transition, and a second block

of combinational logic that determines the output of an FSM. One of the classichardware implementations is theRichards controller.

Mealy and Moore machines produce logic with asynchronous output, because there isa propagation delay between the flip-flop and output. This causes slower operating

frequencies in FSM. A Mealy or Moore machine can be convertible to a FSM which

output is directly from a flip-flop, which makes the FSM run at higher frequencies.

This kind of FSM is sometimes called Medvedev FSM. A counter is the simplest form

of this kind of FSM.

2.6.2 SOFTWARE APPLICATIONS


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The following concepts are commonly used to build software applications with finite state

machines:

1) Automata-based programming2) Event driven FSM3) Virtual FSM (VFSM)

1)Automata-based programming:

Automata-based programming is a programming paradigm in

which the program or its part is thought of as a model of a finite state machine (FSM) or any

other (often more complicated) formal automaton (see automata theory). Sometimes a

potentially-infinite set of possible states is introduced, and such a set can have a complicated

structure, not just an enumeration.

FSM-based programming is generally the same, but, formally speaking, doesn't cover all

possible variants as FSM stands for finite state machine and automata-based programmingdoesn't necessarily employ FSMs in the strict sense.

The following properties are key indicators for automata-based programming:

1. The time period of the program's execution is clearly separated down to the steps ofthe automaton. Each of the steps is effectively an execution of a code section (same

for all the steps), which has a single entry point. Such a section can be a function or

other routine, or just a cycle body. The step section might be divided down to

subsection to be executed depending on different states, although this is not

necessary.

2. Any communication between the steps is only possible via the explicitly noted set ofvariables named the state. Between any two steps, the program (or its part created

using the automata-based technique) can not have implicit components of its state,
http://en.wikipedia.org/wiki/Automata-based_programminghttp://en.wikipedia.org/wiki/Event_driven_finite_state_machinehttp://en.wikipedia.org/wiki/Virtual_finite_state_machinehttp://en.wikipedia.org/wiki/Automata-based_programminghttp://en.wikipedia.org/wiki/Automata-based_programminghttp://en.wikipedia.org/wiki/Automata-based_programminghttp://en.wikipedia.org/wiki/Automata-based_programminghttp://en.wikipedia.org/wiki/Virtual_finite_state_machinehttp://en.wikipedia.org/wiki/Event_driven_finite_state_machinehttp://en.wikipedia.org/wiki/Automata-based_programming


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such as local (stack) variables' values, return addresses, the current instruction pointer

etc. That is, the state of the whole program, taken at any two moments of entering the

step of the automaton, can only differ in the values of the variables being considered

as the state of the automaton.

The whole execution of the automata-based code is a (possibly explicit) cycle of the

automaton's steps.

Another reason to use the notion ofautomata-based programming is that the programmer's

style of thinking about the program in this technique is very similar to the style of thinking

used to solve math-related tasks using Turing machine, Markov algorithm etc.

2) Event driven FSM :

In computation, a finite-state machine (FSM) is event

driven if the transition from one state to another is triggered by an event or amessage. This is

in contrast to the parsing-theory origins of the term finite-state machine where the machine is

described as consuming characters or tokens.

Often these machines are implemented as threads or processes communicating with one

another as part of a larger application. For example, a telecommunication protocol is most ofthe time implemented as an event-driven finite-state machine.

3)Virtual finite state machine:

It is a finite state machine (FSM) defined in a virtualenvironment. The VFSM concept provides a software specification method to describe the

behaviour of a control system using assigned names of input control properties and of

output actions.

The VFSM method introduces an execution model and facilitates the idea of an executable

specification. This technology is mainly used in complex machine control, instrumentation

and telecommunication applications.


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MEALY MACHINE APPLICATIONS

Mealy machines provide a rudimentary mathematical model for cipher machines.

Considering the input and output alphabet the Latin alphabet, for example, then a Mealy

machine can be designed that given a string of letters (a sequence of inputs) can process it

into a ciphered string (a sequence of outputs). However, although one could use a Mealy

model to describe the Enigma, the state diagram would be too complex to provide feasible

means of designing complex ciphering machines.

MOORE MACHINE APPLICATIONS

edge detector using XOR binary adding machine clocked sequential systems ( a restricted form of Moore machine where the state

changes only when the global clock signal changes )

Moore and Mealy machines are two methods of implementing a Finite State Machineor FSM. FSMs are widely used in integrated circuits for implementing simple

functions to complex algorithms.

Any function that is inherently state-dependent will require an FSM implementationin hardware, e.g. Serial Bus Transfer protocols, like USB and power management

applications.

Moore machines are generally preferred in RTL, since they are timing friendly. Atestbench can use either.


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CHAPTER 3

HARDWARE AND SOFTWARE

REQUIREMENTS


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3 HARDWARE AND SOFTWARE REQUIREMENTS

3. 1 IMPLEMENTATION OF MEMORY CONTROLLER FSM USING

MATLAB

3.1.1 MATLAB

MATLAB (matrix laboratory) is a numerical computing environment and fourth-generation

programming language. Developed by Math Works. MATLAB allows matrix manipulations,

plotting of functions and data, implementation of algorithms, creation of user interfaces, and

interfacing with programs written in other languages, including C, CR++, Java, and

FORTRAN.

MATLAB is a commercial software package written by The Math works,

Inc, sometimes called TMW. Quoting from their web page: "Numeric computation, technical

graphics and visualization, and an intuitive programming language for applications in

engineering and science."

MATLAB is a complete environment for high-level programming, as well

as interactive data analysis. MATLAB excels at numerical computations, especially when

dealing with vectors or matrices of data. Symbolic math is available through an add-on

toolbox that uses a MuPAD kernel.

MATLAB is a programming environment for algorithm development, data

analysis, visualization, and numerical computation. Using MATLAB, you can solve technical

computing problems faster than with traditional programming languages, such as C, C++, and

FORTRAN.

You can use MATLAB in a wide range of applications, including signal

and image processing, communications, control design, test and measurement, financial

modeling and analysis, and computational biology. For a million engineers and scientists in

industry and academia, MATLAB is the language of technical computing. There are many

add-on toolboxes that extend MATLAB to specific areas of functionality, such as statistics,

finance, signal processing, image processing, bioinformatics, etc.


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3.1.2 SIMULINK

Simulink is a graphical, drag and drop environment for building simple andcomplex signal and system dynamic simulations.

Simulink is a software package for modeling, simulating, and analyzing dynamicalsystems.

Simulink is an extension to Matlab that allows engineers to rapidly and accuratelybuild computer models of dynamical systems using block diagram notation.

Simulink

is an environment for multidomain simulation and Model-Based Design for

dynamic and embedded systems. It provides an interactive graphical environment and a

customizable set of block libraries that let you design, simulate, implement, and test a varietyof time-varying systems, including communications, controls, signal processing, video

processing, and image processing.

Add-on products extend Simulink software to multiple modeling domains, as well as provide

tools for design, implementation, and verification and validation tasks.

Simulink is integrated with MATLAB, providing immediate access to an extensive range of

tools that let you develop algorithms, analyze and visualize simulations, create batch

processing scripts, customize the modeling environment, and define signal, parameter, andtest data.


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Key Features

Extensive and expandable libraries of predefined blocks Interactive graphical editor for assembling and managing intuitive block diagrams Ability to manage complex designs by segmenting models into hierarchies of design

components

Model Explorer to navigate, create, configure, and search all signals, parameters,properties, and generated code associated with your model

Application programming interfaces (APIs) that let you connect with other simulationprograms and incorporate hand-written code

MATLAB Function blocks for bringing MATLAB algorithms into Simulink andembedded system implementations

Simulation modes (Normal, Accelerator, and Rapid Accelerator) for runningsimulations interpretively or at compiled C-code speeds using fixed- or variable-step solvers

Graphical debugger and profiler to examine simulation results and then diagnoseperformance and unexpected behavior in your design

Full access to MATLAB for analyzing and visualizing results, customizing themodeling environment, and defining signal, parameter, and test data

Model analysis and diagnostics tools to ensure model consistency and identifymodeling errors

You can construct a model by assembling design components, each of which could be a

separate model.

State flow is an interactive design tool for modeling and simulating complex reactive

systems. Tightly integrated with Simulink and MATLAB, State flow provides Simulink users

with an elegant solution for designing embedded systems by giving them an efficient way to

incorporate complex control and supervisory logic within their Simulink models. With State

flow, you can quickly develop graphical models of event-driven systems using finite state

machine theory, state chart formalisms, and flow diagram notation. Together, State flow and

Simulink serve as an executable specification and virtual prototype of your system design.


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3.1.2.1 Getting Started

To start a Simulink session, we need to bring up MATLAB program first and then from

MATLAB command window, enter: >> simulink

Fig 3.1 Simulink library window

To start a model, click on the NEW FILE ICON in the screenshot above. Alternately, you

may use key strokes CTRL+N. A new window will appear on the screen. We can construct

and simulate a model in this window.

3.1.2.2 Steps for creating a simple model

STEP 1: Creating Blocks

From BLOCK SET CATEGORIES section of the SIMULINK LIBRARY BROWSER

window, click on the "+" sign next to the Simulink group to expand the tree and select

Sources. A set of blocks will appear in the BLOCKSET group. Click on the SineWave block and drag it to the workspace window.


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Continue to build your model by adding more components like aScope from Sinks library,

an Integrator block from Continuous library, and a Mux block from Signal

Routing library. To move the blocks around, simply click on it and drag it to a desired

location.You may remove (delete) a block by simply clicking on it and use the DEL key or

keys combination CTRL-X.

STEP 2: Making Connections

To establish connections between the blocks, move the cursor to the output port represented

by ">" sign on the block. Once placed at a port, the cursor will turn into a cross "+" enabling

you to make connection between blocks. To make a connection: left-click while holding

down the control key (on your keyboard) and drag from source port to a destination port. The

connected model is shown below.

Fig 3.2 Connected model

A sine signal is generated by the Sine Wave block (a source) and is displayed by the scope.

The integrated sine signal is sent to scope for display along with the original signal from the

source via the Mux, whose function is to multiplex signals in form of scalar, vector, or matrix

into a bus.

STEP 3: Running Simulation

You now may run the simulation of the simple system above by clicking on the play

button . Alternately, you may use keystrokes CTRL+T, or choose Start submenu (under

Simulation menu).Double click on the Scope block to display of the scope.


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3.1.3 Xilinx

Xilinx ISEis a software tool produced by Xilinx for synthesis and analysis of HDL designs,

which enables the developer to synthesize ("compile") their designs, perform timing analysis,

examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the

target device with the programmer.

Xilinx design solutions continue to lower overall design costs with new technology and faster

performance than any other PLD solution. Achieve greater system-level design productivity

and bring products to production faster with breakthrough technologies in the Xilinx ISE

Design Suite. Built on methodologies to enable team design, power optimization, and to

simplify IP integration, the ISE Design Suite unlocks full potential of Xilinx Targeted Design

Platforms with configurations for logic, embedded, and DSP designsall available with

tightly integrated design flows.

3.1.3.1 Hardware Description Language

In electronics, a hardware description language or HDL is any language from a class of

computer languages, specification languages, or modeling languages for formal

description and design of electronic circuits, and most commonly, digital logic. It can

describe the circuit's operation, its design and organization, and tests to verify its

operation by means of simulation.

HDLs are used to write executable specifications for hardware. A program designed to

implement the underlying semantics of the language statements and simulate the progress

of time provides the hardware designer with the ability to model a piece of hardware

before it is created physically. It is this executability that gives HDLs the illusion of being

programming languages, when they are more precisely classified as specification

languages or modeling languages. Simulators capable of supporting discrete-event

(digital) and continuous-time (analog) modeling exist, and HDLs targeted for each are

available.


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3.1.4 Verilog

In the semiconductor and electronic design industry, Verilog is a hardware description

language (HDL) used to model electronic systems. Verilog HDL is most commonly used in

the design, verification, and implementation of digital logic chips at the register-transfer levelof abstraction. It is also used in the verification of analog and circuits. Hardware description

languages such as Verilog differ from software programming languages because they include

ways of describing the propagation of time and signal dependencies.A Verilog design

consists of a hierarchy of modules. Modules encapsulate design hierarchy, and communicate

with other modules through a set of declared input, output, and bidirectional ports.

CHAPTER 4


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IMPLEMENTATION OF FSM USING SIMULINK


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4. IMPLEMENTATION OF FSM USING SIMULINK

4.1 MAIN BLOCK DIAGRAM IN SIMULINK


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4.2 MEALY BLOCK DIAGRAM IN SIMULINK

OUTPUT :


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4.3 MOORE BLOCK DIAGRAM IN SIMULINK

OUTPUT :


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CHAPTER 5

RESULTS


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5. RESULTS

5.1 CODING

5.1.1 MEALY MACHINE CODE

function Z = mealy_fsm(A)

% Mealy State Machine

% y = f(x,u) :

% all actions are condition actions and

% outputs are function of state and input

persistent mealy_state_reg;

if isempty(mealy_state_reg)

mealy_state_reg = fi(0, 0, 2, 0);

end

S1 = 0;

S2 = 1;

S3 = 2;

S4 = 3;

% switch to new state based on the value state register

switch uint8(mealy_state_reg)

case S1,

% value of output 'Z' depends both on state and inputs

if (A)

Z = true;

mealy_state_reg(1) = S1;


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else

Z = false;


end

case S2,

if (A)

Z = false;


else

Z = true;


end

case S3,

if (A)

Z = false;


else

Z = true;


end

case S4,

if (A)

Z = true;


else


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Z = false;


end

otherwise,

Z = false;

end

5.1.2 MOORE MACHINE CODE

function Z = moore_fsm(A)

% Moore State Machine

% y = f(x) :

% all actions are state actions and

% outputs are pure functions of state only

% using persistent keyword to model state registers in hardware

persistent moore_state_reg;

if isempty(moore_state_reg)

moore_state_reg = fi(0, 0, 2, 0);

end

S1 = 0;

S2 = 1;

S3 = 2;

S4 = 3;

% switch to new state based on the value state register

switch uint8(moore_state_reg)


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end

case S4,

Z = true;

if (~A)

moore_state_reg(1) = S1;

else

moore_state_reg(1) = S3;

end

otherwise,

Z = false;

end

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